gwj / at91sam9263 · Commits

Commit 38482a77f0b3f3147242c1f3eee573c51871b3a5

Authored by Blue Swirl
1 parent 789c91ef

Convert logical operations and umul/smul 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 2 changed files with 43 additions and 24 deletions
target-sparc/op_helper.c
  View file @38482a7
... ... @@ -902,6 +902,23 @@ static uint32_t compute_C_addx_xcc(void)
902 902 }
903 903 #endif
904 904  
  905 +static uint32_t compute_all_logic(void)
  906 +{
  907 + return get_NZ_icc(CC_DST);
  908 +}
  909 +
  910 +static uint32_t compute_C_logic(void)
  911 +{
  912 + return 0;
  913 +}
  914 +
  915 +#ifdef TARGET_SPARC64
  916 +static uint32_t compute_all_logic_xcc(void)
  917 +{
  918 + return get_NZ_xcc(CC_DST);
  919 +}
  920 +#endif
  921 +
905 922 typedef struct CCTable {
906 923 uint32_t (*compute_all)(void); /* return all the flags */
907 924 uint32_t (*compute_c)(void); /* return the C flag */
... ... @@ -912,6 +929,7 @@ static const CCTable icc_table[CC_OP_NB] = {
912 929 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
913 930 [CC_OP_ADD] = { compute_all_add, compute_C_add },
914 931 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
  932 + [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
915 933 };
916 934  
917 935 #ifdef TARGET_SPARC64
... ... @@ -920,6 +938,7 @@ static const CCTable xcc_table[CC_OP_NB] = {
920 938 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
921 939 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
922 940 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
  941 + [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
923 942 };
924 943 #endif
925 944  
... ...
target-sparc/translate.c
  View file @38482a7
... ... @@ -3136,9 +3136,9 @@ static void disas_sparc_insn(DisasContext * dc)
3136 3136 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3137 3137 }
3138 3138 if (xop & 0x10) {
3139   - gen_op_logic_cc(cpu_dst);
3140   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3141   - dc->cc_op = CC_OP_FLAGS;
  3139 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3140 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3141 + dc->cc_op = CC_OP_LOGIC;
3142 3142 }
3143 3143 break;
3144 3144 case 0x2: /* or */
... ... @@ -3149,9 +3149,9 @@ static void disas_sparc_insn(DisasContext * dc)
3149 3149 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3150 3150 }
3151 3151 if (xop & 0x10) {
3152   - gen_op_logic_cc(cpu_dst);
3153   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3154   - dc->cc_op = CC_OP_FLAGS;
  3152 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3153 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3154 + dc->cc_op = CC_OP_LOGIC;
3155 3155 }
3156 3156 break;
3157 3157 case 0x3: /* xor */
... ... @@ -3162,9 +3162,9 @@ static void disas_sparc_insn(DisasContext * dc)
3162 3162 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3163 3163 }
3164 3164 if (xop & 0x10) {
3165   - gen_op_logic_cc(cpu_dst);
3166   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3167   - dc->cc_op = CC_OP_FLAGS;
  3165 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3166 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3167 + dc->cc_op = CC_OP_LOGIC;
3168 3168 }
3169 3169 break;
3170 3170 case 0x4: /* sub */
... ... @@ -3195,9 +3195,9 @@ static void disas_sparc_insn(DisasContext * dc)
3195 3195 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
3196 3196 }
3197 3197 if (xop & 0x10) {
3198   - gen_op_logic_cc(cpu_dst);
3199   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3200   - dc->cc_op = CC_OP_FLAGS;
  3198 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3199 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3200 + dc->cc_op = CC_OP_LOGIC;
3201 3201 }
3202 3202 break;
3203 3203 case 0x6: /* orn */
... ... @@ -3208,9 +3208,9 @@ static void disas_sparc_insn(DisasContext * dc)
3208 3208 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
3209 3209 }
3210 3210 if (xop & 0x10) {
3211   - gen_op_logic_cc(cpu_dst);
3212   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3213   - dc->cc_op = CC_OP_FLAGS;
  3211 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3212 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3213 + dc->cc_op = CC_OP_LOGIC;
3214 3214 }
3215 3215 break;
3216 3216 case 0x7: /* xorn */
... ... @@ -3222,9 +3222,9 @@ static void disas_sparc_insn(DisasContext * dc)
3222 3222 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3223 3223 }
3224 3224 if (xop & 0x10) {
3225   - gen_op_logic_cc(cpu_dst);
3226   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3227   - dc->cc_op = CC_OP_FLAGS;
  3225 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3226 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3227 + dc->cc_op = CC_OP_LOGIC;
3228 3228 }
3229 3229 break;
3230 3230 case 0x8: /* addx, V9 addc */
... ... @@ -3269,18 +3269,18 @@ static void disas_sparc_insn(DisasContext * dc)
3269 3269 CHECK_IU_FEATURE(dc, MUL);
3270 3270 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3271 3271 if (xop & 0x10) {
3272   - gen_op_logic_cc(cpu_dst);
3273   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3274   - dc->cc_op = CC_OP_FLAGS;
  3272 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3273 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3274 + dc->cc_op = CC_OP_LOGIC;
3275 3275 }
3276 3276 break;
3277 3277 case 0xb: /* smul */
3278 3278 CHECK_IU_FEATURE(dc, MUL);
3279 3279 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3280 3280 if (xop & 0x10) {
3281   - gen_op_logic_cc(cpu_dst);
3282   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3283   - dc->cc_op = CC_OP_FLAGS;
  3281 + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
  3282 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  3283 + dc->cc_op = CC_OP_LOGIC;
3284 3284 }
3285 3285 break;
3286 3286 case 0xc: /* subx, V9 subc */
... ...