gwj / at91sam9263 · Commits

Commit d35527d9f9ca7b0c99de06eb720cb35ee56ac5f6

Authored by blueswir1
1 parent 1f5063fb

Convert CCR and CWP ops to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4086 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 29 additions and 26 deletions
target-sparc/helper.h
  View file @d35527d
... ... @@ -8,6 +8,10 @@ target_ulong TCG_HELPER_PROTO helper_rdpsr(void);
8 8 void TCG_HELPER_PROTO helper_wrpstate(target_ulong new_state);
9 9 void TCG_HELPER_PROTO helper_done(void);
10 10 void TCG_HELPER_PROTO helper_retry(void);
  11 +target_ulong TCG_HELPER_PROTO helper_rdccr(void);
  12 +void TCG_HELPER_PROTO helper_wrccr(target_ulong new_ccr);
  13 +target_ulong TCG_HELPER_PROTO helper_rdcwp(void);
  14 +void TCG_HELPER_PROTO helper_wrcwp(target_ulong new_cwp);
11 15 target_ulong TCG_HELPER_PROTO helper_array8(target_ulong pixel_addr,
12 16 target_ulong cubesize);
13 17 target_ulong TCG_HELPER_PROTO helper_alignaddr(target_ulong addr,
... ...
target-sparc/op.c
  View file @d35527d
... ... @@ -258,28 +258,6 @@ void OPPROTO op_restore(void)
258 258 FORCE_RET();
259 259 }
260 260 #else
261   -void OPPROTO op_rdccr(void)
262   -{
263   - T0 = GET_CCR(env);
264   -}
265   -
266   -void OPPROTO op_wrccr(void)
267   -{
268   - PUT_CCR(env, T0);
269   -}
270   -
271   -// CWP handling is reversed in V9, but we still use the V8 register
272   -// order.
273   -void OPPROTO op_rdcwp(void)
274   -{
275   - T0 = GET_CWP64(env);
276   -}
277   -
278   -void OPPROTO op_wrcwp(void)
279   -{
280   - PUT_CWP64(env, T0);
281   -}
282   -
283 261 /* XXX: use another pointer for %iN registers to avoid slow wrapping
284 262 handling ? */
285 263 void OPPROTO op_save(void)
... ...
target-sparc/op_helper.c
  View file @d35527d
... ... @@ -1636,6 +1636,27 @@ target_ulong helper_rdpsr(void)
1636 1636 }
1637 1637  
1638 1638 #else
  1639 +target_ulong helper_rdccr(void)
  1640 +{
  1641 + return GET_CCR(env);
  1642 +}
  1643 +
  1644 +void helper_wrccr(target_ulong new_ccr)
  1645 +{
  1646 + PUT_CCR(env, new_ccr);
  1647 +}
  1648 +
  1649 +// CWP handling is reversed in V9, but we still use the V8 register
  1650 +// order.
  1651 +target_ulong helper_rdcwp(void)
  1652 +{
  1653 + return GET_CWP64(env);
  1654 +}
  1655 +
  1656 +void helper_wrcwp(target_ulong new_cwp)
  1657 +{
  1658 + PUT_CWP64(env, new_cwp);
  1659 +}
1639 1660  
1640 1661 // This function uses non-native bit order
1641 1662 #define GET_FIELD(X, FROM, TO) \
... ...
target-sparc/translate.c
  View file @d35527d
... ... @@ -2023,7 +2023,7 @@ static void disas_sparc_insn(DisasContext * dc)
2023 2023 break;
2024 2024 #ifdef TARGET_SPARC64
2025 2025 case 0x2: /* V9 rdccr */
2026   - gen_op_rdccr();
  2026 + tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
2027 2027 gen_movl_T0_reg(rd);
2028 2028 break;
2029 2029 case 0x3: /* V9 rdasi */
... ... @@ -2205,7 +2205,7 @@ static void disas_sparc_insn(DisasContext * dc)
2205 2205 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2206 2206 break;
2207 2207 case 9: // cwp
2208   - gen_op_rdcwp();
  2208 + tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
2209 2209 break;
2210 2210 case 10: // cansave
2211 2211 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
... ... @@ -3113,7 +3113,7 @@ static void disas_sparc_insn(DisasContext * dc)
3113 3113 #else
3114 3114 case 0x2: /* V9 wrccr */
3115 3115 gen_op_xor_T1_T0();
3116   - gen_op_wrccr();
  3116 + tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
3117 3117 break;
3118 3118 case 0x3: /* V9 wrasi */
3119 3119 gen_op_xor_T1_T0();
... ... @@ -3322,7 +3322,7 @@ static void disas_sparc_insn(DisasContext * dc)
3322 3322 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3323 3323 break;
3324 3324 case 9: // cwp
3325   - gen_op_wrcwp();
  3325 + tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
3326 3326 break;
3327 3327 case 10: // cansave
3328 3328 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
... ...