gwj / at91sam9263 · Commits

Commit 1f5063fb9756805efcd8c5a438ab747f36f796d9

Authored by blueswir1
1 parent eb24dadd

Convert array8/16/32 and alignaddr to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 45 additions and 52 deletions
target-sparc/helper.h
  View file @1f5063f
... ... @@ -8,6 +8,10 @@ target_ulong TCG_HELPER_PROTO helper_rdpsr(void);
8 8 void TCG_HELPER_PROTO helper_wrpstate(target_ulong new_state);
9 9 void TCG_HELPER_PROTO helper_done(void);
10 10 void TCG_HELPER_PROTO helper_retry(void);
  11 +target_ulong TCG_HELPER_PROTO helper_array8(target_ulong pixel_addr,
  12 + target_ulong cubesize);
  13 +target_ulong TCG_HELPER_PROTO helper_alignaddr(target_ulong addr,
  14 + target_ulong offset);
11 15 target_ulong TCG_HELPER_PROTO helper_popc(target_ulong val);
12 16 void TCG_HELPER_PROTO helper_ldf_asi(target_ulong addr, int asi, int size,
13 17 int rd);
... ...
target-sparc/op.c
  View file @1f5063f
... ... @@ -568,54 +568,6 @@ void OPPROTO op_restored(void)
568 568 #endif
569 569  
570 570 #ifdef TARGET_SPARC64
571   -// This function uses non-native bit order
572   -#define GET_FIELD(X, FROM, TO) \
573   - ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
574   -
575   -// This function uses the order in the manuals, i.e. bit 0 is 2^0
576   -#define GET_FIELD_SP(X, FROM, TO) \
577   - GET_FIELD(X, 63 - (TO), 63 - (FROM))
578   -
579   -void OPPROTO op_array8()
580   -{
581   - T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
582   - (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
583   - (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
584   - (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
585   - (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
586   - (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12);
587   -}
588   -
589   -void OPPROTO op_array16()
590   -{
591   - T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
592   - (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
593   - (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
594   - (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
595   - (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
596   - (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1;
597   -}
598   -
599   -void OPPROTO op_array32()
600   -{
601   - T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
602   - (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
603   - (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
604   - (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
605   - (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
606   - (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2;
607   -}
608   -
609   -void OPPROTO op_alignaddr()
610   -{
611   - uint64_t tmp;
612   -
613   - tmp = T0 + T1;
614   - env->gsr &= ~7ULL;
615   - env->gsr |= tmp & 7ULL;
616   - T0 = tmp & ~7ULL;
617   -}
618   -
619 571 void OPPROTO op_faligndata()
620 572 {
621 573 uint64_t tmp;
... ...
target-sparc/op_helper.c
  View file @1f5063f
... ... @@ -1637,6 +1637,37 @@ target_ulong helper_rdpsr(void)
1637 1637  
1638 1638 #else
1639 1639  
  1640 +// This function uses non-native bit order
  1641 +#define GET_FIELD(X, FROM, TO) \
  1642 + ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
  1643 +
  1644 +// This function uses the order in the manuals, i.e. bit 0 is 2^0
  1645 +#define GET_FIELD_SP(X, FROM, TO) \
  1646 + GET_FIELD(X, 63 - (TO), 63 - (FROM))
  1647 +
  1648 +target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
  1649 +{
  1650 + return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
  1651 + (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
  1652 + (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
  1653 + (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
  1654 + (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
  1655 + (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
  1656 + (((pixel_addr >> 55) & 1) << 4) |
  1657 + (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
  1658 + GET_FIELD_SP(pixel_addr, 11, 12);
  1659 +}
  1660 +
  1661 +target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
  1662 +{
  1663 + uint64_t tmp;
  1664 +
  1665 + tmp = addr + offset;
  1666 + env->gsr &= ~7ULL;
  1667 + env->gsr |= tmp & 7ULL;
  1668 + return tmp & ~7ULL;
  1669 +}
  1670 +
1640 1671 target_ulong helper_popc(target_ulong val)
1641 1672 {
1642 1673 return ctpop64(val);
... ...
target-sparc/translate.c
  View file @1f5063f
... ... @@ -3515,25 +3515,31 @@ static void disas_sparc_insn(DisasContext * dc)
3515 3515 case 0x010: /* VIS I array8 */
3516 3516 gen_movl_reg_T0(rs1);
3517 3517 gen_movl_reg_T1(rs2);
3518   - gen_op_array8();
  3518 + tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
  3519 + cpu_T[1]);
3519 3520 gen_movl_T0_reg(rd);
3520 3521 break;
3521 3522 case 0x012: /* VIS I array16 */
3522 3523 gen_movl_reg_T0(rs1);
3523 3524 gen_movl_reg_T1(rs2);
3524   - gen_op_array16();
  3525 + tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
  3526 + cpu_T[1]);
  3527 + tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
3525 3528 gen_movl_T0_reg(rd);
3526 3529 break;
3527 3530 case 0x014: /* VIS I array32 */
3528 3531 gen_movl_reg_T0(rs1);
3529 3532 gen_movl_reg_T1(rs2);
3530   - gen_op_array32();
  3533 + tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
  3534 + cpu_T[1]);
  3535 + tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
3531 3536 gen_movl_T0_reg(rd);
3532 3537 break;
3533 3538 case 0x018: /* VIS I alignaddr */
3534 3539 gen_movl_reg_T0(rs1);
3535 3540 gen_movl_reg_T1(rs2);
3536   - gen_op_alignaddr();
  3541 + tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
  3542 + cpu_T[1]);
3537 3543 gen_movl_T0_reg(rd);
3538 3544 break;
3539 3545 case 0x019: /* VIS II bmask */
... ...