gwj / at91sam9263 · Commits

Commit d077b6f759d6758e0d2a80f053448f152ca2ba6d

Authored by ths
1 parent d297f464

Make bcond and btarget TCG registers. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4805 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 43 additions and 73 deletions
target-mips/translate.c
  View file @d077b6f
... ... @@ -423,7 +423,7 @@ enum {
423 423 };
424 424  
425 425 /* global register indices */
426   -static TCGv cpu_env, current_fpu;
  426 +static TCGv cpu_env, bcond, btarget, current_fpu;
427 427  
428 428 /* FPU TNs, global for now. */
429 429 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
... ... @@ -532,8 +532,7 @@ typedef struct DisasContext {
532 532  
533 533 enum {
534 534 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
535   - * exception condition
536   - */
  535 + * exception condition */
537 536 BS_STOP = 1, /* We want to stop translation for any reason */
538 537 BS_BRANCH = 2, /* We reached a branch condition */
539 538 BS_EXCP = 3, /* We reached an exception condition */
... ... @@ -823,33 +822,6 @@ static inline void gen_save_pc(target_ulong pc)
823 822 tcg_temp_free(r_tmp);
824 823 }
825 824  
826   -static inline void gen_breg_pc(void)
827   -{
828   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
829   -
830   - tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
831   - tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, active_tc.PC));
832   - tcg_temp_free(r_tmp);
833   -}
834   -
835   -static inline void gen_save_btarget(target_ulong btarget)
836   -{
837   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
838   -
839   - tcg_gen_movi_tl(r_tmp, btarget);
840   - tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
841   - tcg_temp_free(r_tmp);
842   -}
843   -
844   -static always_inline void gen_save_breg_target(int reg)
845   -{
846   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
847   -
848   - gen_load_gpr(r_tmp, reg);
849   - tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
850   - tcg_temp_free(r_tmp);
851   -}
852   -
853 825 static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
854 826 {
855 827 #if defined MIPS_DEBUG_DISAS
... ... @@ -875,7 +847,7 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
875 847 case MIPS_HFLAG_BC:
876 848 case MIPS_HFLAG_BL:
877 849 case MIPS_HFLAG_B:
878   - gen_save_btarget(ctx->btarget);
  850 + tcg_gen_movi_tl(btarget, ctx->btarget);
879 851 break;
880 852 }
881 853 }
... ... @@ -2505,7 +2477,7 @@ static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong des
2505 2477 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2506 2478 int rs, int rt, int32_t offset)
2507 2479 {
2508   - target_ulong btarget = -1;
  2480 + target_ulong btgt = -1;
2509 2481 int blink = 0;
2510 2482 int bcond = 0;
2511 2483 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
... ... @@ -2535,7 +2507,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2535 2507 gen_load_gpr(t1, rt);
2536 2508 bcond = 1;
2537 2509 }
2538   - btarget = ctx->pc + 4 + offset;
  2510 + btgt = ctx->pc + 4 + offset;
2539 2511 break;
2540 2512 case OPC_BGEZ:
2541 2513 case OPC_BGEZAL:
... ... @@ -2554,12 +2526,12 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2554 2526 gen_load_gpr(t0, rs);
2555 2527 bcond = 1;
2556 2528 }
2557   - btarget = ctx->pc + 4 + offset;
  2529 + btgt = ctx->pc + 4 + offset;
2558 2530 break;
2559 2531 case OPC_J:
2560 2532 case OPC_JAL:
2561 2533 /* Jump to immediate */
2562   - btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
  2534 + btgt = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
2563 2535 break;
2564 2536 case OPC_JR:
2565 2537 case OPC_JALR:
... ... @@ -2571,7 +2543,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2571 2543 generate_exception(ctx, EXCP_RI);
2572 2544 goto out;
2573 2545 }
2574   - gen_save_breg_target(rs);
  2546 + gen_load_gpr(btarget, rs);
2575 2547 break;
2576 2548 default:
2577 2549 MIPS_INVAL("branch/jump");
... ... @@ -2625,12 +2597,12 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2625 2597 goto out;
2626 2598 case OPC_J:
2627 2599 ctx->hflags |= MIPS_HFLAG_B;
2628   - MIPS_DEBUG("j " TARGET_FMT_lx, btarget);
  2600 + MIPS_DEBUG("j " TARGET_FMT_lx, btgt);
2629 2601 break;
2630 2602 case OPC_JAL:
2631 2603 blink = 31;
2632 2604 ctx->hflags |= MIPS_HFLAG_B;
2633   - MIPS_DEBUG("jal " TARGET_FMT_lx, btarget);
  2605 + MIPS_DEBUG("jal " TARGET_FMT_lx, btgt);
2634 2606 break;
2635 2607 case OPC_JR:
2636 2608 ctx->hflags |= MIPS_HFLAG_BR;
... ... @@ -2651,80 +2623,80 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2651 2623 case OPC_BEQ:
2652 2624 gen_op_eq(t0, t1);
2653 2625 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2654   - regnames[rs], regnames[rt], btarget);
  2626 + regnames[rs], regnames[rt], btgt);
2655 2627 goto not_likely;
2656 2628 case OPC_BEQL:
2657 2629 gen_op_eq(t0, t1);
2658 2630 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2659   - regnames[rs], regnames[rt], btarget);
  2631 + regnames[rs], regnames[rt], btgt);
2660 2632 goto likely;
2661 2633 case OPC_BNE:
2662 2634 gen_op_ne(t0, t1);
2663 2635 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2664   - regnames[rs], regnames[rt], btarget);
  2636 + regnames[rs], regnames[rt], btgt);
2665 2637 goto not_likely;
2666 2638 case OPC_BNEL:
2667 2639 gen_op_ne(t0, t1);
2668 2640 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2669   - regnames[rs], regnames[rt], btarget);
  2641 + regnames[rs], regnames[rt], btgt);
2670 2642 goto likely;
2671 2643 case OPC_BGEZ:
2672 2644 gen_op_gez(t0);
2673   - MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2645 + MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2674 2646 goto not_likely;
2675 2647 case OPC_BGEZL:
2676 2648 gen_op_gez(t0);
2677   - MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2649 + MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2678 2650 goto likely;
2679 2651 case OPC_BGEZAL:
2680 2652 gen_op_gez(t0);
2681   - MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2653 + MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2682 2654 blink = 31;
2683 2655 goto not_likely;
2684 2656 case OPC_BGEZALL:
2685 2657 gen_op_gez(t0);
2686 2658 blink = 31;
2687   - MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2659 + MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2688 2660 goto likely;
2689 2661 case OPC_BGTZ:
2690 2662 gen_op_gtz(t0);
2691   - MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2663 + MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2692 2664 goto not_likely;
2693 2665 case OPC_BGTZL:
2694 2666 gen_op_gtz(t0);
2695   - MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2667 + MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2696 2668 goto likely;
2697 2669 case OPC_BLEZ:
2698 2670 gen_op_lez(t0);
2699   - MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2671 + MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2700 2672 goto not_likely;
2701 2673 case OPC_BLEZL:
2702 2674 gen_op_lez(t0);
2703   - MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2675 + MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2704 2676 goto likely;
2705 2677 case OPC_BLTZ:
2706 2678 gen_op_ltz(t0);
2707   - MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2679 + MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2708 2680 goto not_likely;
2709 2681 case OPC_BLTZL:
2710 2682 gen_op_ltz(t0);
2711   - MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2683 + MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2712 2684 goto likely;
2713 2685 case OPC_BLTZAL:
2714 2686 gen_op_ltz(t0);
2715 2687 blink = 31;
2716   - MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2688 + MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2717 2689 not_likely:
2718 2690 ctx->hflags |= MIPS_HFLAG_BC;
2719   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
  2691 + tcg_gen_trunc_tl_i32(bcond, t0);
2720 2692 break;
2721 2693 case OPC_BLTZALL:
2722 2694 gen_op_ltz(t0);
2723 2695 blink = 31;
2724   - MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
  2696 + MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2725 2697 likely:
2726 2698 ctx->hflags |= MIPS_HFLAG_BL;
2727   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
  2699 + tcg_gen_trunc_tl_i32(bcond, t0);
2728 2700 break;
2729 2701 default:
2730 2702 MIPS_INVAL("conditional branch/jump");
... ... @@ -2733,9 +2705,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2733 2705 }
2734 2706 }
2735 2707 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
2736   - blink, ctx->hflags, btarget);
  2708 + blink, ctx->hflags, btgt);
2737 2709  
2738   - ctx->btarget = btarget;
  2710 + ctx->btarget = btgt;
2739 2711 if (blink > 0) {
2740 2712 tcg_gen_movi_tl(t0, ctx->pc + 8);
2741 2713 gen_store_gpr(t0, blink);
... ... @@ -5789,7 +5761,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5789 5761 opn = "bc1tl";
5790 5762 likely:
5791 5763 ctx->hflags |= MIPS_HFLAG_BL;
5792   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
  5764 + tcg_gen_trunc_tl_i32(bcond, t0);
5793 5765 break;
5794 5766 case OPC_BC1FANY2:
5795 5767 {
... ... @@ -5874,7 +5846,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5874 5846 opn = "bc1any4t";
5875 5847 not_likely:
5876 5848 ctx->hflags |= MIPS_HFLAG_BC;
5877   - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
  5849 + tcg_gen_trunc_tl_i32(bcond, t0);
5878 5850 break;
5879 5851 default:
5880 5852 MIPS_INVAL(opn);
... ... @@ -7209,19 +7181,16 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7209 7181  
7210 7182 /* Handle blikely not taken case */
7211 7183 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
7212   - TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL);
7213 7184 int l1 = gen_new_label();
7214 7185  
7215 7186 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
7216   - tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
7217   - tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
7218   - tcg_temp_free(r_tmp);
  7187 + tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
7219 7188 {
7220   - TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
  7189 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
7221 7190  
7222   - tcg_gen_movi_i32(r_tmp2, ctx->hflags & ~MIPS_HFLAG_BMASK);
7223   - tcg_gen_st_i32(r_tmp2, cpu_env, offsetof(CPUState, hflags));
7224   - tcg_temp_free(r_tmp2);
  7191 + tcg_gen_movi_i32(r_tmp, ctx->hflags & ~MIPS_HFLAG_BMASK);
  7192 + tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
  7193 + tcg_temp_free(r_tmp);
7225 7194 }
7226 7195 gen_goto_tb(ctx, 1, ctx->pc + 4);
7227 7196 gen_set_label(l1);
... ... @@ -7818,12 +7787,9 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7818 7787 /* Conditional branch */
7819 7788 MIPS_DEBUG("conditional branch");
7820 7789 {
7821   - TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL);
7822 7790 int l1 = gen_new_label();
7823 7791  
7824   - tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
7825   - tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
7826   - tcg_temp_free(r_tmp);
  7792 + tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
7827 7793 gen_goto_tb(ctx, 1, ctx->pc + 4);
7828 7794 gen_set_label(l1);
7829 7795 gen_goto_tb(ctx, 0, ctx->btarget);
... ... @@ -7832,7 +7798,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7832 7798 case MIPS_HFLAG_BR:
7833 7799 /* unconditional branch to register */
7834 7800 MIPS_DEBUG("branch to register");
7835   - gen_breg_pc();
  7801 + tcg_gen_st_tl(btarget, cpu_env, offsetof(CPUState, active_tc.PC));
7836 7802 tcg_gen_exit_tb(0);
7837 7803 break;
7838 7804 default:
... ... @@ -8125,6 +8091,10 @@ static void mips_tcg_init(void)
8125 8091 return;
8126 8092  
8127 8093 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  8094 + bcond = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  8095 + offsetof(CPUState, bcond), "bcond");
  8096 + btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8097 + offsetof(CPUState, btarget), "btarget");
8128 8098 current_fpu = tcg_global_mem_new(TCG_TYPE_PTR,
8129 8099 TCG_AREG0,
8130 8100 offsetof(CPUState, fpu),
... ...