gwj / at91sam9263 · Commits

Commit ce8536e23f5cc37484f8d56fd81b386f78add542

Authored by blueswir1
1 parent 8911f501

Convert ldf/ldfsr and stf/stfsr to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4101 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 13 additions and 19 deletions
target-sparc/op_mem.h
  View file @ce8536e
@@ -15,22 +15,12 @@ void OPPROTO glue(op_std, MEMSUFFIX)(void) @@ -15,22 +15,12 @@ void OPPROTO glue(op_std, MEMSUFFIX)(void)
15 15
16 #endif /* __i386__ */ 16 #endif /* __i386__ */
17 /*** Floating-point store ***/ 17 /*** Floating-point store ***/
18 -void OPPROTO glue(op_stf, MEMSUFFIX) (void)  
19 -{  
20 - glue(stfl, MEMSUFFIX)(ADDR(T0), FT0);  
21 -}  
22 -  
23 void OPPROTO glue(op_stdf, MEMSUFFIX) (void) 18 void OPPROTO glue(op_stdf, MEMSUFFIX) (void)
24 { 19 {
25 glue(stfq, MEMSUFFIX)(ADDR(T0), DT0); 20 glue(stfq, MEMSUFFIX)(ADDR(T0), DT0);
26 } 21 }
27 22
28 /*** Floating-point load ***/ 23 /*** Floating-point load ***/
29 -void OPPROTO glue(op_ldf, MEMSUFFIX) (void)  
30 -{  
31 - FT0 = glue(ldfl, MEMSUFFIX)(ADDR(T0));  
32 -}  
33 -  
34 void OPPROTO glue(op_lddf, MEMSUFFIX) (void) 24 void OPPROTO glue(op_lddf, MEMSUFFIX) (void)
35 { 25 {
36 DT0 = glue(ldfq, MEMSUFFIX)(ADDR(T0)); 26 DT0 = glue(ldfq, MEMSUFFIX)(ADDR(T0));
target-sparc/translate.c
  View file @ce8536e
@@ -226,9 +226,7 @@ static void gen_op_store_QT0_fpr(unsigned int dst) @@ -226,9 +226,7 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
226 #ifdef __i386__ 226 #ifdef __i386__
227 OP_LD_TABLE(std); 227 OP_LD_TABLE(std);
228 #endif /* __i386__ */ 228 #endif /* __i386__ */
229 -OP_LD_TABLE(stf);  
230 OP_LD_TABLE(stdf); 229 OP_LD_TABLE(stdf);
231 -OP_LD_TABLE(ldf);  
232 OP_LD_TABLE(lddf); 230 OP_LD_TABLE(lddf);
233 #endif 231 #endif
234 232
@@ -4295,12 +4293,15 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4295,12 +4293,15 @@ static void disas_sparc_insn(DisasContext * dc)
4295 switch (xop) { 4293 switch (xop) {
4296 case 0x20: /* load fpreg */ 4294 case 0x20: /* load fpreg */
4297 gen_op_check_align_T0_3(); 4295 gen_op_check_align_T0_3();
4298 - gen_op_ldst(ldf);  
4299 - gen_op_store_FT0_fpr(rd); 4296 + tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
  4297 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  4298 + offsetof(CPUState, fpr[rd]));
4300 break; 4299 break;
4301 case 0x21: /* load fsr */ 4300 case 0x21: /* load fsr */
4302 gen_op_check_align_T0_3(); 4301 gen_op_check_align_T0_3();
4303 - gen_op_ldst(ldf); 4302 + tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
  4303 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  4304 + offsetof(CPUState, ft0));
4304 tcg_gen_helper_0_0(helper_ldfsr); 4305 tcg_gen_helper_0_0(helper_ldfsr);
4305 break; 4306 break;
4306 case 0x22: /* load quad fpreg */ 4307 case 0x22: /* load quad fpreg */
@@ -4422,17 +4423,20 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4422,17 +4423,20 @@ static void disas_sparc_insn(DisasContext * dc)
4422 if (gen_trap_ifnofpu(dc)) 4423 if (gen_trap_ifnofpu(dc))
4423 goto jmp_insn; 4424 goto jmp_insn;
4424 switch (xop) { 4425 switch (xop) {
4425 - case 0x24: 4426 + case 0x24: /* store fpreg */
4426 gen_op_check_align_T0_3(); 4427 gen_op_check_align_T0_3();
4427 - gen_op_load_fpr_FT0(rd);  
4428 - gen_op_ldst(stf); 4428 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  4429 + offsetof(CPUState, fpr[rd]));
  4430 + tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
4429 break; 4431 break;
4430 case 0x25: /* stfsr, V9 stxfsr */ 4432 case 0x25: /* stfsr, V9 stxfsr */
4431 #ifdef CONFIG_USER_ONLY 4433 #ifdef CONFIG_USER_ONLY
4432 gen_op_check_align_T0_3(); 4434 gen_op_check_align_T0_3();
4433 #endif 4435 #endif
4434 tcg_gen_helper_0_0(helper_stfsr); 4436 tcg_gen_helper_0_0(helper_stfsr);
4435 - gen_op_ldst(stf); 4437 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  4438 + offsetof(CPUState, ft0));
  4439 + tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
4436 break; 4440 break;
4437 case 0x26: 4441 case 0x26:
4438 #ifdef TARGET_SPARC64 4442 #ifdef TARGET_SPARC64