gwj / at91sam9263 · Commits

Commit 8911f5019c06693dbca07901bc97423f82a4bcc4

Authored by blueswir1
1 parent e429073d

Fix i32/i64/TL mismatches 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4100 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 149 additions and 148 deletions
target-sparc/translate.c
  View file @8911f50
... ... @@ -52,7 +52,7 @@ static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
52 52 static TCGv cpu_xcc;
53 53 #endif
54 54 /* local register indexes (only used inside old micro ops) */
55   -static TCGv cpu_tmp0;
  55 +static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
56 56  
57 57 typedef struct DisasContext {
58 58 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
... ... @@ -117,81 +117,81 @@ static void disas_sparc_insn(DisasContext * dc);
117 117 /* floating point registers moves */
118 118 static void gen_op_load_fpr_FT0(unsigned int src)
119 119 {
120   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
121   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
  120 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  121 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
122 122 }
123 123  
124 124 static void gen_op_load_fpr_FT1(unsigned int src)
125 125 {
126   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
127   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1));
  126 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  127 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
128 128 }
129 129  
130 130 static void gen_op_store_FT0_fpr(unsigned int dst)
131 131 {
132   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
133   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
  132 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
  133 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
134 134 }
135 135  
136 136 static void gen_op_load_fpr_DT0(unsigned int src)
137 137 {
138   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
139   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
140   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
141   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
  138 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  139 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
  140 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  141 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
142 142 }
143 143  
144 144 static void gen_op_load_fpr_DT1(unsigned int src)
145 145 {
146   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
147   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
148   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
  146 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  147 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
  148 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  149 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
150 150 }
151 151  
152 152 static void gen_op_store_DT0_fpr(unsigned int dst)
153 153 {
154   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
155   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
156   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
157   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
  154 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
  155 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
  156 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
  157 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
158 158 }
159 159  
160 160 #ifdef CONFIG_USER_ONLY
161 161 static void gen_op_load_fpr_QT0(unsigned int src)
162 162 {
163   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
164   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
165   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
166   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
167   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
169   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
170   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
  163 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  164 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
  165 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  166 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
  167 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
  168 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
  169 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
  170 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
171 171 }
172 172  
173 173 static void gen_op_load_fpr_QT1(unsigned int src)
174 174 {
175   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
176   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
177   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
178   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
179   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
180   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
181   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
182   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
  175 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  176 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
  177 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  178 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
  179 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
  180 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
  181 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
  182 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
183 183 }
184 184  
185 185 static void gen_op_store_QT0_fpr(unsigned int dst)
186 186 {
187   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
188   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
189   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
190   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
191   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
192   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
193   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
194   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
  187 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
  188 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
  189 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
  190 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
  191 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
  192 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
  193 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
  194 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
195 195 }
196 196 #endif
197 197  
... ... @@ -233,7 +233,7 @@ OP_LD_TABLE(lddf);
233 233 #endif
234 234  
235 235 #ifdef TARGET_ABI32
236   -#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
  236 +#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
237 237 #else
238 238 #define ABI32_MASK(addr)
239 239 #endif
... ... @@ -294,12 +294,14 @@ static inline void gen_movl_T1_reg(int reg)
294 294  
295 295 static inline void gen_op_movl_T0_env(size_t offset)
296 296 {
297   - tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
  297 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offset);
  298 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
298 299 }
299 300  
300 301 static inline void gen_op_movl_env_T0(size_t offset)
301 302 {
302   - tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
  303 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  304 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offset);
303 305 }
304 306  
305 307 static inline void gen_op_movtl_T0_env(size_t offset)
... ... @@ -361,32 +363,36 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
361 363 // XXX suboptimal
362 364 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
363 365 {
364   - tcg_gen_shri_i32(reg, src, 23);
  366 + tcg_gen_extu_i32_tl(reg, src);
  367 + tcg_gen_shri_tl(reg, reg, 23);
365 368 tcg_gen_andi_tl(reg, reg, 0x1);
366 369 }
367 370  
368 371 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
369 372 {
370   - tcg_gen_shri_i32(reg, src, 22);
  373 + tcg_gen_extu_i32_tl(reg, src);
  374 + tcg_gen_shri_tl(reg, reg, 22);
371 375 tcg_gen_andi_tl(reg, reg, 0x1);
372 376 }
373 377  
374 378 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
375 379 {
376   - tcg_gen_shri_i32(reg, src, 21);
  380 + tcg_gen_extu_i32_tl(reg, src);
  381 + tcg_gen_shri_tl(reg, reg, 21);
377 382 tcg_gen_andi_tl(reg, reg, 0x1);
378 383 }
379 384  
380 385 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
381 386 {
382   - tcg_gen_shri_i32(reg, src, 20);
  387 + tcg_gen_extu_i32_tl(reg, src);
  388 + tcg_gen_shri_tl(reg, reg, 20);
383 389 tcg_gen_andi_tl(reg, reg, 0x1);
384 390 }
385 391  
386 392 static inline void gen_op_exception(int exception)
387 393 {
388   - tcg_gen_movi_i32(cpu_tmp0, exception);
389   - tcg_gen_helper_0_1(raise_exception, cpu_tmp0);
  394 + tcg_gen_movi_i32(cpu_tmp32, exception);
  395 + tcg_gen_helper_0_1(raise_exception, cpu_tmp32);
390 396 }
391 397  
392 398 static inline void gen_cc_clear(void)
... ... @@ -405,14 +411,18 @@ static inline void gen_cc_clear(void)
405 411 */
406 412 static inline void gen_cc_NZ(TCGv dst)
407 413 {
  414 + TCGv r_temp;
408 415 int l1, l2;
409 416  
410 417 l1 = gen_new_label();
411 418 l2 = gen_new_label();
412   - tcg_gen_brcond_i32(TCG_COND_NE, dst, tcg_const_i32(0), l1);
  419 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  420 + tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
  421 + tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
413 422 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
414 423 gen_set_label(l1);
415   - tcg_gen_brcond_i32(TCG_COND_GE, dst, tcg_const_i32(0), l2);
  424 + tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
  425 + tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
416 426 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
417 427 gen_set_label(l2);
418 428 #ifdef TARGET_SPARC64
... ... @@ -437,10 +447,13 @@ static inline void gen_cc_NZ(TCGv dst)
437 447 */
438 448 static inline void gen_cc_C_add(TCGv dst, TCGv src1)
439 449 {
  450 + TCGv r_temp;
440 451 int l1;
441 452  
442 453 l1 = gen_new_label();
443   - tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
  454 + r_temp = tcg_temp_new(TCG_TYPE_TL);
  455 + tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
  456 + tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
444 457 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
445 458 gen_set_label(l1);
446 459 #ifdef TARGET_SPARC64
... ... @@ -472,7 +485,7 @@ static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
472 485 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
473 486 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
474 487 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
475   - tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
  488 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
476 489 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
477 490 gen_set_label(l1);
478 491 #ifdef TARGET_SPARC64
... ... @@ -506,7 +519,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
506 519 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
507 520 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
508 521 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
509   - tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
  522 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
510 523 gen_op_exception(TT_TOVF);
511 524 gen_set_label(l1);
512 525 #ifdef TARGET_SPARC64
... ... @@ -602,10 +615,15 @@ static inline void gen_op_tadd_T1_T0_ccTV(void)
602 615 */
603 616 static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
604 617 {
  618 + TCGv r_temp1, r_temp2;
605 619 int l1;
606 620  
607 621 l1 = gen_new_label();
608   - tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
  622 + r_temp1 = tcg_temp_new(TCG_TYPE_TL);
  623 + r_temp2 = tcg_temp_new(TCG_TYPE_TL);
  624 + tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
  625 + tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
  626 + tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
609 627 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
610 628 gen_set_label(l1);
611 629 #ifdef TARGET_SPARC64
... ... @@ -636,7 +654,7 @@ static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
636 654 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
637 655 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
638 656 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
639   - tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
  657 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
640 658 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
641 659 gen_set_label(l1);
642 660 #ifdef TARGET_SPARC64
... ... @@ -668,7 +686,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
668 686 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
669 687 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
670 688 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
671   - tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
  689 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
672 690 gen_op_exception(TT_TOVF);
673 691 gen_set_label(l1);
674 692 #ifdef TARGET_SPARC64
... ... @@ -746,9 +764,10 @@ static inline void gen_op_mulscc_T1_T0(void)
746 764 if (!(env->y & 1))
747 765 T1 = 0;
748 766 */
749   - tcg_gen_ld_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
750   - tcg_gen_andi_i32(r_temp, r_temp, 0x1);
751   - tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
  767 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
  768 + tcg_gen_extu_i32_tl(r_temp, cpu_tmp32);
  769 + tcg_gen_andi_tl(r_temp, r_temp, 0x1);
  770 + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
752 771 tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
753 772 tcg_gen_br(l2);
754 773 gen_set_label(l1);
... ... @@ -757,11 +776,11 @@ static inline void gen_op_mulscc_T1_T0(void)
757 776  
758 777 // b2 = T0 & 1;
759 778 // env->y = (b2 << 31) | (env->y >> 1);
760   - tcg_gen_shli_i32(r_temp, cpu_T[0], 31);
761   - tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
762   - tcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 1);
763   - tcg_gen_or_i32(cpu_tmp0, cpu_tmp0, r_temp);
764   - tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
  779 + tcg_gen_shli_tl(r_temp, cpu_T[0], 31);
  780 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
  781 + tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
  782 + tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp);
  783 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
765 784  
766 785 // b1 = N ^ V;
767 786 gen_mov_reg_N(cpu_tmp0, cpu_psr);
... ... @@ -791,8 +810,8 @@ static inline void gen_op_umul_T1_T0(void)
791 810 r_temp = tcg_temp_new(TCG_TYPE_I64);
792 811 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
793 812  
794   - tcg_gen_extu_i32_i64(r_temp, cpu_T[1]);
795   - tcg_gen_extu_i32_i64(r_temp2, cpu_T[0]);
  813 + tcg_gen_extu_tl_i64(r_temp, cpu_T[1]);
  814 + tcg_gen_extu_tl_i64(r_temp2, cpu_T[0]);
796 815 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
797 816  
798 817 tcg_gen_shri_i64(r_temp, r_temp2, 32);
... ... @@ -801,7 +820,7 @@ static inline void gen_op_umul_T1_T0(void)
801 820 #ifdef TARGET_SPARC64
802 821 tcg_gen_mov_i64(cpu_T[0], r_temp2);
803 822 #else
804   - tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2);
  823 + tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
805 824 #endif
806 825  
807 826 tcg_gen_discard_i64(r_temp);
... ... @@ -815,8 +834,8 @@ static inline void gen_op_smul_T1_T0(void)
815 834 r_temp = tcg_temp_new(TCG_TYPE_I64);
816 835 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
817 836  
818   - tcg_gen_ext_i32_i64(r_temp, cpu_T[1]);
819   - tcg_gen_ext_i32_i64(r_temp2, cpu_T[0]);
  837 + tcg_gen_ext_tl_i64(r_temp, cpu_T[1]);
  838 + tcg_gen_ext_tl_i64(r_temp2, cpu_T[0]);
820 839 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
821 840  
822 841 tcg_gen_shri_i64(r_temp, r_temp2, 32);
... ... @@ -825,7 +844,7 @@ static inline void gen_op_smul_T1_T0(void)
825 844 #ifdef TARGET_SPARC64
826 845 tcg_gen_mov_i64(cpu_T[0], r_temp2);
827 846 #else
828   - tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2);
  847 + tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
829 848 #endif
830 849  
831 850 tcg_gen_discard_i64(r_temp);
... ... @@ -843,12 +862,12 @@ static inline void gen_op_sdiv_T1_T0(void)
843 862 }
844 863  
845 864 #ifdef TARGET_SPARC64
846   -static inline void gen_trap_ifdivzero_i64(TCGv divisor)
  865 +static inline void gen_trap_ifdivzero_tl(TCGv divisor)
847 866 {
848 867 int l1;
849 868  
850 869 l1 = gen_new_label();
851   - tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
  870 + tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
852 871 gen_op_exception(TT_DIV_ZERO);
853 872 gen_set_label(l1);
854 873 }
... ... @@ -859,9 +878,9 @@ static inline void gen_op_sdivx_T1_T0(void)
859 878  
860 879 l1 = gen_new_label();
861 880 l2 = gen_new_label();
862   - gen_trap_ifdivzero_i64(cpu_T[1]);
863   - tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1);
864   - tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1);
  881 + gen_trap_ifdivzero_tl(cpu_T[1]);
  882 + tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], tcg_const_tl(INT64_MIN), l1);
  883 + tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(-1), l1);
865 884 tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
866 885 tcg_gen_br(l2);
867 886 gen_set_label(l1);
... ... @@ -1018,14 +1037,16 @@ static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
1018 1037 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
1019 1038 unsigned int fcc_offset)
1020 1039 {
1021   - tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
  1040 + tcg_gen_extu_i32_tl(reg, src);
  1041 + tcg_gen_shri_tl(reg, reg, 10 + fcc_offset);
1022 1042 tcg_gen_andi_tl(reg, reg, 0x1);
1023 1043 }
1024 1044  
1025 1045 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1026 1046 unsigned int fcc_offset)
1027 1047 {
1028   - tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
  1048 + tcg_gen_extu_i32_tl(reg, src);
  1049 + tcg_gen_shri_tl(reg, reg, 11 + fcc_offset);
1029 1050 tcg_gen_andi_tl(reg, reg, 0x1);
1030 1051 }
1031 1052  
... ... @@ -1753,41 +1774,37 @@ static inline void gen_swap_asi(int insn)
1753 1774 tcg_const_i32(4), tcg_const_i32(0));
1754 1775 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
1755 1776 tcg_const_i32(4));
1756   - tcg_gen_mov_i32(cpu_T[1], r_temp);
  1777 + tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
1757 1778 tcg_gen_discard_i32(r_asi);
1758 1779 tcg_gen_discard_i32(r_temp);
1759 1780 }
1760 1781  
1761 1782 static inline void gen_ldda_asi(int insn)
1762 1783 {
1763   - TCGv r_dword, r_asi;
  1784 + TCGv r_asi;
1764 1785  
1765   - r_dword = tcg_temp_new(TCG_TYPE_I64);
1766 1786 r_asi = gen_get_asi(insn, cpu_T[0]);
1767   - tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], r_asi,
  1787 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], r_asi,
1768 1788 tcg_const_i32(8), tcg_const_i32(0));
1769   - tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1770   - tcg_gen_shri_i64(r_dword, r_dword, 32);
1771   - tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
  1789 + tcg_gen_andi_i64(cpu_T[0], cpu_tmp64, 0xffffffffULL);
  1790 + tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
  1791 + tcg_gen_andi_i64(cpu_T[1], cpu_tmp64, 0xffffffffULL);
1772 1792 tcg_gen_discard_i32(r_asi);
1773   - tcg_gen_discard_i64(r_dword);
1774 1793 }
1775 1794  
1776 1795 static inline void gen_stda_asi(int insn, int rd)
1777 1796 {
1778   - TCGv r_dword, r_temp, r_asi;
  1797 + TCGv r_temp, r_asi;
1779 1798  
1780   - r_dword = tcg_temp_new(TCG_TYPE_I64);
1781 1799 r_temp = tcg_temp_new(TCG_TYPE_I32);
1782 1800 gen_movl_reg_TN(rd + 1, r_temp);
1783   - tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
  1801 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
1784 1802 r_temp);
1785 1803 r_asi = gen_get_asi(insn, cpu_T[0]);
1786   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi,
  1804 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, r_asi,
1787 1805 tcg_const_i32(8));
1788 1806 tcg_gen_discard_i32(r_asi);
1789 1807 tcg_gen_discard_i32(r_temp);
1790   - tcg_gen_discard_i64(r_dword);
1791 1808 }
1792 1809  
1793 1810 static inline void gen_cas_asi(int insn, int rd)
... ... @@ -1805,15 +1822,13 @@ static inline void gen_cas_asi(int insn, int rd)
1805 1822  
1806 1823 static inline void gen_casx_asi(int insn, int rd)
1807 1824 {
1808   - TCGv r_val1, r_asi;
  1825 + TCGv r_asi;
1809 1826  
1810   - r_val1 = tcg_temp_new(TCG_TYPE_I64);
1811   - gen_movl_reg_TN(rd, r_val1);
  1827 + gen_movl_reg_TN(rd, cpu_tmp64);
1812 1828 r_asi = gen_get_asi(insn, cpu_T[0]);
1813   - tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
  1829 + tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], cpu_tmp64, cpu_T[1],
1814 1830 r_asi);
1815 1831 tcg_gen_discard_i32(r_asi);
1816   - tcg_gen_discard_i32(r_val1);
1817 1832 }
1818 1833  
1819 1834 #elif !defined(CONFIG_USER_ONLY)
... ... @@ -1821,27 +1836,21 @@ static inline void gen_casx_asi(int insn, int rd)
1821 1836 static inline void gen_ld_asi(int insn, int size, int sign)
1822 1837 {
1823 1838 int asi;
1824   - TCGv r_dword;
1825 1839  
1826   - r_dword = tcg_temp_new(TCG_TYPE_I64);
1827 1840 asi = GET_FIELD(insn, 19, 26);
1828   - tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
  1841 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
1829 1842 tcg_const_i32(size), tcg_const_i32(sign));
1830   - tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1831   - tcg_gen_discard_i64(r_dword);
  1843 + tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
1832 1844 }
1833 1845  
1834 1846 static inline void gen_st_asi(int insn, int size)
1835 1847 {
1836 1848 int asi;
1837   - TCGv r_dword;
1838 1849  
1839   - r_dword = tcg_temp_new(TCG_TYPE_I64);
1840   - tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
  1850 + tcg_gen_extu_tl_i64(cpu_tmp64, cpu_T[1]);
1841 1851 asi = GET_FIELD(insn, 19, 26);
1842   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
  1852 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
1843 1853 tcg_const_i32(size));
1844   - tcg_gen_discard_i64(r_dword);
1845 1854 }
1846 1855  
1847 1856 static inline void gen_swap_asi(int insn)
... ... @@ -1855,38 +1864,33 @@ static inline void gen_swap_asi(int insn)
1855 1864 tcg_const_i32(4), tcg_const_i32(0));
1856 1865 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi),
1857 1866 tcg_const_i32(4));
1858   - tcg_gen_mov_i32(cpu_T[1], r_temp);
  1867 + tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
1859 1868 tcg_gen_discard_i32(r_temp);
1860 1869 }
1861 1870  
1862 1871 static inline void gen_ldda_asi(int insn)
1863 1872 {
1864 1873 int asi;
1865   - TCGv r_dword;
1866 1874  
1867   - r_dword = tcg_temp_new(TCG_TYPE_I64);
1868 1875 asi = GET_FIELD(insn, 19, 26);
1869   - tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
  1876 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
1870 1877 tcg_const_i32(8), tcg_const_i32(0));
1871   - tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1872   - tcg_gen_shri_i64(r_dword, r_dword, 32);
1873   - tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1874   - tcg_gen_discard_i64(r_dword);
  1878 + tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
  1879 + tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
  1880 + tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
1875 1881 }
1876 1882  
1877 1883 static inline void gen_stda_asi(int insn, int rd)
1878 1884 {
1879 1885 int asi;
1880   - TCGv r_dword, r_temp;
  1886 + TCGv r_temp;
1881 1887  
1882   - r_dword = tcg_temp_new(TCG_TYPE_I64);
1883 1888 r_temp = tcg_temp_new(TCG_TYPE_I32);
1884 1889 gen_movl_reg_TN(rd + 1, r_temp);
1885   - tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], r_temp);
  1890 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], r_temp);
1886 1891 asi = GET_FIELD(insn, 19, 26);
1887   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
  1892 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
1888 1893 tcg_const_i32(8));
1889   - tcg_gen_discard_i64(r_dword);
1890 1894 }
1891 1895 #endif
1892 1896  
... ... @@ -1898,7 +1902,7 @@ static inline void gen_ldstub_asi(int insn)
1898 1902 gen_ld_asi(insn, 1, 0);
1899 1903  
1900 1904 asi = GET_FIELD(insn, 19, 26);
1901   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xff),
  1905 + tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xffULL),
1902 1906 tcg_const_i32(asi), tcg_const_i32(1));
1903 1907 }
1904 1908 #endif
... ... @@ -3090,7 +3094,7 @@ static void disas_sparc_insn(DisasContext * dc)
3090 3094 break;
3091 3095 #ifdef TARGET_SPARC64
3092 3096 case 0xd: /* V9 udivx */
3093   - gen_trap_ifdivzero_i64(cpu_T[1]);
  3097 + gen_trap_ifdivzero_tl(cpu_T[1]);
3094 3098 tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3095 3099 break;
3096 3100 #endif
... ... @@ -3134,18 +3138,18 @@ static void disas_sparc_insn(DisasContext * dc)
3134 3138 break;
3135 3139 #ifndef TARGET_SPARC64
3136 3140 case 0x25: /* sll */
3137   - tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3138   - tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
  3141 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
  3142 + tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3139 3143 gen_movl_T0_reg(rd);
3140 3144 break;
3141 3145 case 0x26: /* srl */
3142   - tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3143   - tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
  3146 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
  3147 + tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3144 3148 gen_movl_T0_reg(rd);
3145 3149 break;
3146 3150 case 0x27: /* sra */
3147   - tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3148   - tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
  3151 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
  3152 + tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3149 3153 gen_movl_T0_reg(rd);
3150 3154 break;
3151 3155 #endif
... ... @@ -3407,7 +3411,7 @@ static void disas_sparc_insn(DisasContext * dc)
3407 3411 goto illegal_insn;
3408 3412 }
3409 3413 #else
3410   - tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
  3414 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3411 3415 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3412 3416 #endif
3413 3417 }
... ... @@ -4115,17 +4119,15 @@ static void disas_sparc_insn(DisasContext * dc)
4115 4119 if (rd & 1)
4116 4120 goto illegal_insn;
4117 4121 else {
4118   - TCGv r_dword;
4119   -
4120   - r_dword = tcg_temp_new(TCG_TYPE_I64);
4121 4122 gen_op_check_align_T0_7();
4122 4123 ABI32_MASK(cpu_T[0]);
4123   - tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
4124   - tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
  4124 + tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
  4125 + tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
  4126 + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL);
4125 4127 gen_movl_T0_reg(rd + 1);
4126   - tcg_gen_shri_i64(r_dword, r_dword, 32);
4127   - tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
4128   - tcg_gen_discard_i64(r_dword);
  4128 + tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
  4129 + tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
  4130 + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL);
4129 4131 }
4130 4132 break;
4131 4133 case 0x9: /* load signed byte */
... ... @@ -4138,18 +4140,17 @@ static void disas_sparc_insn(DisasContext * dc)
4138 4140 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
4139 4141 break;
4140 4142 case 0xd: /* ldstub -- XXX: should be atomically */
4141   - tcg_gen_movi_i32(cpu_tmp0, 0xff);
4142 4143 ABI32_MASK(cpu_T[0]);
4143 4144 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4144   - tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
  4145 + tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_T[0], dc->mem_idx);
4145 4146 break;
4146 4147 case 0x0f: /* swap register with memory. Also atomically */
4147 4148 gen_op_check_align_T0_3();
4148 4149 gen_movl_reg_T1(rd);
4149 4150 ABI32_MASK(cpu_T[0]);
4150   - tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
  4151 + tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
4151 4152 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4152   - tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
  4153 + tcg_gen_extu_i32_tl(cpu_T[1], cpu_tmp32);
4153 4154 break;
4154 4155 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4155 4156 case 0x10: /* load word alternate */
... ... @@ -4342,16 +4343,14 @@ static void disas_sparc_insn(DisasContext * dc)
4342 4343 goto illegal_insn;
4343 4344 #ifndef __i386__
4344 4345 else {
4345   - TCGv r_dword, r_low;
  4346 + TCGv r_low;
4346 4347  
4347 4348 gen_op_check_align_T0_7();
4348   - r_dword = tcg_temp_new(TCG_TYPE_I64);
4349 4349 r_low = tcg_temp_new(TCG_TYPE_I32);
4350 4350 gen_movl_reg_TN(rd + 1, r_low);
4351   - tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
  4351 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
4352 4352 r_low);
4353   - tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
4354   - tcg_gen_discard_i64(r_dword);
  4353 + tcg_gen_qemu_st64(cpu_tmp64, cpu_T[0], dc->mem_idx);
4355 4354 }
4356 4355 #else /* __i386__ */
4357 4356 gen_op_check_align_T0_7();
... ... @@ -4584,6 +4583,8 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4584 4583 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4585 4584  
4586 4585 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
  4586 + cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
  4587 + cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4587 4588  
4588 4589 do {
4589 4590 if (env->nb_breakpoints > 0) {
... ...