Commit cbc37b28b3d0803a7ed73801c2969ed35e70e2e4
1 parent
af58f9ca
target-mips: optimize gen_movcf_*()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6957 c046a42c-6fe2-441c-8c8c-71466251a162
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23 additions
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51 deletions
target-mips/translate.c
... | ... | @@ -5722,98 +5722,70 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) |
5722 | 5722 | |
5723 | 5723 | static inline void gen_movcf_s (int fs, int fd, int cc, int tf) |
5724 | 5724 | { |
5725 | - uint32_t ccbit; | |
5726 | 5725 | int cond; |
5727 | - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); | |
5728 | - TCGv_i32 fp0 = tcg_temp_local_new_i32(); | |
5726 | + TCGv_i32 t0 = tcg_temp_new_i32(); | |
5729 | 5727 | int l1 = gen_new_label(); |
5730 | 5728 | |
5731 | - if (cc) | |
5732 | - ccbit = 1 << (24 + cc); | |
5733 | - else | |
5734 | - ccbit = 1 << 23; | |
5735 | - | |
5736 | 5729 | if (tf) |
5737 | 5730 | cond = TCG_COND_EQ; |
5738 | 5731 | else |
5739 | 5732 | cond = TCG_COND_NE; |
5740 | 5733 | |
5741 | - gen_load_fpr32(fp0, fd); | |
5742 | - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); | |
5743 | - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); | |
5744 | - tcg_temp_free_i32(r_tmp1); | |
5745 | - gen_load_fpr32(fp0, fs); | |
5734 | + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5735 | + tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
5736 | + gen_load_fpr32(t0, fs); | |
5737 | + gen_store_fpr32(t0, fd); | |
5746 | 5738 | gen_set_label(l1); |
5747 | - gen_store_fpr32(fp0, fd); | |
5748 | - tcg_temp_free_i32(fp0); | |
5739 | + tcg_temp_free_i32(t0); | |
5749 | 5740 | } |
5750 | 5741 | |
5751 | 5742 | static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) |
5752 | 5743 | { |
5753 | - uint32_t ccbit; | |
5754 | 5744 | int cond; |
5755 | - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); | |
5756 | - TCGv_i64 fp0 = tcg_temp_local_new_i64(); | |
5745 | + TCGv_i32 t0 = tcg_temp_new_i32(); | |
5746 | + TCGv_i64 fp0; | |
5757 | 5747 | int l1 = gen_new_label(); |
5758 | 5748 | |
5759 | - if (cc) | |
5760 | - ccbit = 1 << (24 + cc); | |
5761 | - else | |
5762 | - ccbit = 1 << 23; | |
5763 | - | |
5764 | 5749 | if (tf) |
5765 | 5750 | cond = TCG_COND_EQ; |
5766 | 5751 | else |
5767 | 5752 | cond = TCG_COND_NE; |
5768 | 5753 | |
5769 | - gen_load_fpr64(ctx, fp0, fd); | |
5770 | - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); | |
5771 | - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); | |
5772 | - tcg_temp_free_i32(r_tmp1); | |
5754 | + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5755 | + tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
5756 | + fp0 = tcg_temp_local_new_i64(); | |
5773 | 5757 | gen_load_fpr64(ctx, fp0, fs); |
5774 | - gen_set_label(l1); | |
5775 | 5758 | gen_store_fpr64(ctx, fp0, fd); |
5776 | 5759 | tcg_temp_free_i64(fp0); |
5760 | + gen_set_label(l1); | |
5761 | + tcg_temp_free_i32(t0); | |
5777 | 5762 | } |
5778 | 5763 | |
5779 | 5764 | static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) |
5780 | 5765 | { |
5781 | - uint32_t ccbit1, ccbit2; | |
5782 | 5766 | int cond; |
5783 | - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); | |
5784 | - TCGv_i32 fp0 = tcg_temp_local_new_i32(); | |
5767 | + TCGv_i32 t0 = tcg_temp_new_i32(); | |
5785 | 5768 | int l1 = gen_new_label(); |
5786 | 5769 | int l2 = gen_new_label(); |
5787 | 5770 | |
5788 | - if (cc) { | |
5789 | - ccbit1 = 1 << (24 + cc); | |
5790 | - ccbit2 = 1 << (25 + cc); | |
5791 | - } else { | |
5792 | - ccbit1 = 1 << 23; | |
5793 | - ccbit2 = 1 << 25; | |
5794 | - } | |
5795 | - | |
5796 | 5771 | if (tf) |
5797 | 5772 | cond = TCG_COND_EQ; |
5798 | 5773 | else |
5799 | 5774 | cond = TCG_COND_NE; |
5800 | 5775 | |
5801 | - gen_load_fpr32(fp0, fd); | |
5802 | - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit1); | |
5803 | - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); | |
5804 | - gen_load_fpr32(fp0, fs); | |
5776 | + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5777 | + tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
5778 | + gen_load_fpr32(t0, fs); | |
5779 | + gen_store_fpr32(t0, fd); | |
5805 | 5780 | gen_set_label(l1); |
5806 | - gen_store_fpr32(fp0, fd); | |
5807 | 5781 | |
5808 | - gen_load_fpr32h(fp0, fd); | |
5809 | - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit2); | |
5810 | - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l2); | |
5811 | - gen_load_fpr32h(fp0, fs); | |
5782 | + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1)); | |
5783 | + tcg_gen_brcondi_i32(cond, t0, 0, l2); | |
5784 | + gen_load_fpr32h(t0, fs); | |
5785 | + gen_store_fpr32h(t0, fd); | |
5812 | 5786 | gen_set_label(l2); |
5813 | - gen_store_fpr32h(fp0, fd); | |
5814 | 5787 | |
5815 | - tcg_temp_free_i32(r_tmp1); | |
5816 | - tcg_temp_free_i32(fp0); | |
5788 | + tcg_temp_free_i32(t0); | |
5817 | 5789 | } |
5818 | 5790 | |
5819 | 5791 | ... | ... |