gwj / at91sam9263 · Commits

Commit c45a3a030ed776f8590170e1f4cf1e320656d0a9

Authored by dmakow
1 parent 3c6f9b87

added push buttons

Inline Side-by-side
Showing 9 changed files with 472 additions and 179 deletions
monitor.c
  View file @c45a3a0
... ... @@ -92,6 +92,9 @@ struct Monitor {
92 92 LIST_ENTRY(Monitor) entry;
93 93 };
94 94  
  95 +static QEMUTimer *button_timer1;
  96 +static QEMUTimer *button_timer2;
  97 +
95 98 static LIST_HEAD(mon_list, Monitor) mon_list;
96 99  
97 100 static const mon_cmd_t mon_cmds[];
... ... @@ -543,11 +546,45 @@ static void do_set_gpio(Monitor* mon, const char* port, const char* value)
543 546 printf("Invalid channel\n");
544 547 }
545 548  
  549 +
  550 +static void button_handler1(void *mon)
  551 +{
  552 + qemu_del_timer(button_timer1);
  553 + do_set_gpio((Monitor*)mon, "C5", "1");
  554 +}
  555 +
  556 +static void button_handler2(void *mon)
  557 +{
  558 + qemu_del_timer(button_timer2);
  559 + do_set_gpio((Monitor*)mon, "C4", "1");
  560 +}
  561 +
  562 +
  563 +static void do_b1(Monitor* mon)
  564 +{
  565 + do_set_gpio(mon, "C5", "0");
  566 + qemu_mod_timer(button_timer1, qemu_get_clock(vm_clock) +
  567 + muldiv64(ticks_per_sec, 100, 1000));
  568 +}
  569 +
  570 +static void do_b2(Monitor* mon)
  571 +{
  572 + do_set_gpio(mon, "C4", "0");
  573 + qemu_mod_timer(button_timer2, qemu_get_clock(vm_clock) +
  574 + muldiv64(ticks_per_sec, 100, 1000));
  575 +}
  576 +
  577 +
  578 +
  579 +
  580 +
546 581 static void do_p1(Monitor* mon)
547 582 {
548 583 do_set_gpio(mon, "C5", "0");
549 584 }
550 585  
  586 +
  587 +
551 588 static void do_p2(Monitor* mon)
552 589 {
553 590 do_set_gpio(mon, "C4", "0");
... ... @@ -3240,13 +3277,15 @@ void monitor_init(CharDriverState *chr, int flags)
3240 3277 static int is_first_init = 1;
3241 3278 Monitor *mon;
3242 3279  
  3280 + mon = qemu_mallocz(sizeof(*mon));
  3281 +
3243 3282 if (is_first_init) {
3244 3283 key_timer = qemu_new_timer(vm_clock, release_keys, NULL);
  3284 + button_timer1 = qemu_new_timer(vm_clock, button_handler1, mon);
  3285 + button_timer2 = qemu_new_timer(vm_clock, button_handler2, mon);
3245 3286 is_first_init = 0;
3246 3287 }
3247 3288  
3248   - mon = qemu_mallocz(sizeof(*mon));
3249   -
3250 3289 mon->chr = chr;
3251 3290 mon->flags = flags;
3252 3291 if (mon->chr->focus != 0)
... ...
qemu-monitor.hx
  View file @c45a3a0
... ... @@ -683,6 +683,21 @@ STEXI
683 683 Release button 2
684 684 ETEXI
685 685  
  686 + { "b2", "", do_b2, "",
  687 + "button 2" },
  688 +STEXI
  689 +@item b2
  690 +Button 2
  691 +ETEXI
  692 +
  693 + { "b1", "", do_b1, "",
  694 + "button 1" },
  695 +STEXI
  696 +@item b1
  697 +Button 1
  698 +ETEXI
  699 +
  700 +
686 701  
687 702 STEXI
688 703 @end table
... ...
virtual_lab/Makefile 0 → 100644
  View file @c45a3a0
  1 +# SW VirtualLab DMCS@2020
  2 +
  3 +CCFLAGS=-g -mcpu=arm9 -Os -Wall
  4 +CC=arm-none-eabi-gcc
  5 +#LDFLAGS+=-nostartfiles -Wl,--cref -lc -lgcc -T /opt/arm_user/elf32-littlearm.lds -g -Ttext 0x20000000 -Tdata 0x300000 -n
  6 +LDFLAGS+=-nostartfiles -W -lc -lgcc -T script.lds -g -Ttext 0x20000000 -Tdata 0x300000 -n
  7 +OBJS=cstartup.o lowlevel.o
  8 +#koniec, dalej mozna dowolnie zmieniac
  9 +
  10 +PROGRAM_NAME=led_blink2.elf
  11 +
  12 +all: $(PROGRAM_NAME)
  13 +
  14 +rebuild: clean $(PROGRAM_NAME)
  15 +
  16 +$(PROGRAM_NAME): main.o
  17 + $(CC) $(LDFLAGS) $(OBJS) $< -o $@
  18 +
  19 +main.o: main.c
  20 + $(CC) -c $(CCFLAGS) $< -o $@
  21 +
  22 +clean:
  23 + rm -f *.o *.elf
... ...
virtual_lab/compileme.sh
  View file @c45a3a0
1 1 arm-none-eabi-gcc -E -I include -D__ASSEMBLY__ cstartup.S > cstartup_pre.S
2 2 arm-none-eabi-gcc -g -mcpu=arm926ej-s -c cstartup_pre.S -o cstartup.o
  3 +arm-none-eabi-gcc -g -mcpu=arm926ej-s -I include -c lowlevel.c -o lowlevel.o
3 4 arm-none-eabi-gcc -g -mcpu=arm926ej-s -I include lowlevel.c main.c cstartup.o -o main.elf -Ttext 0x20000000 -Tdata 0x300000 -T script.lds
4 5 # -Wl,--verbose
5 6  
... ...
virtual_lab/cstartup_pre.S 0 → 100644
  View file @c45a3a0
  1 +# 1 "cstartup.S"
  2 +# 1 "<built-in>"
  3 +# 1 "<command-line>"
  4 +# 1 "cstartup.S"
  5 +# 39 "cstartup.S"
  6 +# 1 "project.h" 1
  7 +# 44 "project.h"
  8 +# 1 "include/AT91SAM9263-EK.h" 1
  9 +# 45 "project.h" 2
  10 +# 1 "include/AT91SAM9263.h" 1
  11 +# 46 "project.h" 2
  12 +# 40 "cstartup.S" 2
  13 +# 55 "cstartup.S"
  14 + .globl reset_handler
  15 + .align 4
  16 +
  17 +.section .vectors
  18 +.arm
  19 +
  20 +
  21 +
  22 +_exception_vectors:
  23 +reset_vector:
  24 + ldr pc, =reset_handler
  25 +undef_vector:
  26 + b undef_vector
  27 +swi_vector:
  28 + b swi_vector
  29 +pabt_vector:
  30 + ldr pc, =pabt_handler
  31 +dabt_vector:
  32 + ldr pc, =dabt_handler
  33 +rsvd_vector:
  34 + b rsvd_vector
  35 +irq_vector:
  36 + b irq_handler
  37 +fiq_vector:
  38 +
  39 +
  40 +
  41 +
  42 +
  43 +fiq_handler:
  44 + b fiq_handler
  45 +
  46 +
  47 +
  48 +
  49 +
  50 +
  51 +irq_handler:
  52 +
  53 +
  54 + sub lr, lr, #4
  55 + stmfd sp!, {lr}
  56 +
  57 + mrs r14, SPSR
  58 + stmfd sp!, {r0,r14}
  59 +
  60 +
  61 +
  62 +
  63 + ldr r14, =( 0xFFFFF000)
  64 + ldr r0 , [r14, #( 0x00000100)]
  65 + str r14, [r14, #( 0x00000100)]
  66 +
  67 +
  68 + msr CPSR_c, #0x13
  69 +
  70 +
  71 + stmfd sp!, {r1-r3, r12, r14}
  72 +
  73 +
  74 + mov r14, pc
  75 + bx r0
  76 +
  77 +
  78 + ldmia sp!, {r1-r3, r12, r14}
  79 +
  80 +
  81 + msr CPSR_c, #0x12 | 0x80
  82 +
  83 +
  84 + ldr r14, =( 0xFFFFF000)
  85 + str r14, [r14, #( 0x00000130)]
  86 +
  87 +
  88 + ldmia sp!, {r0,r14}
  89 + msr SPSR_cxsf, r14
  90 +
  91 +
  92 + ldmia sp!, {pc}^
  93 +
  94 +
  95 +
  96 +
  97 +
  98 +
  99 +
  100 +.section .text
  101 +reset_handler:
  102 + ldr pc, =_low_level_init
  103 +
  104 +
  105 +
  106 +
  107 +
  108 +
  109 +_low_level_init:
  110 + ldr r2, =_lp_ll_init
  111 + ldmia r2, {r0, r1}
  112 + mov sp, r1
  113 + mov lr, pc
  114 + bx r0
  115 +
  116 +
  117 +
  118 +
  119 +_stack_init:
  120 + ldr r2, =_lp_stack_init
  121 + ldmia r2, {r0, r1, r2}
  122 +
  123 +
  124 + msr CPSR_c, #0x17 | 0x80 | 0x40
  125 + mov sp, r0
  126 + sub r0, r0, r1
  127 +
  128 +
  129 + msr CPSR_c, #0x12 | 0x80 | 0x40
  130 + mov sp, r0
  131 + sub r0, r0, r2
  132 +
  133 +
  134 + msr CPSR_c, #0x13 | 0x40
  135 + mov sp, r0
  136 +
  137 +
  138 +
  139 +
  140 +
  141 +_init_data:
  142 + ldr r2, =_lp_data
  143 + ldmia r2, {r1, r3, r4}
  144 +1:
  145 + cmp r3, r4
  146 + ldrcc r2, [r1], #4
  147 + strcc r2, [r3], #4
  148 + bcc 1b
  149 +
  150 +
  151 +_init_bss:
  152 + ldr r2, =_lp_bss
  153 + ldmia r2, {r3, r4}
  154 + mov r2, #0
  155 +1:
  156 + cmp r3, r4
  157 + strcc r2, [r3], #4
  158 + bcc 1b
  159 +
  160 +
  161 +
  162 +
  163 +_branch_main:
  164 + ldr r0, =main
  165 + mov lr, pc
  166 + bx r0
  167 +
  168 +
  169 +
  170 +
  171 +_lp_ll_init:
  172 + .word lowlevel_init
  173 + .word ((0x00300000) + (0x00014000))
  174 +
  175 +_lp_stack_init:
  176 + .word ((0x00300000) + (0x00014000))
  177 + .word 8*3*4
  178 + .word 8*3*4
  179 +
  180 +_lp_bss:
  181 + .word _sbss
  182 + .word _ebss
  183 +
  184 +_lp_data:
  185 + .word _etext
  186 + .word _sdata
  187 + .word _edata
... ...
virtual_lab/led_blink2.elf 0 → 100755
View file @c45a3a0
No preview for this file type
virtual_lab/lowlevel.c
  View file @c45a3a0
1   -/* ----------------------------------------------------------------------------
2   - * ATMEL Microcontroller Software Support - ROUSSET -
3   - * ----------------------------------------------------------------------------
4   - * Copyright (c) 2006, Atmel Corporation
5   - *
6   - * All rights reserved.
7   - *
8   - * Redistribution and use in source and binary forms, with or without
9   - * modification, are permitted provided that the following conditions are met:
10   - *
11   - * - Redistributions of source code must retain the above copyright notice,
12   - * this list of conditions and the disclaiimer below.
13   - *
14   - * - Redistributions in binary form must reproduce the above copyright notice,
15   - * this list of conditions and the disclaimer below in the documentation and/or
16   - * other materials provided with the distribution.
17   - *
18   - * Atmel's name may not be used to endorse or promote products derived from
19   - * this software without specific prior written permission.
20   - *
21   - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
22   - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23   - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
24   - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
25   - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26   - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27   - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
28   - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
29   - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30   - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31   - * ----------------------------------------------------------------------------
32   - */
33   -/*-----------------------------------------------------------------------------
34   - * File Name : lowlevel.c
35   - * Object : low level initialization file
36   - * Creation : FDy 20-Nov-2006
37   - *-----------------------------------------------------------------------------
38   - */
39   -
40   -/* Include Standard files */
41   -#include "project.h"
42   -
43   -
44   -/*-----------------------------------------------------------------------------
45   - * Function Name : default_spurious_handler
46   - * Object : default handler for spurious interrupt
47   - *-----------------------------------------------------------------------------*/
48   -void default_spurious_handler(void)
49   -{
50   - dbgu_print_ascii("-F- Spurious Interrupt\n\r ");
51   - while (1);
52   -}
53   -
54   -/*-----------------------------------------------------------------------------
55   - * Function Name : default_fiq_handler
56   - * Object : default handler for fast interrupt
57   - *-----------------------------------------------------------------------------*/
58   -void default_fiq_handler(void)
59   -{
60   - dbgu_print_ascii("-F- Unexpected FIQ Interrupt\n\r ");
61   - while (1);
62   -}
63   -
64   -/*-----------------------------------------------------------------------------
65   - * Function Name : default_irq_handler
66   - * Object : default handler for irq
67   - *-----------------------------------------------------------------------------*/
68   -void default_irq_handler(void)
69   -{
70   - dbgu_print_ascii("-F- Unexpected IRQ Interrupt\n\r ");
71   - while (1);
72   -}
73   -
74   -/*-----------------------------------------------------------------------------
75   - * Function Name : lowlevel_init
76   - * Object : This function performs very low level HW initialization
77   - * this function can use a Stack, depending the compilation
78   - * optimization mode
79   - *-----------------------------------------------------------------------------*/
80   -void lowlevel_init(void)
81   -{
82   - unsigned char i = 0;
83   -
84   - ///////////////////////////////////////////////////////////////////////////
85   - // Init PMC Step 1. Enable Main Oscillator
86   - // Main Oscillator startup time is board specific:
87   - // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
88   - // (0x40 for AT91C_CKGR_OSCOUNT field)
89   - ///////////////////////////////////////////////////////////////////////////
90   - AT91C_BASE_PMC->PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN));
91   - // Wait Main Oscillator stabilization
92   - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
93   -
94   - ///////////////////////////////////////////////////////////////////////////
95   - // Init PMC Step 2.
96   - // Set PLLA to 200MHz (198,656MHz)
97   - // PLL Startup time depends on PLL RC filter: worst case is choosen
98   - ///////////////////////////////////////////////////////////////////////////
99   - AT91C_BASE_PMC->PMC_PLLAR = AT91C_CKGR_SRCA |
100   - AT91C_CKGR_OUTA_2 |
101   - (0x3F << 8) |
102   - (AT91C_CKGR_MULA & (0x6D << 16)) |
103   - (AT91C_CKGR_DIVA & 9);
104   - // Wait for PLLA stabilization
105   - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
106   - // Wait until the master clock is established for the case we already
107   - // turn on the PLLA
108   - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
109   -
110   - ///////////////////////////////////////////////////////////////////////////
111   - // Init PMC Step 3.
112   - // Selection of Master Clock MCK equal to (Processor Clock PCK) PLLA/2=100MHz
113   - // The PMC_MCKR register must not be programmed in a single write operation
114   - // (see. Product Errata Sheet)
115   - ///////////////////////////////////////////////////////////////////////////
116   - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;
117   - // Wait until the master clock is established
118   - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
119   -
120   - AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
121   - // Wait until the master clock is established
122   - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
123   -
124   - ///////////////////////////////////////////////////////////////////////////
125   - // Reset AIC: assign default handler for each interrupt source
126   - ///////////////////////////////////////////////////////////////////////////
127   - AT91C_BASE_AIC->AIC_SVR[0] = (int) default_fiq_handler ;
128   - for (i = 1; i < 31; i++) {
129   - AT91C_BASE_AIC->AIC_SVR[i] = (int) default_irq_handler ;
130   - }
131   - AT91C_BASE_AIC->AIC_SPU = (unsigned int) default_spurious_handler;
132   -
133   - // Perform 8 IT acknoledge (write any value in EOICR)
134   - for (i = 0; i < 8 ; i++) {
135   - AT91C_BASE_AIC->AIC_EOICR = 0;
136   - }
137   -
138   - ///////////////////////////////////////////////////////////////////////////
139   - // Disable Watchdog
140   - ///////////////////////////////////////////////////////////////////////////
141   - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
142   -
143   - ///////////////////////////////////////////////////////////////////////////
144   - // Remap
145   - ///////////////////////////////////////////////////////////////////////////
146   - AT91C_BASE_MATRIX->MATRIX_MRCR = AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D;
147   -}
  1 +/* ----------------------------------------------------------------------------
  2 + * ATMEL Microcontroller Software Support - ROUSSET -
  3 + * ----------------------------------------------------------------------------
  4 + * Copyright (c) 2006, Atmel Corporation
  5 + *
  6 + * All rights reserved.
  7 + *
  8 + * Redistribution and use in source and binary forms, with or without
  9 + * modification, are permitted provided that the following conditions are met:
  10 + *
  11 + * - Redistributions of source code must retain the above copyright notice,
  12 + * this list of conditions and the disclaiimer below.
  13 + *
  14 + * - Redistributions in binary form must reproduce the above copyright notice,
  15 + * this list of conditions and the disclaimer below in the documentation and/or
  16 + * other materials provided with the distribution.
  17 + *
  18 + * Atmel's name may not be used to endorse or promote products derived from
  19 + * this software without specific prior written permission.
  20 + *
  21 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  24 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 + * ----------------------------------------------------------------------------
  32 + */
  33 +/*-----------------------------------------------------------------------------
  34 + * File Name : lowlevel.c
  35 + * Object : low level initialization file
  36 + * Creation : FDy 20-Nov-2006
  37 + *-----------------------------------------------------------------------------
  38 + */
148 39  
149   -void _exit(int c){while(1);};
  40 +/* Include Standard files */
  41 +#include "project.h"
150 42  
151   -void dabt_handler(){};
152   -void pabt_handler(){};
153   -void dbgu_print_ascii(const char* p){};
154 43 \ No newline at end of file
  44 +void dbgu_print_ascii (const char * buffer) {};
  45 +void dabt_handler (void) {};
  46 +void pabt_handler (void) {};
  47 +void _exit (int c) {while(1);};
  48 +
  49 +/*-----------------------------------------------------------------------------
  50 + * Function Name : default_spurious_handler
  51 + * Object : default handler for spurious interrupt
  52 + *-----------------------------------------------------------------------------*/
  53 +void default_spurious_handler(void)
  54 +{
  55 + dbgu_print_ascii("-F- Spurious Interrupt\n\r ");
  56 + while (1);
  57 +}
  58 +
  59 +/*-----------------------------------------------------------------------------
  60 + * Function Name : default_fiq_handler
  61 + * Object : default handler for fast interrupt
  62 + *-----------------------------------------------------------------------------*/
  63 +void default_fiq_handler(void)
  64 +{
  65 + dbgu_print_ascii("-F- Unexpected FIQ Interrupt\n\r ");
  66 + while (1);
  67 +}
  68 +
  69 +/*-----------------------------------------------------------------------------
  70 + * Function Name : default_irq_handler
  71 + * Object : default handler for irq
  72 + *-----------------------------------------------------------------------------*/
  73 +void default_irq_handler(void)
  74 +{
  75 + dbgu_print_ascii("-F- Unexpected IRQ Interrupt\n\r ");
  76 + while (1);
  77 +}
  78 +
  79 +/*-----------------------------------------------------------------------------
  80 + * Function Name : lowlevel_init
  81 + * Object : This function performs very low level HW initialization
  82 + * this function can use a Stack, depending the compilation
  83 + * optimization mode
  84 + *-----------------------------------------------------------------------------*/
  85 +void lowlevel_init(void)
  86 +{
  87 + unsigned char i = 0;
  88 +
  89 + ///////////////////////////////////////////////////////////////////////////
  90 + // Init PMC Step 1. Enable Main Oscillator
  91 + // Main Oscillator startup time is board specific:
  92 + // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
  93 + // (0x40 for AT91C_CKGR_OSCOUNT field)
  94 + ///////////////////////////////////////////////////////////////////////////
  95 + AT91C_BASE_PMC->PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN));
  96 + // Wait Main Oscillator stabilization
  97 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
  98 +
  99 + ///////////////////////////////////////////////////////////////////////////
  100 + // Init PMC Step 2.
  101 + // Set PLLA to 200MHz (198,656MHz)
  102 + // PLL Startup time depends on PLL RC filter: worst case is choosen
  103 + ///////////////////////////////////////////////////////////////////////////
  104 + AT91C_BASE_PMC->PMC_PLLAR = AT91C_CKGR_SRCA |
  105 + AT91C_CKGR_OUTA_2 |
  106 + (0x3F << 8) |
  107 + (AT91C_CKGR_MULA & (0x6D << 16)) |
  108 + (AT91C_CKGR_DIVA & 9);
  109 + // Wait for PLLA stabilization
  110 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
  111 + // Wait until the master clock is established for the case we already
  112 + // turn on the PLLA
  113 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
  114 +
  115 + ///////////////////////////////////////////////////////////////////////////
  116 + // Init PMC Step 3.
  117 + // Selection of Master Clock MCK equal to (Processor Clock PCK) PLLA/2=100MHz
  118 + // The PMC_MCKR register must not be programmed in a single write operation
  119 + // (see. Product Errata Sheet)
  120 + ///////////////////////////////////////////////////////////////////////////
  121 + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;
  122 + // Wait until the master clock is established
  123 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
  124 +
  125 + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
  126 + // Wait until the master clock is established
  127 + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
  128 +
  129 + ///////////////////////////////////////////////////////////////////////////
  130 + // Reset AIC: assign default handler for each interrupt source
  131 + ///////////////////////////////////////////////////////////////////////////
  132 + AT91C_BASE_AIC->AIC_SVR[0] = (int) default_fiq_handler ;
  133 + for (i = 1; i < 31; i++) {
  134 + AT91C_BASE_AIC->AIC_SVR[i] = (int) default_irq_handler ;
  135 + }
  136 + AT91C_BASE_AIC->AIC_SPU = (unsigned int) default_spurious_handler;
  137 +
  138 + // Perform 8 IT acknoledge (write any value in EOICR)
  139 + for (i = 0; i < 8 ; i++) {
  140 + AT91C_BASE_AIC->AIC_EOICR = 0;
  141 + }
  142 +
  143 + ///////////////////////////////////////////////////////////////////////////
  144 + // Disable Watchdog
  145 + ///////////////////////////////////////////////////////////////////////////
  146 + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
  147 +
  148 + ///////////////////////////////////////////////////////////////////////////
  149 + // Remap
  150 + ///////////////////////////////////////////////////////////////////////////
  151 + AT91C_BASE_MATRIX->MATRIX_MRCR = AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D;
  152 +}
... ...
virtual_lab/main.c
  View file @c45a3a0
1 1 #include <stdint.h>
2 2 #include <stdbool.h>
3 3  
4   -#define PA_PER (*((volatile uint32_t*)0xFFFFF200))
5   -#define PA_PDR (*((volatile uint32_t*)0xFFFFF204))
6   -#define PA_OER (*((volatile uint32_t*)0xFFFFF210))
7   -#define PA_SODR (*((volatile uint32_t*)0xFFFFF230))
8   -#define PA_CODR (*((volatile uint32_t*)0xFFFFF234))
9   -#define PA_PDSR (*((volatile uint32_t*)0xFFFFF23C))
10   -
11   -
12 4 #define PB_PER (*((volatile uint32_t*)0xFFFFF400))
13   -#define PB_PDR (*((volatile uint32_t*)0xFFFFF404))
14 5 #define PB_OER (*((volatile uint32_t*)0xFFFFF410))
15 6 #define PB_SODR (*((volatile uint32_t*)0xFFFFF430))
16 7 #define PB_CODR (*((volatile uint32_t*)0xFFFFF434))
... ... @@ -26,7 +17,7 @@
26 17  
27 18 #define PMC_PCER (*((volatile uint32_t*)0xFFFFFC10))
28 19  
29   -#define PER_ID_PBIOC_TO_PIOE 4
  20 +#define CLK_PIO_CDE 4
30 21  
31 22 #define DS1 (1 << 8) //PB8
32 23 #define DS2 (1 << 29) //PC29
... ... @@ -34,15 +25,38 @@
34 25 #define BT2 (1 << 4) //PC4
35 26 #define BT1 (1 << 5) //PC5
36 27  
37   -void delay(void)
  28 +void delay_ms (int delay)
  29 +{
  30 + volatile uint64_t DelayStep;
  31 + for(DelayStep = 0; DelayStep < 100000*delay; DelayStep++);
  32 +}
  33 +
  34 +void ConfigureLEDs (void)
  35 +{
  36 + PB_PER = DS1;
  37 + PC_PER = DS2;
  38 + PB_OER = DS1;
  39 + PC_OER = DS2;
  40 + PB_SODR = DS1;
  41 + PC_SODR = DS2;
  42 +}
  43 +
  44 +
  45 +void ConfigureButtons (void)
38 46 {
39   - volatile uint64_t i;
40   - for(i = 0; i < 100000000; i++);
  47 + PMC_PCER = 1 << CLK_PIO_CDE;
  48 + PC_PER = BT1 | BT2;
  49 + PC_ODR = BT1 | BT2;
  50 + PC_PUER = BT1 | BT2;
41 51 }
42 52  
43 53 int main(void)
44 54 {
45   - PMC_PCER = 1 << PER_ID_PBIOC_TO_PIOE;
  55 + int Decimator=0;
  56 + ConfigureLEDs();
  57 + ConfigureButtons();
  58 +#if 0
  59 + PMC_PCER = 1 << PER_ID_PBIOC_TO_PIOE;
46 60 PB_PER = DS1; //PIO enable register
47 61 // PB_PDR = 0xffffffff; //PIO disable register
48 62  
... ... @@ -51,16 +65,32 @@ int main(void)
51 65 PC_OER = DS2; //PIO controller output enable register
52 66 PC_ODR = BT1 | BT2;
53 67 PC_PUER = BT1 | BT2;
54   - while(true)
55   - {
56   -// delay();
57   - if(PC_PDSR & BT1)
58   - PB_SODR = DS1;
59   - else
60   - PB_CODR = DS1;
61   - if(PC_PDSR & BT2)
62   - PC_SODR = DS2;
63   - else
64   - PC_CODR = DS2;
65   - }
  68 +#endif
  69 +
  70 + while(true)
  71 + {
  72 + for (Decimator=0; Decimator<100; Decimator++)
  73 + {
  74 + if((PC_PDSR & BT1) == 0)
  75 + PB_SODR = DS1;
  76 +
  77 + if((PC_PDSR & BT2) == 0)
  78 + PB_CODR = DS1;
  79 + delay_ms(10);
  80 + }
  81 +
  82 + PC_CODR = DS2;
  83 +
  84 + for (Decimator=0; Decimator<100; Decimator++)
  85 + {
  86 + if((PC_PDSR & BT1) == 0)
  87 + PB_SODR = DS1;
  88 +
  89 + if((PC_PDSR & BT2) == 0)
  90 + PB_CODR = DS1;
  91 + delay_ms(10);
  92 + }
  93 +
  94 + PC_SODR = DS2;
  95 + }
66 96 }
... ...
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