gwj / at91sam9263 · Commits

Commit be24bb4f3007c3e07cbf1934f7e781493d876ab7

Authored by ths
1 parent ca88500f

Pass T0/T1 explicitly to helper functions, and clean up a few dyngen 

leftovers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 1130 additions and 1105 deletions
target-mips/exec.h
  View file @be24bb4
@@ -54,7 +54,6 @@ void dump_fpu(CPUState *env); @@ -54,7 +54,6 @@ void dump_fpu(CPUState *env);
54 void fpu_dump_state(CPUState *env, FILE *f, 54 void fpu_dump_state(CPUState *env, FILE *f,
55 int (*fpu_fprintf)(FILE *f, const char *fmt, ...), 55 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
56 int flags); 56 int flags);
57 -void dump_sc (void);  
58 57
59 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, 58 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
60 int mmu_idx, int is_softmmu); 59 int mmu_idx, int is_softmmu);
target-mips/helper.h
  View file @be24bb4
@@ -7,157 +7,157 @@ DEF_HELPER(void, do_raise_exception, (int excp)) @@ -7,157 +7,157 @@ DEF_HELPER(void, do_raise_exception, (int excp))
7 DEF_HELPER(void, do_interrupt_restart, (void)) 7 DEF_HELPER(void, do_interrupt_restart, (void))
8 8
9 #ifdef TARGET_MIPS64 9 #ifdef TARGET_MIPS64
10 -DEF_HELPER(void, do_ldl, (int mem_idx))  
11 -DEF_HELPER(void, do_ldr, (int mem_idx))  
12 -DEF_HELPER(void, do_sdl, (int mem_idx))  
13 -DEF_HELPER(void, do_sdr, (int mem_idx)) 10 +DEF_HELPER(target_ulong, do_ldl, (target_ulong t0, target_ulong t1, int mem_idx))
  11 +DEF_HELPER(target_ulong, do_ldr, (target_ulong t0, target_ulong t1, int mem_idx))
  12 +DEF_HELPER(void, do_sdl, (target_ulong t0, target_ulong t1, int mem_idx))
  13 +DEF_HELPER(void, do_sdr, (target_ulong t0, target_ulong t1, int mem_idx))
14 #endif 14 #endif
15 -DEF_HELPER(void, do_lwl, (int mem_idx))  
16 -DEF_HELPER(void, do_lwr, (int mem_idx))  
17 -DEF_HELPER(void, do_swl, (int mem_idx))  
18 -DEF_HELPER(void, do_swr, (int mem_idx)) 15 +DEF_HELPER(target_ulong, do_lwl, (target_ulong t0, target_ulong t1, int mem_idx))
  16 +DEF_HELPER(target_ulong, do_lwr, (target_ulong t0, target_ulong t1, int mem_idx))
  17 +DEF_HELPER(void, do_swl, (target_ulong t0, target_ulong t1, int mem_idx))
  18 +DEF_HELPER(void, do_swr, (target_ulong t0, target_ulong t1, int mem_idx))
19 19
20 -DEF_HELPER(void, do_clo, (void))  
21 -DEF_HELPER(void, do_clz, (void)) 20 +DEF_HELPER(target_ulong, do_clo, (target_ulong t0))
  21 +DEF_HELPER(target_ulong, do_clz, (target_ulong t0))
22 #ifdef TARGET_MIPS64 22 #ifdef TARGET_MIPS64
23 -DEF_HELPER(void, do_dclo, (void))  
24 -DEF_HELPER(void, do_dclz, (void))  
25 -DEF_HELPER(void, do_dmult, (void))  
26 -DEF_HELPER(void, do_dmultu, (void)) 23 +DEF_HELPER(target_ulong, do_dclo, (target_ulong t0))
  24 +DEF_HELPER(target_ulong, do_dclz, (target_ulong t0))
  25 +DEF_HELPER(void, do_dmult, (target_ulong t0, target_ulong t1))
  26 +DEF_HELPER(void, do_dmultu, (target_ulong t0, target_ulong t1))
27 #endif 27 #endif
28 28
29 -DEF_HELPER(void, do_muls, (void))  
30 -DEF_HELPER(void, do_mulsu, (void))  
31 -DEF_HELPER(void, do_macc, (void))  
32 -DEF_HELPER(void, do_maccu, (void))  
33 -DEF_HELPER(void, do_msac, (void))  
34 -DEF_HELPER(void, do_msacu, (void))  
35 -DEF_HELPER(void, do_mulhi, (void))  
36 -DEF_HELPER(void, do_mulhiu, (void))  
37 -DEF_HELPER(void, do_mulshi, (void))  
38 -DEF_HELPER(void, do_mulshiu, (void))  
39 -DEF_HELPER(void, do_macchi, (void))  
40 -DEF_HELPER(void, do_macchiu, (void))  
41 -DEF_HELPER(void, do_msachi, (void))  
42 -DEF_HELPER(void, do_msachiu, (void)) 29 +DEF_HELPER(target_ulong, do_muls, (target_ulong t0, target_ulong t1))
  30 +DEF_HELPER(target_ulong, do_mulsu, (target_ulong t0, target_ulong t1))
  31 +DEF_HELPER(target_ulong, do_macc, (target_ulong t0, target_ulong t1))
  32 +DEF_HELPER(target_ulong, do_maccu, (target_ulong t0, target_ulong t1))
  33 +DEF_HELPER(target_ulong, do_msac, (target_ulong t0, target_ulong t1))
  34 +DEF_HELPER(target_ulong, do_msacu, (target_ulong t0, target_ulong t1))
  35 +DEF_HELPER(target_ulong, do_mulhi, (target_ulong t0, target_ulong t1))
  36 +DEF_HELPER(target_ulong, do_mulhiu, (target_ulong t0, target_ulong t1))
  37 +DEF_HELPER(target_ulong, do_mulshi, (target_ulong t0, target_ulong t1))
  38 +DEF_HELPER(target_ulong, do_mulshiu, (target_ulong t0, target_ulong t1))
  39 +DEF_HELPER(target_ulong, do_macchi, (target_ulong t0, target_ulong t1))
  40 +DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1))
  41 +DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1))
  42 +DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
43 43
44 /* CP0 helpers */ 44 /* CP0 helpers */
45 #ifndef CONFIG_USER_ONLY 45 #ifndef CONFIG_USER_ONLY
46 -DEF_HELPER(void, do_mfc0_mvpcontrol, (void))  
47 -DEF_HELPER(void, do_mfc0_mvpconf0, (void))  
48 -DEF_HELPER(void, do_mfc0_mvpconf1, (void))  
49 -DEF_HELPER(void, do_mfc0_random, (void))  
50 -DEF_HELPER(void, do_mfc0_tcstatus, (void))  
51 -DEF_HELPER(void, do_mftc0_tcstatus, (void))  
52 -DEF_HELPER(void, do_mfc0_tcbind, (void))  
53 -DEF_HELPER(void, do_mftc0_tcbind, (void))  
54 -DEF_HELPER(void, do_mfc0_tcrestart, (void))  
55 -DEF_HELPER(void, do_mftc0_tcrestart, (void))  
56 -DEF_HELPER(void, do_mfc0_tchalt, (void))  
57 -DEF_HELPER(void, do_mftc0_tchalt, (void))  
58 -DEF_HELPER(void, do_mfc0_tccontext, (void))  
59 -DEF_HELPER(void, do_mftc0_tccontext, (void))  
60 -DEF_HELPER(void, do_mfc0_tcschedule, (void))  
61 -DEF_HELPER(void, do_mftc0_tcschedule, (void))  
62 -DEF_HELPER(void, do_mfc0_tcschefback, (void))  
63 -DEF_HELPER(void, do_mftc0_tcschefback, (void))  
64 -DEF_HELPER(void, do_mfc0_count, (void))  
65 -DEF_HELPER(void, do_mftc0_entryhi, (void))  
66 -DEF_HELPER(void, do_mftc0_status, (void))  
67 -DEF_HELPER(void, do_mfc0_lladdr, (void))  
68 -DEF_HELPER(void, do_mfc0_watchlo, (uint32_t sel))  
69 -DEF_HELPER(void, do_mfc0_watchhi, (uint32_t sel))  
70 -DEF_HELPER(void, do_mfc0_debug, (void))  
71 -DEF_HELPER(void, do_mftc0_debug, (void)) 46 +DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (target_ulong t0))
  47 +DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (target_ulong t0))
  48 +DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (target_ulong t0))
  49 +DEF_HELPER(target_ulong, do_mfc0_random, (target_ulong t0))
  50 +DEF_HELPER(target_ulong, do_mfc0_tcstatus, (target_ulong t0))
  51 +DEF_HELPER(target_ulong, do_mftc0_tcstatus, (target_ulong t0))
  52 +DEF_HELPER(target_ulong, do_mfc0_tcbind, (target_ulong t0))
  53 +DEF_HELPER(target_ulong, do_mftc0_tcbind, (target_ulong t0))
  54 +DEF_HELPER(target_ulong, do_mfc0_tcrestart, (target_ulong t0))
  55 +DEF_HELPER(target_ulong, do_mftc0_tcrestart, (target_ulong t0))
  56 +DEF_HELPER(target_ulong, do_mfc0_tchalt, (target_ulong t0))
  57 +DEF_HELPER(target_ulong, do_mftc0_tchalt, (target_ulong t0))
  58 +DEF_HELPER(target_ulong, do_mfc0_tccontext, (target_ulong t0))
  59 +DEF_HELPER(target_ulong, do_mftc0_tccontext, (target_ulong t0))
  60 +DEF_HELPER(target_ulong, do_mfc0_tcschedule, (target_ulong t0))
  61 +DEF_HELPER(target_ulong, do_mftc0_tcschedule, (target_ulong t0))
  62 +DEF_HELPER(target_ulong, do_mfc0_tcschefback, (target_ulong t0))
  63 +DEF_HELPER(target_ulong, do_mftc0_tcschefback, (target_ulong t0))
  64 +DEF_HELPER(target_ulong, do_mfc0_count, (target_ulong t0))
  65 +DEF_HELPER(target_ulong, do_mftc0_entryhi, (target_ulong t0))
  66 +DEF_HELPER(target_ulong, do_mftc0_status, (target_ulong t0))
  67 +DEF_HELPER(target_ulong, do_mfc0_lladdr, (target_ulong t0))
  68 +DEF_HELPER(target_ulong, do_mfc0_watchlo, (target_ulong t0, uint32_t sel))
  69 +DEF_HELPER(target_ulong, do_mfc0_watchhi, (target_ulong t0, uint32_t sel))
  70 +DEF_HELPER(target_ulong, do_mfc0_debug, (target_ulong t0))
  71 +DEF_HELPER(target_ulong, do_mftc0_debug, (target_ulong t0))
72 #ifdef TARGET_MIPS64 72 #ifdef TARGET_MIPS64
73 -DEF_HELPER(void, do_dmfc0_tcrestart, (void))  
74 -DEF_HELPER(void, do_dmfc0_tchalt, (void))  
75 -DEF_HELPER(void, do_dmfc0_tccontext, (void))  
76 -DEF_HELPER(void, do_dmfc0_tcschedule, (void))  
77 -DEF_HELPER(void, do_dmfc0_tcschefback, (void))  
78 -DEF_HELPER(void, do_dmfc0_lladdr, (void))  
79 -DEF_HELPER(void, do_dmfc0_watchlo, (uint32_t sel)) 73 +DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (target_ulong t0))
  74 +DEF_HELPER(target_ulong, do_dmfc0_tchalt, (target_ulong t0))
  75 +DEF_HELPER(target_ulong, do_dmfc0_tccontext, (target_ulong t0))
  76 +DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (target_ulong t0))
  77 +DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (target_ulong t0))
  78 +DEF_HELPER(target_ulong, do_dmfc0_lladdr, (target_ulong t0))
  79 +DEF_HELPER(target_ulong, do_dmfc0_watchlo, (target_ulong t0, uint32_t sel))
80 #endif /* TARGET_MIPS64 */ 80 #endif /* TARGET_MIPS64 */
81 81
82 -DEF_HELPER(void, do_mtc0_index, (void))  
83 -DEF_HELPER(void, do_mtc0_mvpcontrol, (void))  
84 -DEF_HELPER(void, do_mtc0_vpecontrol, (void))  
85 -DEF_HELPER(void, do_mtc0_vpeconf0, (void))  
86 -DEF_HELPER(void, do_mtc0_vpeconf1, (void))  
87 -DEF_HELPER(void, do_mtc0_yqmask, (void))  
88 -DEF_HELPER(void, do_mtc0_vpeopt, (void))  
89 -DEF_HELPER(void, do_mtc0_entrylo0, (void))  
90 -DEF_HELPER(void, do_mtc0_tcstatus, (void))  
91 -DEF_HELPER(void, do_mttc0_tcstatus, (void))  
92 -DEF_HELPER(void, do_mtc0_tcbind, (void))  
93 -DEF_HELPER(void, do_mttc0_tcbind, (void))  
94 -DEF_HELPER(void, do_mtc0_tcrestart, (void))  
95 -DEF_HELPER(void, do_mttc0_tcrestart, (void))  
96 -DEF_HELPER(void, do_mtc0_tchalt, (void))  
97 -DEF_HELPER(void, do_mttc0_tchalt, (void))  
98 -DEF_HELPER(void, do_mtc0_tccontext, (void))  
99 -DEF_HELPER(void, do_mttc0_tccontext, (void))  
100 -DEF_HELPER(void, do_mtc0_tcschedule, (void))  
101 -DEF_HELPER(void, do_mttc0_tcschedule, (void))  
102 -DEF_HELPER(void, do_mtc0_tcschefback, (void))  
103 -DEF_HELPER(void, do_mttc0_tcschefback, (void))  
104 -DEF_HELPER(void, do_mtc0_entrylo1, (void))  
105 -DEF_HELPER(void, do_mtc0_context, (void))  
106 -DEF_HELPER(void, do_mtc0_pagemask, (void))  
107 -DEF_HELPER(void, do_mtc0_pagegrain, (void))  
108 -DEF_HELPER(void, do_mtc0_wired, (void))  
109 -DEF_HELPER(void, do_mtc0_srsconf0, (void))  
110 -DEF_HELPER(void, do_mtc0_srsconf1, (void))  
111 -DEF_HELPER(void, do_mtc0_srsconf2, (void))  
112 -DEF_HELPER(void, do_mtc0_srsconf3, (void))  
113 -DEF_HELPER(void, do_mtc0_srsconf4, (void))  
114 -DEF_HELPER(void, do_mtc0_hwrena, (void))  
115 -DEF_HELPER(void, do_mtc0_count, (void))  
116 -DEF_HELPER(void, do_mtc0_entryhi, (void))  
117 -DEF_HELPER(void, do_mttc0_entryhi, (void))  
118 -DEF_HELPER(void, do_mtc0_compare, (void))  
119 -DEF_HELPER(void, do_mtc0_status, (void))  
120 -DEF_HELPER(void, do_mttc0_status, (void))  
121 -DEF_HELPER(void, do_mtc0_intctl, (void))  
122 -DEF_HELPER(void, do_mtc0_srsctl, (void))  
123 -DEF_HELPER(void, do_mtc0_cause, (void))  
124 -DEF_HELPER(void, do_mtc0_ebase, (void))  
125 -DEF_HELPER(void, do_mtc0_config0, (void))  
126 -DEF_HELPER(void, do_mtc0_config2, (void))  
127 -DEF_HELPER(void, do_mtc0_watchlo, (uint32_t sel))  
128 -DEF_HELPER(void, do_mtc0_watchhi, (uint32_t sel))  
129 -DEF_HELPER(void, do_mtc0_xcontext, (void))  
130 -DEF_HELPER(void, do_mtc0_framemask, (void))  
131 -DEF_HELPER(void, do_mtc0_debug, (void))  
132 -DEF_HELPER(void, do_mttc0_debug, (void))  
133 -DEF_HELPER(void, do_mtc0_performance0, (void))  
134 -DEF_HELPER(void, do_mtc0_taglo, (void))  
135 -DEF_HELPER(void, do_mtc0_datalo, (void))  
136 -DEF_HELPER(void, do_mtc0_taghi, (void))  
137 -DEF_HELPER(void, do_mtc0_datahi, (void)) 82 +DEF_HELPER(void, do_mtc0_index, (target_ulong t0))
  83 +DEF_HELPER(void, do_mtc0_mvpcontrol, (target_ulong t0))
  84 +DEF_HELPER(void, do_mtc0_vpecontrol, (target_ulong t0))
  85 +DEF_HELPER(void, do_mtc0_vpeconf0, (target_ulong t0))
  86 +DEF_HELPER(void, do_mtc0_vpeconf1, (target_ulong t0))
  87 +DEF_HELPER(void, do_mtc0_yqmask, (target_ulong t0))
  88 +DEF_HELPER(void, do_mtc0_vpeopt, (target_ulong t0))
  89 +DEF_HELPER(void, do_mtc0_entrylo0, (target_ulong t0))
  90 +DEF_HELPER(void, do_mtc0_tcstatus, (target_ulong t0))
  91 +DEF_HELPER(void, do_mttc0_tcstatus, (target_ulong t0))
  92 +DEF_HELPER(void, do_mtc0_tcbind, (target_ulong t0))
  93 +DEF_HELPER(void, do_mttc0_tcbind, (target_ulong t0))
  94 +DEF_HELPER(void, do_mtc0_tcrestart, (target_ulong t0))
  95 +DEF_HELPER(void, do_mttc0_tcrestart, (target_ulong t0))
  96 +DEF_HELPER(void, do_mtc0_tchalt, (target_ulong t0))
  97 +DEF_HELPER(void, do_mttc0_tchalt, (target_ulong t0))
  98 +DEF_HELPER(void, do_mtc0_tccontext, (target_ulong t0))
  99 +DEF_HELPER(void, do_mttc0_tccontext, (target_ulong t0))
  100 +DEF_HELPER(void, do_mtc0_tcschedule, (target_ulong t0))
  101 +DEF_HELPER(void, do_mttc0_tcschedule, (target_ulong t0))
  102 +DEF_HELPER(void, do_mtc0_tcschefback, (target_ulong t0))
  103 +DEF_HELPER(void, do_mttc0_tcschefback, (target_ulong t0))
  104 +DEF_HELPER(void, do_mtc0_entrylo1, (target_ulong t0))
  105 +DEF_HELPER(void, do_mtc0_context, (target_ulong t0))
  106 +DEF_HELPER(void, do_mtc0_pagemask, (target_ulong t0))
  107 +DEF_HELPER(void, do_mtc0_pagegrain, (target_ulong t0))
  108 +DEF_HELPER(void, do_mtc0_wired, (target_ulong t0))
  109 +DEF_HELPER(void, do_mtc0_srsconf0, (target_ulong t0))
  110 +DEF_HELPER(void, do_mtc0_srsconf1, (target_ulong t0))
  111 +DEF_HELPER(void, do_mtc0_srsconf2, (target_ulong t0))
  112 +DEF_HELPER(void, do_mtc0_srsconf3, (target_ulong t0))
  113 +DEF_HELPER(void, do_mtc0_srsconf4, (target_ulong t0))
  114 +DEF_HELPER(void, do_mtc0_hwrena, (target_ulong t0))
  115 +DEF_HELPER(void, do_mtc0_count, (target_ulong t0))
  116 +DEF_HELPER(void, do_mtc0_entryhi, (target_ulong t0))
  117 +DEF_HELPER(void, do_mttc0_entryhi, (target_ulong t0))
  118 +DEF_HELPER(void, do_mtc0_compare, (target_ulong t0))
  119 +DEF_HELPER(void, do_mtc0_status, (target_ulong t0))
  120 +DEF_HELPER(void, do_mttc0_status, (target_ulong t0))
  121 +DEF_HELPER(void, do_mtc0_intctl, (target_ulong t0))
  122 +DEF_HELPER(void, do_mtc0_srsctl, (target_ulong t0))
  123 +DEF_HELPER(void, do_mtc0_cause, (target_ulong t0))
  124 +DEF_HELPER(void, do_mtc0_ebase, (target_ulong t0))
  125 +DEF_HELPER(void, do_mtc0_config0, (target_ulong t0))
  126 +DEF_HELPER(void, do_mtc0_config2, (target_ulong t0))
  127 +DEF_HELPER(void, do_mtc0_watchlo, (target_ulong t0, uint32_t sel))
  128 +DEF_HELPER(void, do_mtc0_watchhi, (target_ulong t0, uint32_t sel))
  129 +DEF_HELPER(void, do_mtc0_xcontext, (target_ulong t0))
  130 +DEF_HELPER(void, do_mtc0_framemask, (target_ulong t0))
  131 +DEF_HELPER(void, do_mtc0_debug, (target_ulong t0))
  132 +DEF_HELPER(void, do_mttc0_debug, (target_ulong t0))
  133 +DEF_HELPER(void, do_mtc0_performance0, (target_ulong t0))
  134 +DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0))
  135 +DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0))
  136 +DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0))
  137 +DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0))
138 #endif /* !CONFIG_USER_ONLY */ 138 #endif /* !CONFIG_USER_ONLY */
139 139
140 /* MIPS MT functions */ 140 /* MIPS MT functions */
141 -DEF_HELPER(void, do_mftgpr, (uint32_t sel))  
142 -DEF_HELPER(void, do_mftlo, (uint32_t sel))  
143 -DEF_HELPER(void, do_mfthi, (uint32_t sel))  
144 -DEF_HELPER(void, do_mftacx, (uint32_t sel))  
145 -DEF_HELPER(void, do_mftdsp, (void))  
146 -DEF_HELPER(void, do_mttgpr, (uint32_t sel))  
147 -DEF_HELPER(void, do_mttlo, (uint32_t sel))  
148 -DEF_HELPER(void, do_mtthi, (uint32_t sel))  
149 -DEF_HELPER(void, do_mttacx, (uint32_t sel))  
150 -DEF_HELPER(void, do_mttdsp, (void))  
151 -DEF_HELPER(void, do_dmt, (void))  
152 -DEF_HELPER(void, do_emt, (void))  
153 -DEF_HELPER(void, do_dvpe, (void))  
154 -DEF_HELPER(void, do_evpe, (void))  
155 -DEF_HELPER(void, do_fork, (void))  
156 -DEF_HELPER(void, do_yield, (void)) 141 +DEF_HELPER(target_ulong, do_mftgpr, (target_ulong t0, uint32_t sel))
  142 +DEF_HELPER(target_ulong, do_mftlo, (target_ulong t0, uint32_t sel))
  143 +DEF_HELPER(target_ulong, do_mfthi, (target_ulong t0, uint32_t sel))
  144 +DEF_HELPER(target_ulong, do_mftacx, (target_ulong t0, uint32_t sel))
  145 +DEF_HELPER(target_ulong, do_mftdsp, (target_ulong t0))
  146 +DEF_HELPER(void, do_mttgpr, (target_ulong t0, uint32_t sel))
  147 +DEF_HELPER(void, do_mttlo, (target_ulong t0, uint32_t sel))
  148 +DEF_HELPER(void, do_mtthi, (target_ulong t0, uint32_t sel))
  149 +DEF_HELPER(void, do_mttacx, (target_ulong t0, uint32_t sel))
  150 +DEF_HELPER(void, do_mttdsp, (target_ulong t0))
  151 +DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
  152 +DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
  153 +DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
  154 +DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
  155 +DEF_HELPER(target_ulong, do_fork, (target_ulong t0, target_ulong t1))
  156 +DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
157 157
158 /* CP1 functions */ 158 /* CP1 functions */
159 -DEF_HELPER(void, do_cfc1, (uint32_t reg))  
160 -DEF_HELPER(void, do_ctc1, (uint32_t reg)) 159 +DEF_HELPER(target_ulong, do_cfc1, (target_ulong t0, uint32_t reg))
  160 +DEF_HELPER(void, do_ctc1, (target_ulong t0, uint32_t reg))
161 161
162 DEF_HELPER(void, do_float_cvtd_s, (void)) 162 DEF_HELPER(void, do_float_cvtd_s, (void))
163 DEF_HELPER(void, do_float_cvtd_w, (void)) 163 DEF_HELPER(void, do_float_cvtd_w, (void))
@@ -239,24 +239,24 @@ FOP_PROTO(ngt) @@ -239,24 +239,24 @@ FOP_PROTO(ngt)
239 #undef FOP_PROTO 239 #undef FOP_PROTO
240 240
241 /* Special functions */ 241 /* Special functions */
242 -DEF_HELPER(void, do_di, (void))  
243 -DEF_HELPER(void, do_ei, (void))  
244 -DEF_HELPER(void, do_eret, (void))  
245 -DEF_HELPER(void, do_deret, (void))  
246 -DEF_HELPER(void, do_rdhwr_cpunum, (void))  
247 -DEF_HELPER(void, do_rdhwr_synci_step, (void))  
248 -DEF_HELPER(void, do_rdhwr_cc, (void))  
249 -DEF_HELPER(void, do_rdhwr_ccres, (void)) 242 +DEF_HELPER(target_ulong, do_di, (target_ulong t0))
  243 +DEF_HELPER(target_ulong, do_ei, (target_ulong t0))
  244 +DEF_HELPER(void, do_eret, (target_ulong t0))
  245 +DEF_HELPER(void, do_deret, (target_ulong t0))
  246 +DEF_HELPER(target_ulong, do_rdhwr_cpunum, (target_ulong t0))
  247 +DEF_HELPER(target_ulong, do_rdhwr_synci_step, (target_ulong t0))
  248 +DEF_HELPER(target_ulong, do_rdhwr_cc, (target_ulong t0))
  249 +DEF_HELPER(target_ulong, do_rdhwr_ccres, (target_ulong t0))
250 DEF_HELPER(void, do_pmon, (int function)) 250 DEF_HELPER(void, do_pmon, (int function))
251 DEF_HELPER(void, do_wait, (void)) 251 DEF_HELPER(void, do_wait, (void))
252 252
253 /* Bitfield operations. */ 253 /* Bitfield operations. */
254 -DEF_HELPER(void, do_ext, (uint32_t pos, uint32_t size))  
255 -DEF_HELPER(void, do_ins, (uint32_t pos, uint32_t size))  
256 -DEF_HELPER(void, do_wsbh, (void)) 254 +DEF_HELPER(target_ulong, do_ext, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
  255 +DEF_HELPER(target_ulong, do_ins, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
  256 +DEF_HELPER(target_ulong, do_wsbh, (target_ulong t0, target_ulong t1))
257 #ifdef TARGET_MIPS64 257 #ifdef TARGET_MIPS64
258 -DEF_HELPER(void, do_dext, (uint32_t pos, uint32_t size))  
259 -DEF_HELPER(void, do_dins, (uint32_t pos, uint32_t size))  
260 -DEF_HELPER(void, do_dsbh, (void))  
261 -DEF_HELPER(void, do_dshd, (void)) 258 +DEF_HELPER(target_ulong, do_dext, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
  259 +DEF_HELPER(target_ulong, do_dins, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
  260 +DEF_HELPER(target_ulong, do_dsbh, (target_ulong t0, target_ulong t1))
  261 +DEF_HELPER(target_ulong, do_dshd, (target_ulong t0, target_ulong t1))
262 #endif 262 #endif
target-mips/op_helper.c
  View file @be24bb4
@@ -33,7 +33,6 @@ void do_raise_exception_err (uint32_t exception, int error_code) @@ -33,7 +33,6 @@ void do_raise_exception_err (uint32_t exception, int error_code)
33 #endif 33 #endif
34 env->exception_index = exception; 34 env->exception_index = exception;
35 env->error_code = error_code; 35 env->error_code = error_code;
36 - T0 = 0;  
37 cpu_loop_exit(); 36 cpu_loop_exit();
38 } 37 }
39 38
@@ -65,106 +64,26 @@ void do_restore_state (void *pc_ptr) @@ -65,106 +64,26 @@ void do_restore_state (void *pc_ptr)
65 } 64 }
66 } 65 }
67 66
68 -void do_clo (void) 67 +target_ulong do_clo (target_ulong t0)
69 { 68 {
70 - T0 = clo32(T0); 69 + return clo32(t0);
71 } 70 }
72 71
73 -void do_clz (void) 72 +target_ulong do_clz (target_ulong t0)
74 { 73 {
75 - T0 = clz32(T0); 74 + return clz32(t0);
76 } 75 }
77 76
78 #if defined(TARGET_MIPS64) 77 #if defined(TARGET_MIPS64)
79 -#if TARGET_LONG_BITS > HOST_LONG_BITS  
80 -/* Those might call libgcc functions. */  
81 -void do_dsll (void)  
82 -{  
83 - T0 = T0 << T1;  
84 -}  
85 -  
86 -void do_dsll32 (void)  
87 -{  
88 - T0 = T0 << (T1 + 32);  
89 -}  
90 -  
91 -void do_dsra (void)  
92 -{  
93 - T0 = (int64_t)T0 >> T1;  
94 -}  
95 -  
96 -void do_dsra32 (void)  
97 -{  
98 - T0 = (int64_t)T0 >> (T1 + 32);  
99 -}  
100 -  
101 -void do_dsrl (void)  
102 -{  
103 - T0 = T0 >> T1;  
104 -}  
105 -  
106 -void do_dsrl32 (void)  
107 -{  
108 - T0 = T0 >> (T1 + 32);  
109 -}  
110 -  
111 -void do_drotr (void)  
112 -{  
113 - target_ulong tmp;  
114 -  
115 - if (T1) {  
116 - tmp = T0 << (0x40 - T1);  
117 - T0 = (T0 >> T1) | tmp;  
118 - }  
119 -}  
120 -  
121 -void do_drotr32 (void)  
122 -{  
123 - target_ulong tmp;  
124 -  
125 - tmp = T0 << (0x40 - (32 + T1));  
126 - T0 = (T0 >> (32 + T1)) | tmp;  
127 -}  
128 -  
129 -void do_dsllv (void)  
130 -{  
131 - T0 = T1 << (T0 & 0x3F);  
132 -}  
133 -  
134 -void do_dsrav (void)  
135 -{  
136 - T0 = (int64_t)T1 >> (T0 & 0x3F);  
137 -}  
138 -  
139 -void do_dsrlv (void)  
140 -{  
141 - T0 = T1 >> (T0 & 0x3F);  
142 -}  
143 -  
144 -void do_drotrv (void)  
145 -{  
146 - target_ulong tmp;  
147 -  
148 - T0 &= 0x3F;  
149 - if (T0) {  
150 - tmp = T1 << (0x40 - T0);  
151 - T0 = (T1 >> T0) | tmp;  
152 - } else  
153 - T0 = T1;  
154 -}  
155 -  
156 -#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */  
157 -  
158 -void do_dclo (void) 78 +target_ulong do_dclo (target_ulong t0)
159 { 79 {
160 - T0 = clo64(T0); 80 + return clo64(t0);
161 } 81 }
162 82
163 -void do_dclz (void) 83 +target_ulong do_dclz (target_ulong t0)
164 { 84 {
165 - T0 = clz64(T0); 85 + return clz64(t0);
166 } 86 }
167 -  
168 #endif /* TARGET_MIPS64 */ 87 #endif /* TARGET_MIPS64 */
169 88
170 /* 64 bits arithmetic for 32 bits hosts */ 89 /* 64 bits arithmetic for 32 bits hosts */
@@ -179,132 +98,160 @@ static always_inline void set_HILO (uint64_t HILO) @@ -179,132 +98,160 @@ static always_inline void set_HILO (uint64_t HILO)
179 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); 98 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
180 } 99 }
181 100
182 -static always_inline void set_HIT0_LO (uint64_t HILO) 101 +static always_inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
183 { 102 {
184 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); 103 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
185 - T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); 104 + t0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
186 } 105 }
187 106
188 -static always_inline void set_HI_LOT0 (uint64_t HILO) 107 +static always_inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
189 { 108 {
190 - T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); 109 + t0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
191 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); 110 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
192 } 111 }
193 112
194 #if TARGET_LONG_BITS > HOST_LONG_BITS 113 #if TARGET_LONG_BITS > HOST_LONG_BITS
195 -void do_madd (void) 114 +void do_madd (target_ulong t0, target_ulong t1)
196 { 115 {
197 int64_t tmp; 116 int64_t tmp;
198 117
199 - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); 118 + tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
200 set_HILO((int64_t)get_HILO() + tmp); 119 set_HILO((int64_t)get_HILO() + tmp);
201 } 120 }
202 121
203 -void do_maddu (void) 122 +void do_maddu (target_ulong t0, target_ulong t1)
204 { 123 {
205 uint64_t tmp; 124 uint64_t tmp;
206 125
207 - tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); 126 + tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
208 set_HILO(get_HILO() + tmp); 127 set_HILO(get_HILO() + tmp);
209 } 128 }
210 129
211 -void do_msub (void) 130 +void do_msub (target_ulong t0, target_ulong t1)
212 { 131 {
213 int64_t tmp; 132 int64_t tmp;
214 133
215 - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); 134 + tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
216 set_HILO((int64_t)get_HILO() - tmp); 135 set_HILO((int64_t)get_HILO() - tmp);
217 } 136 }
218 137
219 -void do_msubu (void) 138 +void do_msubu (target_ulong t0, target_ulong t1)
220 { 139 {
221 uint64_t tmp; 140 uint64_t tmp;
222 141
223 - tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); 142 + tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
224 set_HILO(get_HILO() - tmp); 143 set_HILO(get_HILO() - tmp);
225 } 144 }
226 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ 145 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
227 146
228 /* Multiplication variants of the vr54xx. */ 147 /* Multiplication variants of the vr54xx. */
229 -void do_muls (void) 148 +target_ulong do_muls (target_ulong t0, target_ulong t1)
230 { 149 {
231 - set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); 150 + set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  151 +
  152 + return t0;
232 } 153 }
233 154
234 -void do_mulsu (void) 155 +target_ulong do_mulsu (target_ulong t0, target_ulong t1)
235 { 156 {
236 - set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); 157 + set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  158 +
  159 + return t0;
237 } 160 }
238 161
239 -void do_macc (void) 162 +target_ulong do_macc (target_ulong t0, target_ulong t1)
240 { 163 {
241 - set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); 164 + set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  165 +
  166 + return t0;
242 } 167 }
243 168
244 -void do_macchi (void) 169 +target_ulong do_macchi (target_ulong t0, target_ulong t1)
245 { 170 {
246 - set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); 171 + set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  172 +
  173 + return t0;
247 } 174 }
248 175
249 -void do_maccu (void) 176 +target_ulong do_maccu (target_ulong t0, target_ulong t1)
250 { 177 {
251 - set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); 178 + set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  179 +
  180 + return t0;
252 } 181 }
253 182
254 -void do_macchiu (void) 183 +target_ulong do_macchiu (target_ulong t0, target_ulong t1)
255 { 184 {
256 - set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); 185 + set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  186 +
  187 + return t0;
257 } 188 }
258 189
259 -void do_msac (void) 190 +target_ulong do_msac (target_ulong t0, target_ulong t1)
260 { 191 {
261 - set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); 192 + set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  193 +
  194 + return t0;
262 } 195 }
263 196
264 -void do_msachi (void) 197 +target_ulong do_msachi (target_ulong t0, target_ulong t1)
265 { 198 {
266 - set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); 199 + set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  200 +
  201 + return t0;
267 } 202 }
268 203
269 -void do_msacu (void) 204 +target_ulong do_msacu (target_ulong t0, target_ulong t1)
270 { 205 {
271 - set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); 206 + set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  207 +
  208 + return t0;
272 } 209 }
273 210
274 -void do_msachiu (void) 211 +target_ulong do_msachiu (target_ulong t0, target_ulong t1)
275 { 212 {
276 - set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); 213 + set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  214 +
  215 + return t0;
277 } 216 }
278 217
279 -void do_mulhi (void) 218 +target_ulong do_mulhi (target_ulong t0, target_ulong t1)
280 { 219 {
281 - set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); 220 + set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
  221 +
  222 + return t0;
282 } 223 }
283 224
284 -void do_mulhiu (void) 225 +target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
285 { 226 {
286 - set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); 227 + set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
  228 +
  229 + return t0;
287 } 230 }
288 231
289 -void do_mulshi (void) 232 +target_ulong do_mulshi (target_ulong t0, target_ulong t1)
290 { 233 {
291 - set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); 234 + set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
  235 +
  236 + return t0;
292 } 237 }
293 238
294 -void do_mulshiu (void) 239 +target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
295 { 240 {
296 - set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); 241 + set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
  242 +
  243 + return t0;
297 } 244 }
298 245
299 #ifdef TARGET_MIPS64 246 #ifdef TARGET_MIPS64
300 -void do_dmult (void) 247 +void do_dmult (target_ulong t0, target_ulong t1)
301 { 248 {
302 - muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1); 249 + muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
303 } 250 }
304 251
305 -void do_dmultu (void) 252 +void do_dmultu (target_ulong t0, target_ulong t1)
306 { 253 {
307 - mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1); 254 + mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
308 } 255 }
309 #endif 256 #endif
310 257
@@ -316,7 +263,7 @@ void do_dmultu (void) @@ -316,7 +263,7 @@ void do_dmultu (void)
316 #define GET_OFFSET(addr, offset) (addr - (offset)) 263 #define GET_OFFSET(addr, offset) (addr - (offset))
317 #endif 264 #endif
318 265
319 -void do_lwl(int mem_idx) 266 +target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
320 { 267 {
321 target_ulong tmp; 268 target_ulong tmp;
322 269
@@ -333,27 +280,27 @@ void do_lwl(int mem_idx) @@ -333,27 +280,27 @@ void do_lwl(int mem_idx)
333 case 2: ldfun = ldub_user; break; 280 case 2: ldfun = ldub_user; break;
334 } 281 }
335 #endif 282 #endif
336 - tmp = ldfun(T0);  
337 - T1 = (T1 & 0x00FFFFFF) | (tmp << 24); 283 + tmp = ldfun(t0);
  284 + t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
338 285
339 - if (GET_LMASK(T0) <= 2) {  
340 - tmp = ldfun(GET_OFFSET(T0, 1));  
341 - T1 = (T1 & 0xFF00FFFF) | (tmp << 16); 286 + if (GET_LMASK(t0) <= 2) {
  287 + tmp = ldfun(GET_OFFSET(t0, 1));
  288 + t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
342 } 289 }
343 290
344 - if (GET_LMASK(T0) <= 1) {  
345 - tmp = ldfun(GET_OFFSET(T0, 2));  
346 - T1 = (T1 & 0xFFFF00FF) | (tmp << 8); 291 + if (GET_LMASK(t0) <= 1) {
  292 + tmp = ldfun(GET_OFFSET(t0, 2));
  293 + t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
347 } 294 }
348 295
349 - if (GET_LMASK(T0) == 0) {  
350 - tmp = ldfun(GET_OFFSET(T0, 3));  
351 - T1 = (T1 & 0xFFFFFF00) | tmp; 296 + if (GET_LMASK(t0) == 0) {
  297 + tmp = ldfun(GET_OFFSET(t0, 3));
  298 + t1 = (t1 & 0xFFFFFF00) | tmp;
352 } 299 }
353 - T1 = (int32_t)T1; 300 + return (int32_t)t1;
354 } 301 }
355 302
356 -void do_lwr(int mem_idx) 303 +target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
357 { 304 {
358 target_ulong tmp; 305 target_ulong tmp;
359 306
@@ -370,27 +317,27 @@ void do_lwr(int mem_idx) @@ -370,27 +317,27 @@ void do_lwr(int mem_idx)
370 case 2: ldfun = ldub_user; break; 317 case 2: ldfun = ldub_user; break;
371 } 318 }
372 #endif 319 #endif
373 - tmp = ldfun(T0);  
374 - T1 = (T1 & 0xFFFFFF00) | tmp; 320 + tmp = ldfun(t0);
  321 + t1 = (t1 & 0xFFFFFF00) | tmp;
375 322
376 - if (GET_LMASK(T0) >= 1) {  
377 - tmp = ldfun(GET_OFFSET(T0, -1));  
378 - T1 = (T1 & 0xFFFF00FF) | (tmp << 8); 323 + if (GET_LMASK(t0) >= 1) {
  324 + tmp = ldfun(GET_OFFSET(t0, -1));
  325 + t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
379 } 326 }
380 327
381 - if (GET_LMASK(T0) >= 2) {  
382 - tmp = ldfun(GET_OFFSET(T0, -2));  
383 - T1 = (T1 & 0xFF00FFFF) | (tmp << 16); 328 + if (GET_LMASK(t0) >= 2) {
  329 + tmp = ldfun(GET_OFFSET(t0, -2));
  330 + t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
384 } 331 }
385 332
386 - if (GET_LMASK(T0) == 3) {  
387 - tmp = ldfun(GET_OFFSET(T0, -3));  
388 - T1 = (T1 & 0x00FFFFFF) | (tmp << 24); 333 + if (GET_LMASK(t0) == 3) {
  334 + tmp = ldfun(GET_OFFSET(t0, -3));
  335 + t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
389 } 336 }
390 - T1 = (int32_t)T1; 337 + return (int32_t)t1;
391 } 338 }
392 339
393 -void do_swl(int mem_idx) 340 +void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
394 { 341 {
395 #ifdef CONFIG_USER_ONLY 342 #ifdef CONFIG_USER_ONLY
396 #define stfun stb_raw 343 #define stfun stb_raw
@@ -405,19 +352,19 @@ void do_swl(int mem_idx) @@ -405,19 +352,19 @@ void do_swl(int mem_idx)
405 case 2: stfun = stb_user; break; 352 case 2: stfun = stb_user; break;
406 } 353 }
407 #endif 354 #endif
408 - stfun(T0, (uint8_t)(T1 >> 24)); 355 + stfun(t0, (uint8_t)(t1 >> 24));
409 356
410 - if (GET_LMASK(T0) <= 2)  
411 - stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 16)); 357 + if (GET_LMASK(t0) <= 2)
  358 + stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
412 359
413 - if (GET_LMASK(T0) <= 1)  
414 - stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 8)); 360 + if (GET_LMASK(t0) <= 1)
  361 + stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
415 362
416 - if (GET_LMASK(T0) == 0)  
417 - stfun(GET_OFFSET(T0, 3), (uint8_t)T1); 363 + if (GET_LMASK(t0) == 0)
  364 + stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
418 } 365 }
419 366
420 -void do_swr(int mem_idx) 367 +void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
421 { 368 {
422 #ifdef CONFIG_USER_ONLY 369 #ifdef CONFIG_USER_ONLY
423 #define stfun stb_raw 370 #define stfun stb_raw
@@ -432,16 +379,16 @@ void do_swr(int mem_idx) @@ -432,16 +379,16 @@ void do_swr(int mem_idx)
432 case 2: stfun = stb_user; break; 379 case 2: stfun = stb_user; break;
433 } 380 }
434 #endif 381 #endif
435 - stfun(T0, (uint8_t)T1); 382 + stfun(t0, (uint8_t)t1);
436 383
437 - if (GET_LMASK(T0) >= 1)  
438 - stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8)); 384 + if (GET_LMASK(t0) >= 1)
  385 + stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
439 386
440 - if (GET_LMASK(T0) >= 2)  
441 - stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16)); 387 + if (GET_LMASK(t0) >= 2)
  388 + stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
442 389
443 - if (GET_LMASK(T0) == 3)  
444 - stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24)); 390 + if (GET_LMASK(t0) == 3)
  391 + stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
445 } 392 }
446 393
447 #if defined(TARGET_MIPS64) 394 #if defined(TARGET_MIPS64)
@@ -454,14 +401,14 @@ void do_swr(int mem_idx) @@ -454,14 +401,14 @@ void do_swr(int mem_idx)
454 #define GET_LMASK64(v) (((v) & 7) ^ 7) 401 #define GET_LMASK64(v) (((v) & 7) ^ 7)
455 #endif 402 #endif
456 403
457 -void do_ldl(int mem_idx) 404 +target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
458 { 405 {
459 uint64_t tmp; 406 uint64_t tmp;
460 407
461 #ifdef CONFIG_USER_ONLY 408 #ifdef CONFIG_USER_ONLY
462 #define ldfun ldub_raw 409 #define ldfun ldub_raw
463 #else 410 #else
464 - target_ulong (*ldfun)(target_ulong); 411 + int (*ldfun)(target_ulong);
465 412
466 switch (mem_idx) 413 switch (mem_idx)
467 { 414 {
@@ -471,53 +418,55 @@ void do_ldl(int mem_idx) @@ -471,53 +418,55 @@ void do_ldl(int mem_idx)
471 case 2: ldfun = ldub_user; break; 418 case 2: ldfun = ldub_user; break;
472 } 419 }
473 #endif 420 #endif
474 - tmp = ldfun(T0);  
475 - T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); 421 + tmp = ldfun(t0);
  422 + t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
476 423
477 - if (GET_LMASK64(T0) <= 6) {  
478 - tmp = ldfun(GET_OFFSET(T0, 1));  
479 - T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); 424 + if (GET_LMASK64(t0) <= 6) {
  425 + tmp = ldfun(GET_OFFSET(t0, 1));
  426 + t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
480 } 427 }
481 428
482 - if (GET_LMASK64(T0) <= 5) {  
483 - tmp = ldfun(GET_OFFSET(T0, 2));  
484 - T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); 429 + if (GET_LMASK64(t0) <= 5) {
  430 + tmp = ldfun(GET_OFFSET(t0, 2));
  431 + t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
485 } 432 }
486 433
487 - if (GET_LMASK64(T0) <= 4) {  
488 - tmp = ldfun(GET_OFFSET(T0, 3));  
489 - T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); 434 + if (GET_LMASK64(t0) <= 4) {
  435 + tmp = ldfun(GET_OFFSET(t0, 3));
  436 + t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
490 } 437 }
491 438
492 - if (GET_LMASK64(T0) <= 3) {  
493 - tmp = ldfun(GET_OFFSET(T0, 4));  
494 - T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); 439 + if (GET_LMASK64(t0) <= 3) {
  440 + tmp = ldfun(GET_OFFSET(t0, 4));
  441 + t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
495 } 442 }
496 443
497 - if (GET_LMASK64(T0) <= 2) {  
498 - tmp = ldfun(GET_OFFSET(T0, 5));  
499 - T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); 444 + if (GET_LMASK64(t0) <= 2) {
  445 + tmp = ldfun(GET_OFFSET(t0, 5));
  446 + t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
500 } 447 }
501 448
502 - if (GET_LMASK64(T0) <= 1) {  
503 - tmp = ldfun(GET_OFFSET(T0, 6));  
504 - T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); 449 + if (GET_LMASK64(t0) <= 1) {
  450 + tmp = ldfun(GET_OFFSET(t0, 6));
  451 + t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
505 } 452 }
506 453
507 - if (GET_LMASK64(T0) == 0) {  
508 - tmp = ldfun(GET_OFFSET(T0, 7));  
509 - T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; 454 + if (GET_LMASK64(t0) == 0) {
  455 + tmp = ldfun(GET_OFFSET(t0, 7));
  456 + t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
510 } 457 }
  458 +
  459 + return t1;
511 } 460 }
512 461
513 -void do_ldr(int mem_idx) 462 +target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
514 { 463 {
515 uint64_t tmp; 464 uint64_t tmp;
516 465
517 #ifdef CONFIG_USER_ONLY 466 #ifdef CONFIG_USER_ONLY
518 #define ldfun ldub_raw 467 #define ldfun ldub_raw
519 #else 468 #else
520 - target_ulong (*ldfun)(target_ulong); 469 + int (*ldfun)(target_ulong);
521 470
522 switch (mem_idx) 471 switch (mem_idx)
523 { 472 {
@@ -527,46 +476,48 @@ void do_ldr(int mem_idx) @@ -527,46 +476,48 @@ void do_ldr(int mem_idx)
527 case 2: ldfun = ldub_user; break; 476 case 2: ldfun = ldub_user; break;
528 } 477 }
529 #endif 478 #endif
530 - tmp = ldfun(T0);  
531 - T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; 479 + tmp = ldfun(t0);
  480 + t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
532 481
533 - if (GET_LMASK64(T0) >= 1) {  
534 - tmp = ldfun(GET_OFFSET(T0, -1));  
535 - T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); 482 + if (GET_LMASK64(t0) >= 1) {
  483 + tmp = ldfun(GET_OFFSET(t0, -1));
  484 + t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
536 } 485 }
537 486
538 - if (GET_LMASK64(T0) >= 2) {  
539 - tmp = ldfun(GET_OFFSET(T0, -2));  
540 - T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); 487 + if (GET_LMASK64(t0) >= 2) {
  488 + tmp = ldfun(GET_OFFSET(t0, -2));
  489 + t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
541 } 490 }
542 491
543 - if (GET_LMASK64(T0) >= 3) {  
544 - tmp = ldfun(GET_OFFSET(T0, -3));  
545 - T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); 492 + if (GET_LMASK64(t0) >= 3) {
  493 + tmp = ldfun(GET_OFFSET(t0, -3));
  494 + t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
546 } 495 }
547 496
548 - if (GET_LMASK64(T0) >= 4) {  
549 - tmp = ldfun(GET_OFFSET(T0, -4));  
550 - T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); 497 + if (GET_LMASK64(t0) >= 4) {
  498 + tmp = ldfun(GET_OFFSET(t0, -4));
  499 + t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
551 } 500 }
552 501
553 - if (GET_LMASK64(T0) >= 5) {  
554 - tmp = ldfun(GET_OFFSET(T0, -5));  
555 - T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); 502 + if (GET_LMASK64(t0) >= 5) {
  503 + tmp = ldfun(GET_OFFSET(t0, -5));
  504 + t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
556 } 505 }
557 506
558 - if (GET_LMASK64(T0) >= 6) {  
559 - tmp = ldfun(GET_OFFSET(T0, -6));  
560 - T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); 507 + if (GET_LMASK64(t0) >= 6) {
  508 + tmp = ldfun(GET_OFFSET(t0, -6));
  509 + t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
561 } 510 }
562 511
563 - if (GET_LMASK64(T0) == 7) {  
564 - tmp = ldfun(GET_OFFSET(T0, -7));  
565 - T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); 512 + if (GET_LMASK64(t0) == 7) {
  513 + tmp = ldfun(GET_OFFSET(t0, -7));
  514 + t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
566 } 515 }
  516 +
  517 + return t1;
567 } 518 }
568 519
569 -void do_sdl(int mem_idx) 520 +void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
570 { 521 {
571 #ifdef CONFIG_USER_ONLY 522 #ifdef CONFIG_USER_ONLY
572 #define stfun stb_raw 523 #define stfun stb_raw
@@ -581,31 +532,31 @@ void do_sdl(int mem_idx) @@ -581,31 +532,31 @@ void do_sdl(int mem_idx)
581 case 2: stfun = stb_user; break; 532 case 2: stfun = stb_user; break;
582 } 533 }
583 #endif 534 #endif
584 - stfun(T0, (uint8_t)(T1 >> 56)); 535 + stfun(t0, (uint8_t)(t1 >> 56));
585 536
586 - if (GET_LMASK64(T0) <= 6)  
587 - stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 48)); 537 + if (GET_LMASK64(t0) <= 6)
  538 + stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
588 539
589 - if (GET_LMASK64(T0) <= 5)  
590 - stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 40)); 540 + if (GET_LMASK64(t0) <= 5)
  541 + stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
591 542
592 - if (GET_LMASK64(T0) <= 4)  
593 - stfun(GET_OFFSET(T0, 3), (uint8_t)(T1 >> 32)); 543 + if (GET_LMASK64(t0) <= 4)
  544 + stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
594 545
595 - if (GET_LMASK64(T0) <= 3)  
596 - stfun(GET_OFFSET(T0, 4), (uint8_t)(T1 >> 24)); 546 + if (GET_LMASK64(t0) <= 3)
  547 + stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
597 548
598 - if (GET_LMASK64(T0) <= 2)  
599 - stfun(GET_OFFSET(T0, 5), (uint8_t)(T1 >> 16)); 549 + if (GET_LMASK64(t0) <= 2)
  550 + stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
600 551
601 - if (GET_LMASK64(T0) <= 1)  
602 - stfun(GET_OFFSET(T0, 6), (uint8_t)(T1 >> 8)); 552 + if (GET_LMASK64(t0) <= 1)
  553 + stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
603 554
604 - if (GET_LMASK64(T0) <= 0)  
605 - stfun(GET_OFFSET(T0, 7), (uint8_t)T1); 555 + if (GET_LMASK64(t0) <= 0)
  556 + stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
606 } 557 }
607 558
608 -void do_sdr(int mem_idx) 559 +void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
609 { 560 {
610 #ifdef CONFIG_USER_ONLY 561 #ifdef CONFIG_USER_ONLY
611 #define stfun stb_raw 562 #define stfun stb_raw
@@ -620,28 +571,28 @@ void do_sdr(int mem_idx) @@ -620,28 +571,28 @@ void do_sdr(int mem_idx)
620 case 2: stfun = stb_user; break; 571 case 2: stfun = stb_user; break;
621 } 572 }
622 #endif 573 #endif
623 - stfun(T0, (uint8_t)T1); 574 + stfun(t0, (uint8_t)t1);
624 575
625 - if (GET_LMASK64(T0) >= 1)  
626 - stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8)); 576 + if (GET_LMASK64(t0) >= 1)
  577 + stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
627 578
628 - if (GET_LMASK64(T0) >= 2)  
629 - stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16)); 579 + if (GET_LMASK64(t0) >= 2)
  580 + stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
630 581
631 - if (GET_LMASK64(T0) >= 3)  
632 - stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24)); 582 + if (GET_LMASK64(t0) >= 3)
  583 + stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
633 584
634 - if (GET_LMASK64(T0) >= 4)  
635 - stfun(GET_OFFSET(T0, -4), (uint8_t)(T1 >> 32)); 585 + if (GET_LMASK64(t0) >= 4)
  586 + stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
636 587
637 - if (GET_LMASK64(T0) >= 5)  
638 - stfun(GET_OFFSET(T0, -5), (uint8_t)(T1 >> 40)); 588 + if (GET_LMASK64(t0) >= 5)
  589 + stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
639 590
640 - if (GET_LMASK64(T0) >= 6)  
641 - stfun(GET_OFFSET(T0, -6), (uint8_t)(T1 >> 48)); 591 + if (GET_LMASK64(t0) >= 6)
  592 + stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
642 593
643 - if (GET_LMASK64(T0) == 7)  
644 - stfun(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56)); 594 + if (GET_LMASK64(t0) == 7)
  595 + stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
645 } 596 }
646 #endif /* TARGET_MIPS64 */ 597 #endif /* TARGET_MIPS64 */
647 598
@@ -699,203 +650,207 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global) @@ -699,203 +650,207 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global)
699 #else 650 #else
700 651
701 /* CP0 helpers */ 652 /* CP0 helpers */
702 -void do_mfc0_mvpcontrol (void) 653 +target_ulong do_mfc0_mvpcontrol (target_ulong t0)
703 { 654 {
704 - T0 = env->mvp->CP0_MVPControl; 655 + return env->mvp->CP0_MVPControl;
705 } 656 }
706 657
707 -void do_mfc0_mvpconf0 (void) 658 +target_ulong do_mfc0_mvpconf0 (target_ulong t0)
708 { 659 {
709 - T0 = env->mvp->CP0_MVPConf0; 660 + return env->mvp->CP0_MVPConf0;
710 } 661 }
711 662
712 -void do_mfc0_mvpconf1 (void) 663 +target_ulong do_mfc0_mvpconf1 (target_ulong t0)
713 { 664 {
714 - T0 = env->mvp->CP0_MVPConf1; 665 + return env->mvp->CP0_MVPConf1;
715 } 666 }
716 667
717 -void do_mfc0_random (void) 668 +target_ulong do_mfc0_random (target_ulong t0)
718 { 669 {
719 - T0 = (int32_t)cpu_mips_get_random(env); 670 + return (int32_t)cpu_mips_get_random(env);
720 } 671 }
721 672
722 -void do_mfc0_tcstatus (void) 673 +target_ulong do_mfc0_tcstatus (target_ulong t0)
723 { 674 {
724 - T0 = env->CP0_TCStatus[env->current_tc]; 675 + return env->CP0_TCStatus[env->current_tc];
725 } 676 }
726 677
727 -void do_mftc0_tcstatus(void) 678 +target_ulong do_mftc0_tcstatus(target_ulong t0)
728 { 679 {
729 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 680 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
730 681
731 - T0 = env->CP0_TCStatus[other_tc]; 682 + return env->CP0_TCStatus[other_tc];
732 } 683 }
733 684
734 -void do_mfc0_tcbind (void) 685 +target_ulong do_mfc0_tcbind (target_ulong t0)
735 { 686 {
736 - T0 = env->CP0_TCBind[env->current_tc]; 687 + return env->CP0_TCBind[env->current_tc];
737 } 688 }
738 689
739 -void do_mftc0_tcbind(void) 690 +target_ulong do_mftc0_tcbind(target_ulong t0)
740 { 691 {
741 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
742 693
743 - T0 = env->CP0_TCBind[other_tc]; 694 + return env->CP0_TCBind[other_tc];
744 } 695 }
745 696
746 -void do_mfc0_tcrestart (void) 697 +target_ulong do_mfc0_tcrestart (target_ulong t0)
747 { 698 {
748 - T0 = env->PC[env->current_tc]; 699 + return env->PC[env->current_tc];
749 } 700 }
750 701
751 -void do_mftc0_tcrestart(void) 702 +target_ulong do_mftc0_tcrestart(target_ulong t0)
752 { 703 {
753 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
754 705
755 - T0 = env->PC[other_tc]; 706 + return env->PC[other_tc];
756 } 707 }
757 708
758 -void do_mfc0_tchalt (void) 709 +target_ulong do_mfc0_tchalt (target_ulong t0)
759 { 710 {
760 - T0 = env->CP0_TCHalt[env->current_tc]; 711 + return env->CP0_TCHalt[env->current_tc];
761 } 712 }
762 713
763 -void do_mftc0_tchalt(void) 714 +target_ulong do_mftc0_tchalt(target_ulong t0)
764 { 715 {
765 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
766 717
767 - T0 = env->CP0_TCHalt[other_tc]; 718 + return env->CP0_TCHalt[other_tc];
768 } 719 }
769 720
770 -void do_mfc0_tccontext (void) 721 +target_ulong do_mfc0_tccontext (target_ulong t0)
771 { 722 {
772 - T0 = env->CP0_TCContext[env->current_tc]; 723 + return env->CP0_TCContext[env->current_tc];
773 } 724 }
774 725
775 -void do_mftc0_tccontext(void) 726 +target_ulong do_mftc0_tccontext(target_ulong t0)
776 { 727 {
777 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
778 729
779 - T0 = env->CP0_TCContext[other_tc]; 730 + return env->CP0_TCContext[other_tc];
780 } 731 }
781 732
782 -void do_mfc0_tcschedule (void) 733 +target_ulong do_mfc0_tcschedule (target_ulong t0)
783 { 734 {
784 - T0 = env->CP0_TCSchedule[env->current_tc]; 735 + return env->CP0_TCSchedule[env->current_tc];
785 } 736 }
786 737
787 -void do_mftc0_tcschedule(void) 738 +target_ulong do_mftc0_tcschedule(target_ulong t0)
788 { 739 {
789 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
790 741
791 - T0 = env->CP0_TCSchedule[other_tc]; 742 + return env->CP0_TCSchedule[other_tc];
792 } 743 }
793 744
794 -void do_mfc0_tcschefback (void) 745 +target_ulong do_mfc0_tcschefback (target_ulong t0)
795 { 746 {
796 - T0 = env->CP0_TCScheFBack[env->current_tc]; 747 + return env->CP0_TCScheFBack[env->current_tc];
797 } 748 }
798 749
799 -void do_mftc0_tcschefback(void) 750 +target_ulong do_mftc0_tcschefback(target_ulong t0)
800 { 751 {
801 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
802 753
803 - T0 = env->CP0_TCScheFBack[other_tc]; 754 + return env->CP0_TCScheFBack[other_tc];
804 } 755 }
805 756
806 -void do_mfc0_count (void) 757 +target_ulong do_mfc0_count (target_ulong t0)
807 { 758 {
808 - T0 = (int32_t)cpu_mips_get_count(env); 759 + return (int32_t)cpu_mips_get_count(env);
809 } 760 }
810 761
811 -void do_mftc0_entryhi(void) 762 +target_ulong do_mftc0_entryhi(target_ulong t0)
812 { 763 {
813 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 764 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
814 765
815 - T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); 766 + return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
816 } 767 }
817 768
818 -void do_mftc0_status(void) 769 +target_ulong do_mftc0_status(target_ulong t0)
819 { 770 {
820 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
821 uint32_t tcstatus = env->CP0_TCStatus[other_tc]; 772 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
822 773
823 - T0 = env->CP0_Status & ~0xf1000018;  
824 - T0 |= tcstatus & (0xf << CP0TCSt_TCU0);  
825 - T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);  
826 - T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); 774 + t0 = env->CP0_Status & ~0xf1000018;
  775 + t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
  776 + t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
  777 + t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
  778 +
  779 + return t0;
827 } 780 }
828 781
829 -void do_mfc0_lladdr (void) 782 +target_ulong do_mfc0_lladdr (target_ulong t0)
830 { 783 {
831 - T0 = (int32_t)env->CP0_LLAddr >> 4; 784 + return (int32_t)env->CP0_LLAddr >> 4;
832 } 785 }
833 786
834 -void do_mfc0_watchlo (uint32_t sel) 787 +target_ulong do_mfc0_watchlo (target_ulong t0, uint32_t sel)
835 { 788 {
836 - T0 = (int32_t)env->CP0_WatchLo[sel]; 789 + return (int32_t)env->CP0_WatchLo[sel];
837 } 790 }
838 791
839 -void do_mfc0_watchhi (uint32_t sel) 792 +target_ulong do_mfc0_watchhi (target_ulong t0, uint32_t sel)
840 { 793 {
841 - T0 = env->CP0_WatchHi[sel]; 794 + return env->CP0_WatchHi[sel];
842 } 795 }
843 796
844 -void do_mfc0_debug (void) 797 +target_ulong do_mfc0_debug (target_ulong t0)
845 { 798 {
846 - T0 = env->CP0_Debug; 799 + t0 = env->CP0_Debug;
847 if (env->hflags & MIPS_HFLAG_DM) 800 if (env->hflags & MIPS_HFLAG_DM)
848 - T0 |= 1 << CP0DB_DM; 801 + t0 |= 1 << CP0DB_DM;
  802 +
  803 + return t0;
849 } 804 }
850 805
851 -void do_mftc0_debug(void) 806 +target_ulong do_mftc0_debug(target_ulong t0)
852 { 807 {
853 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 808 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
854 809
855 /* XXX: Might be wrong, check with EJTAG spec. */ 810 /* XXX: Might be wrong, check with EJTAG spec. */
856 - T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |  
857 - (env->CP0_Debug_tcstatus[other_tc] &  
858 - ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); 811 + return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
  812 + (env->CP0_Debug_tcstatus[other_tc] &
  813 + ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
859 } 814 }
860 815
861 #if defined(TARGET_MIPS64) 816 #if defined(TARGET_MIPS64)
862 -void do_dmfc0_tcrestart (void) 817 +target_ulong do_dmfc0_tcrestart (target_ulong t0)
863 { 818 {
864 - T0 = env->PC[env->current_tc]; 819 + return env->PC[env->current_tc];
865 } 820 }
866 821
867 -void do_dmfc0_tchalt (void) 822 +target_ulong do_dmfc0_tchalt (target_ulong t0)
868 { 823 {
869 - T0 = env->CP0_TCHalt[env->current_tc]; 824 + return env->CP0_TCHalt[env->current_tc];
870 } 825 }
871 826
872 -void do_dmfc0_tccontext (void) 827 +target_ulong do_dmfc0_tccontext (target_ulong t0)
873 { 828 {
874 - T0 = env->CP0_TCContext[env->current_tc]; 829 + return env->CP0_TCContext[env->current_tc];
875 } 830 }
876 831
877 -void do_dmfc0_tcschedule (void) 832 +target_ulong do_dmfc0_tcschedule (target_ulong t0)
878 { 833 {
879 - T0 = env->CP0_TCSchedule[env->current_tc]; 834 + return env->CP0_TCSchedule[env->current_tc];
880 } 835 }
881 836
882 -void do_dmfc0_tcschefback (void) 837 +target_ulong do_dmfc0_tcschefback (target_ulong t0)
883 { 838 {
884 - T0 = env->CP0_TCScheFBack[env->current_tc]; 839 + return env->CP0_TCScheFBack[env->current_tc];
885 } 840 }
886 841
887 -void do_dmfc0_lladdr (void) 842 +target_ulong do_dmfc0_lladdr (target_ulong t0)
888 { 843 {
889 - T0 = env->CP0_LLAddr >> 4; 844 + return env->CP0_LLAddr >> 4;
890 } 845 }
891 846
892 -void do_dmfc0_watchlo (uint32_t sel) 847 +target_ulong do_dmfc0_watchlo (target_ulong t0, uint32_t sel)
893 { 848 {
894 - T0 = env->CP0_WatchLo[sel]; 849 + return env->CP0_WatchLo[sel];
895 } 850 }
896 #endif /* TARGET_MIPS64 */ 851 #endif /* TARGET_MIPS64 */
897 852
898 -void do_mtc0_index (void) 853 +void do_mtc0_index (target_ulong t0)
899 { 854 {
900 int num = 1; 855 int num = 1;
901 unsigned int tmp = env->tlb->nb_tlb; 856 unsigned int tmp = env->tlb->nb_tlb;
@@ -904,10 +859,10 @@ void do_mtc0_index (void) @@ -904,10 +859,10 @@ void do_mtc0_index (void)
904 tmp >>= 1; 859 tmp >>= 1;
905 num <<= 1; 860 num <<= 1;
906 } while (tmp); 861 } while (tmp);
907 - env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1)); 862 + env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
908 } 863 }
909 864
910 -void do_mtc0_mvpcontrol (void) 865 +void do_mtc0_mvpcontrol (target_ulong t0)
911 { 866 {
912 uint32_t mask = 0; 867 uint32_t mask = 0;
913 uint32_t newval; 868 uint32_t newval;
@@ -917,21 +872,21 @@ void do_mtc0_mvpcontrol (void) @@ -917,21 +872,21 @@ void do_mtc0_mvpcontrol (void)
917 (1 << CP0MVPCo_EVP); 872 (1 << CP0MVPCo_EVP);
918 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) 873 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
919 mask |= (1 << CP0MVPCo_STLB); 874 mask |= (1 << CP0MVPCo_STLB);
920 - newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); 875 + newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
921 876
922 // TODO: Enable/disable shared TLB, enable/disable VPEs. 877 // TODO: Enable/disable shared TLB, enable/disable VPEs.
923 878
924 env->mvp->CP0_MVPControl = newval; 879 env->mvp->CP0_MVPControl = newval;
925 } 880 }
926 881
927 -void do_mtc0_vpecontrol (void) 882 +void do_mtc0_vpecontrol (target_ulong t0)
928 { 883 {
929 uint32_t mask; 884 uint32_t mask;
930 uint32_t newval; 885 uint32_t newval;
931 886
932 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | 887 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
933 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); 888 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
934 - newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); 889 + newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
935 890
936 /* Yield scheduler intercept not implemented. */ 891 /* Yield scheduler intercept not implemented. */
937 /* Gating storage scheduler intercept not implemented. */ 892 /* Gating storage scheduler intercept not implemented. */
@@ -941,7 +896,7 @@ void do_mtc0_vpecontrol (void) @@ -941,7 +896,7 @@ void do_mtc0_vpecontrol (void)
941 env->CP0_VPEControl = newval; 896 env->CP0_VPEControl = newval;
942 } 897 }
943 898
944 -void do_mtc0_vpeconf0 (void) 899 +void do_mtc0_vpeconf0 (target_ulong t0)
945 { 900 {
946 uint32_t mask = 0; 901 uint32_t mask = 0;
947 uint32_t newval; 902 uint32_t newval;
@@ -951,14 +906,14 @@ void do_mtc0_vpeconf0 (void) @@ -951,14 +906,14 @@ void do_mtc0_vpeconf0 (void)
951 mask |= (0xff << CP0VPEC0_XTC); 906 mask |= (0xff << CP0VPEC0_XTC);
952 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 907 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
953 } 908 }
954 - newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); 909 + newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
955 910
956 // TODO: TC exclusive handling due to ERL/EXL. 911 // TODO: TC exclusive handling due to ERL/EXL.
957 912
958 env->CP0_VPEConf0 = newval; 913 env->CP0_VPEConf0 = newval;
959 } 914 }
960 915
961 -void do_mtc0_vpeconf1 (void) 916 +void do_mtc0_vpeconf1 (target_ulong t0)
962 { 917 {
963 uint32_t mask = 0; 918 uint32_t mask = 0;
964 uint32_t newval; 919 uint32_t newval;
@@ -966,7 +921,7 @@ void do_mtc0_vpeconf1 (void) @@ -966,7 +921,7 @@ void do_mtc0_vpeconf1 (void)
966 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) 921 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
967 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | 922 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
968 (0xff << CP0VPEC1_NCP1); 923 (0xff << CP0VPEC1_NCP1);
969 - newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); 924 + newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
970 925
971 /* UDI not implemented. */ 926 /* UDI not implemented. */
972 /* CP2 not implemented. */ 927 /* CP2 not implemented. */
@@ -976,57 +931,57 @@ void do_mtc0_vpeconf1 (void) @@ -976,57 +931,57 @@ void do_mtc0_vpeconf1 (void)
976 env->CP0_VPEConf1 = newval; 931 env->CP0_VPEConf1 = newval;
977 } 932 }
978 933
979 -void do_mtc0_yqmask (void) 934 +void do_mtc0_yqmask (target_ulong t0)
980 { 935 {
981 /* Yield qualifier inputs not implemented. */ 936 /* Yield qualifier inputs not implemented. */
982 env->CP0_YQMask = 0x00000000; 937 env->CP0_YQMask = 0x00000000;
983 } 938 }
984 939
985 -void do_mtc0_vpeopt (void) 940 +void do_mtc0_vpeopt (target_ulong t0)
986 { 941 {
987 - env->CP0_VPEOpt = T0 & 0x0000ffff; 942 + env->CP0_VPEOpt = t0 & 0x0000ffff;
988 } 943 }
989 944
990 -void do_mtc0_entrylo0 (void) 945 +void do_mtc0_entrylo0 (target_ulong t0)
991 { 946 {
992 /* Large physaddr (PABITS) not implemented */ 947 /* Large physaddr (PABITS) not implemented */
993 /* 1k pages not implemented */ 948 /* 1k pages not implemented */
994 - env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; 949 + env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
995 } 950 }
996 951
997 -void do_mtc0_tcstatus (void) 952 +void do_mtc0_tcstatus (target_ulong t0)
998 { 953 {
999 uint32_t mask = env->CP0_TCStatus_rw_bitmask; 954 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1000 uint32_t newval; 955 uint32_t newval;
1001 956
1002 - newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); 957 + newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (t0 & mask);
1003 958
1004 // TODO: Sync with CP0_Status. 959 // TODO: Sync with CP0_Status.
1005 960
1006 env->CP0_TCStatus[env->current_tc] = newval; 961 env->CP0_TCStatus[env->current_tc] = newval;
1007 } 962 }
1008 963
1009 -void do_mttc0_tcstatus (void) 964 +void do_mttc0_tcstatus (target_ulong t0)
1010 { 965 {
1011 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 966 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012 967
1013 // TODO: Sync with CP0_Status. 968 // TODO: Sync with CP0_Status.
1014 969
1015 - env->CP0_TCStatus[other_tc] = T0; 970 + env->CP0_TCStatus[other_tc] = t0;
1016 } 971 }
1017 972
1018 -void do_mtc0_tcbind (void) 973 +void do_mtc0_tcbind (target_ulong t0)
1019 { 974 {
1020 uint32_t mask = (1 << CP0TCBd_TBE); 975 uint32_t mask = (1 << CP0TCBd_TBE);
1021 uint32_t newval; 976 uint32_t newval;
1022 977
1023 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) 978 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1024 mask |= (1 << CP0TCBd_CurVPE); 979 mask |= (1 << CP0TCBd_CurVPE);
1025 - newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); 980 + newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (t0 & mask);
1026 env->CP0_TCBind[env->current_tc] = newval; 981 env->CP0_TCBind[env->current_tc] = newval;
1027 } 982 }
1028 983
1029 -void do_mttc0_tcbind (void) 984 +void do_mttc0_tcbind (target_ulong t0)
1030 { 985 {
1031 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 986 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1032 uint32_t mask = (1 << CP0TCBd_TBE); 987 uint32_t mask = (1 << CP0TCBd_TBE);
@@ -1034,99 +989,99 @@ void do_mttc0_tcbind (void) @@ -1034,99 +989,99 @@ void do_mttc0_tcbind (void)
1034 989
1035 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) 990 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1036 mask |= (1 << CP0TCBd_CurVPE); 991 mask |= (1 << CP0TCBd_CurVPE);
1037 - newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); 992 + newval = (env->CP0_TCBind[other_tc] & ~mask) | (t0 & mask);
1038 env->CP0_TCBind[other_tc] = newval; 993 env->CP0_TCBind[other_tc] = newval;
1039 } 994 }
1040 995
1041 -void do_mtc0_tcrestart (void) 996 +void do_mtc0_tcrestart (target_ulong t0)
1042 { 997 {
1043 - env->PC[env->current_tc] = T0; 998 + env->PC[env->current_tc] = t0;
1044 env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS); 999 env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1045 env->CP0_LLAddr = 0ULL; 1000 env->CP0_LLAddr = 0ULL;
1046 /* MIPS16 not implemented. */ 1001 /* MIPS16 not implemented. */
1047 } 1002 }
1048 1003
1049 -void do_mttc0_tcrestart (void) 1004 +void do_mttc0_tcrestart (target_ulong t0)
1050 { 1005 {
1051 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1006 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1052 1007
1053 - env->PC[other_tc] = T0; 1008 + env->PC[other_tc] = t0;
1054 env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS); 1009 env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1055 env->CP0_LLAddr = 0ULL; 1010 env->CP0_LLAddr = 0ULL;
1056 /* MIPS16 not implemented. */ 1011 /* MIPS16 not implemented. */
1057 } 1012 }
1058 1013
1059 -void do_mtc0_tchalt (void) 1014 +void do_mtc0_tchalt (target_ulong t0)
1060 { 1015 {
1061 - env->CP0_TCHalt[env->current_tc] = T0 & 0x1; 1016 + env->CP0_TCHalt[env->current_tc] = t0 & 0x1;
1062 1017
1063 // TODO: Halt TC / Restart (if allocated+active) TC. 1018 // TODO: Halt TC / Restart (if allocated+active) TC.
1064 } 1019 }
1065 1020
1066 -void do_mttc0_tchalt (void) 1021 +void do_mttc0_tchalt (target_ulong t0)
1067 { 1022 {
1068 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1023 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1069 1024
1070 // TODO: Halt TC / Restart (if allocated+active) TC. 1025 // TODO: Halt TC / Restart (if allocated+active) TC.
1071 1026
1072 - env->CP0_TCHalt[other_tc] = T0; 1027 + env->CP0_TCHalt[other_tc] = t0;
1073 } 1028 }
1074 1029
1075 -void do_mtc0_tccontext (void) 1030 +void do_mtc0_tccontext (target_ulong t0)
1076 { 1031 {
1077 - env->CP0_TCContext[env->current_tc] = T0; 1032 + env->CP0_TCContext[env->current_tc] = t0;
1078 } 1033 }
1079 1034
1080 -void do_mttc0_tccontext (void) 1035 +void do_mttc0_tccontext (target_ulong t0)
1081 { 1036 {
1082 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1037 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1083 1038
1084 - env->CP0_TCContext[other_tc] = T0; 1039 + env->CP0_TCContext[other_tc] = t0;
1085 } 1040 }
1086 1041
1087 -void do_mtc0_tcschedule (void) 1042 +void do_mtc0_tcschedule (target_ulong t0)
1088 { 1043 {
1089 - env->CP0_TCSchedule[env->current_tc] = T0; 1044 + env->CP0_TCSchedule[env->current_tc] = t0;
1090 } 1045 }
1091 1046
1092 -void do_mttc0_tcschedule (void) 1047 +void do_mttc0_tcschedule (target_ulong t0)
1093 { 1048 {
1094 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1049 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1095 1050
1096 - env->CP0_TCSchedule[other_tc] = T0; 1051 + env->CP0_TCSchedule[other_tc] = t0;
1097 } 1052 }
1098 1053
1099 -void do_mtc0_tcschefback (void) 1054 +void do_mtc0_tcschefback (target_ulong t0)
1100 { 1055 {
1101 - env->CP0_TCScheFBack[env->current_tc] = T0; 1056 + env->CP0_TCScheFBack[env->current_tc] = t0;
1102 } 1057 }
1103 1058
1104 -void do_mttc0_tcschefback (void) 1059 +void do_mttc0_tcschefback (target_ulong t0)
1105 { 1060 {
1106 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1061 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1107 1062
1108 - env->CP0_TCScheFBack[other_tc] = T0; 1063 + env->CP0_TCScheFBack[other_tc] = t0;
1109 } 1064 }
1110 1065
1111 -void do_mtc0_entrylo1 (void) 1066 +void do_mtc0_entrylo1 (target_ulong t0)
1112 { 1067 {
1113 /* Large physaddr (PABITS) not implemented */ 1068 /* Large physaddr (PABITS) not implemented */
1114 /* 1k pages not implemented */ 1069 /* 1k pages not implemented */
1115 - env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; 1070 + env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
1116 } 1071 }
1117 1072
1118 -void do_mtc0_context (void) 1073 +void do_mtc0_context (target_ulong t0)
1119 { 1074 {
1120 - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); 1075 + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
1121 } 1076 }
1122 1077
1123 -void do_mtc0_pagemask (void) 1078 +void do_mtc0_pagemask (target_ulong t0)
1124 { 1079 {
1125 /* 1k pages not implemented */ 1080 /* 1k pages not implemented */
1126 - env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); 1081 + env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1127 } 1082 }
1128 1083
1129 -void do_mtc0_pagegrain (void) 1084 +void do_mtc0_pagegrain (target_ulong t0)
1130 { 1085 {
1131 /* SmartMIPS not implemented */ 1086 /* SmartMIPS not implemented */
1132 /* Large physaddr (PABITS) not implemented */ 1087 /* Large physaddr (PABITS) not implemented */
@@ -1134,52 +1089,52 @@ void do_mtc0_pagegrain (void) @@ -1134,52 +1089,52 @@ void do_mtc0_pagegrain (void)
1134 env->CP0_PageGrain = 0; 1089 env->CP0_PageGrain = 0;
1135 } 1090 }
1136 1091
1137 -void do_mtc0_wired (void) 1092 +void do_mtc0_wired (target_ulong t0)
1138 { 1093 {
1139 - env->CP0_Wired = T0 % env->tlb->nb_tlb; 1094 + env->CP0_Wired = t0 % env->tlb->nb_tlb;
1140 } 1095 }
1141 1096
1142 -void do_mtc0_srsconf0 (void) 1097 +void do_mtc0_srsconf0 (target_ulong t0)
1143 { 1098 {
1144 - env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; 1099 + env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
1145 } 1100 }
1146 1101
1147 -void do_mtc0_srsconf1 (void) 1102 +void do_mtc0_srsconf1 (target_ulong t0)
1148 { 1103 {
1149 - env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; 1104 + env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
1150 } 1105 }
1151 1106
1152 -void do_mtc0_srsconf2 (void) 1107 +void do_mtc0_srsconf2 (target_ulong t0)
1153 { 1108 {
1154 - env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; 1109 + env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
1155 } 1110 }
1156 1111
1157 -void do_mtc0_srsconf3 (void) 1112 +void do_mtc0_srsconf3 (target_ulong t0)
1158 { 1113 {
1159 - env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; 1114 + env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
1160 } 1115 }
1161 1116
1162 -void do_mtc0_srsconf4 (void) 1117 +void do_mtc0_srsconf4 (target_ulong t0)
1163 { 1118 {
1164 - env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; 1119 + env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
1165 } 1120 }
1166 1121
1167 -void do_mtc0_hwrena (void) 1122 +void do_mtc0_hwrena (target_ulong t0)
1168 { 1123 {
1169 - env->CP0_HWREna = T0 & 0x0000000F; 1124 + env->CP0_HWREna = t0 & 0x0000000F;
1170 } 1125 }
1171 1126
1172 -void do_mtc0_count (void) 1127 +void do_mtc0_count (target_ulong t0)
1173 { 1128 {
1174 - cpu_mips_store_count(env, T0); 1129 + cpu_mips_store_count(env, t0);
1175 } 1130 }
1176 1131
1177 -void do_mtc0_entryhi (void) 1132 +void do_mtc0_entryhi (target_ulong t0)
1178 { 1133 {
1179 target_ulong old, val; 1134 target_ulong old, val;
1180 1135
1181 /* 1k pages not implemented */ 1136 /* 1k pages not implemented */
1182 - val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); 1137 + val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1183 #if defined(TARGET_MIPS64) 1138 #if defined(TARGET_MIPS64)
1184 val &= env->SEGMask; 1139 val &= env->SEGMask;
1185 #endif 1140 #endif
@@ -1194,25 +1149,25 @@ void do_mtc0_entryhi (void) @@ -1194,25 +1149,25 @@ void do_mtc0_entryhi (void)
1194 cpu_mips_tlb_flush(env, 1); 1149 cpu_mips_tlb_flush(env, 1);
1195 } 1150 }
1196 1151
1197 -void do_mttc0_entryhi(void) 1152 +void do_mttc0_entryhi(target_ulong t0)
1198 { 1153 {
1199 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1154 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1200 1155
1201 - env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);  
1202 - env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); 1156 + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
  1157 + env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (t0 & 0xff);
1203 } 1158 }
1204 1159
1205 -void do_mtc0_compare (void) 1160 +void do_mtc0_compare (target_ulong t0)
1206 { 1161 {
1207 - cpu_mips_store_compare(env, T0); 1162 + cpu_mips_store_compare(env, t0);
1208 } 1163 }
1209 1164
1210 -void do_mtc0_status (void) 1165 +void do_mtc0_status (target_ulong t0)
1211 { 1166 {
1212 uint32_t val, old; 1167 uint32_t val, old;
1213 uint32_t mask = env->CP0_Status_rw_bitmask; 1168 uint32_t mask = env->CP0_Status_rw_bitmask;
1214 1169
1215 - val = T0 & mask; 1170 + val = t0 & mask;
1216 old = env->CP0_Status; 1171 old = env->CP0_Status;
1217 env->CP0_Status = (env->CP0_Status & ~mask) | val; 1172 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1218 compute_hflags(env); 1173 compute_hflags(env);
@@ -1221,31 +1176,31 @@ void do_mtc0_status (void) @@ -1221,31 +1176,31 @@ void do_mtc0_status (void)
1221 cpu_mips_update_irq(env); 1176 cpu_mips_update_irq(env);
1222 } 1177 }
1223 1178
1224 -void do_mttc0_status(void) 1179 +void do_mttc0_status(target_ulong t0)
1225 { 1180 {
1226 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1181 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1227 uint32_t tcstatus = env->CP0_TCStatus[other_tc]; 1182 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1228 1183
1229 - env->CP0_Status = T0 & ~0xf1000018;  
1230 - tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));  
1231 - tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));  
1232 - tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); 1184 + env->CP0_Status = t0 & ~0xf1000018;
  1185 + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
  1186 + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
  1187 + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1233 env->CP0_TCStatus[other_tc] = tcstatus; 1188 env->CP0_TCStatus[other_tc] = tcstatus;
1234 } 1189 }
1235 1190
1236 -void do_mtc0_intctl (void) 1191 +void do_mtc0_intctl (target_ulong t0)
1237 { 1192 {
1238 /* vectored interrupts not implemented, no performance counters. */ 1193 /* vectored interrupts not implemented, no performance counters. */
1239 - env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); 1194 + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
1240 } 1195 }
1241 1196
1242 -void do_mtc0_srsctl (void) 1197 +void do_mtc0_srsctl (target_ulong t0)
1243 { 1198 {
1244 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); 1199 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1245 - env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); 1200 + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
1246 } 1201 }
1247 1202
1248 -void do_mtc0_cause (void) 1203 +void do_mtc0_cause (target_ulong t0)
1249 { 1204 {
1250 uint32_t mask = 0x00C00300; 1205 uint32_t mask = 0x00C00300;
1251 uint32_t old = env->CP0_Cause; 1206 uint32_t old = env->CP0_Cause;
@@ -1253,7 +1208,7 @@ void do_mtc0_cause (void) @@ -1253,7 +1208,7 @@ void do_mtc0_cause (void)
1253 if (env->insn_flags & ISA_MIPS32R2) 1208 if (env->insn_flags & ISA_MIPS32R2)
1254 mask |= 1 << CP0Ca_DC; 1209 mask |= 1 << CP0Ca_DC;
1255 1210
1256 - env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); 1211 + env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
1257 1212
1258 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { 1213 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1259 if (env->CP0_Cause & (1 << CP0Ca_DC)) 1214 if (env->CP0_Cause & (1 << CP0Ca_DC))
@@ -1264,95 +1219,95 @@ void do_mtc0_cause (void) @@ -1264,95 +1219,95 @@ void do_mtc0_cause (void)
1264 1219
1265 /* Handle the software interrupt as an hardware one, as they 1220 /* Handle the software interrupt as an hardware one, as they
1266 are very similar */ 1221 are very similar */
1267 - if (T0 & CP0Ca_IP_mask) { 1222 + if (t0 & CP0Ca_IP_mask) {
1268 cpu_mips_update_irq(env); 1223 cpu_mips_update_irq(env);
1269 } 1224 }
1270 } 1225 }
1271 1226
1272 -void do_mtc0_ebase (void) 1227 +void do_mtc0_ebase (target_ulong t0)
1273 { 1228 {
1274 /* vectored interrupts not implemented */ 1229 /* vectored interrupts not implemented */
1275 /* Multi-CPU not implemented */ 1230 /* Multi-CPU not implemented */
1276 - env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); 1231 + env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
1277 } 1232 }
1278 1233
1279 -void do_mtc0_config0 (void) 1234 +void do_mtc0_config0 (target_ulong t0)
1280 { 1235 {
1281 - env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); 1236 + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
1282 } 1237 }
1283 1238
1284 -void do_mtc0_config2 (void) 1239 +void do_mtc0_config2 (target_ulong t0)
1285 { 1240 {
1286 /* tertiary/secondary caches not implemented */ 1241 /* tertiary/secondary caches not implemented */
1287 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); 1242 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1288 } 1243 }
1289 1244
1290 -void do_mtc0_watchlo (uint32_t sel) 1245 +void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
1291 { 1246 {
1292 /* Watch exceptions for instructions, data loads, data stores 1247 /* Watch exceptions for instructions, data loads, data stores
1293 not implemented. */ 1248 not implemented. */
1294 - env->CP0_WatchLo[sel] = (T0 & ~0x7); 1249 + env->CP0_WatchLo[sel] = (t0 & ~0x7);
1295 } 1250 }
1296 1251
1297 -void do_mtc0_watchhi (uint32_t sel) 1252 +void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
1298 { 1253 {
1299 - env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8);  
1300 - env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7); 1254 + env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
  1255 + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
1301 } 1256 }
1302 1257
1303 -void do_mtc0_xcontext (void) 1258 +void do_mtc0_xcontext (target_ulong t0)
1304 { 1259 {
1305 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; 1260 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1306 - env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); 1261 + env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
1307 } 1262 }
1308 1263
1309 -void do_mtc0_framemask (void) 1264 +void do_mtc0_framemask (target_ulong t0)
1310 { 1265 {
1311 - env->CP0_Framemask = T0; /* XXX */ 1266 + env->CP0_Framemask = t0; /* XXX */
1312 } 1267 }
1313 1268
1314 -void do_mtc0_debug (void) 1269 +void do_mtc0_debug (target_ulong t0)
1315 { 1270 {
1316 - env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);  
1317 - if (T0 & (1 << CP0DB_DM)) 1271 + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
  1272 + if (t0 & (1 << CP0DB_DM))
1318 env->hflags |= MIPS_HFLAG_DM; 1273 env->hflags |= MIPS_HFLAG_DM;
1319 else 1274 else
1320 env->hflags &= ~MIPS_HFLAG_DM; 1275 env->hflags &= ~MIPS_HFLAG_DM;
1321 } 1276 }
1322 1277
1323 -void do_mttc0_debug(void) 1278 +void do_mttc0_debug(target_ulong t0)
1324 { 1279 {
1325 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1280 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1326 1281
1327 /* XXX: Might be wrong, check with EJTAG spec. */ 1282 /* XXX: Might be wrong, check with EJTAG spec. */
1328 - env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); 1283 + env->CP0_Debug_tcstatus[other_tc] = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1329 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | 1284 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1330 - (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); 1285 + (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1331 } 1286 }
1332 1287
1333 -void do_mtc0_performance0 (void) 1288 +void do_mtc0_performance0 (target_ulong t0)
1334 { 1289 {
1335 - env->CP0_Performance0 = T0 & 0x000007ff; 1290 + env->CP0_Performance0 = t0 & 0x000007ff;
1336 } 1291 }
1337 1292
1338 -void do_mtc0_taglo (void) 1293 +void do_mtc0_taglo (target_ulong t0)
1339 { 1294 {
1340 - env->CP0_TagLo = T0 & 0xFFFFFCF6; 1295 + env->CP0_TagLo = t0 & 0xFFFFFCF6;
1341 } 1296 }
1342 1297
1343 -void do_mtc0_datalo (void) 1298 +void do_mtc0_datalo (target_ulong t0)
1344 { 1299 {
1345 - env->CP0_DataLo = T0; /* XXX */ 1300 + env->CP0_DataLo = t0; /* XXX */
1346 } 1301 }
1347 1302
1348 -void do_mtc0_taghi (void) 1303 +void do_mtc0_taghi (target_ulong t0)
1349 { 1304 {
1350 - env->CP0_TagHi = T0; /* XXX */ 1305 + env->CP0_TagHi = t0; /* XXX */
1351 } 1306 }
1352 1307
1353 -void do_mtc0_datahi (void) 1308 +void do_mtc0_datahi (target_ulong t0)
1354 { 1309 {
1355 - env->CP0_DataHi = T0; /* XXX */ 1310 + env->CP0_DataHi = t0; /* XXX */
1356 } 1311 }
1357 1312
1358 void do_mtc0_status_debug(uint32_t old, uint32_t val) 1313 void do_mtc0_status_debug(uint32_t old, uint32_t val)
@@ -1376,117 +1331,127 @@ void do_mtc0_status_irqraise_debug(void) @@ -1376,117 +1331,127 @@ void do_mtc0_status_irqraise_debug(void)
1376 #endif /* !CONFIG_USER_ONLY */ 1331 #endif /* !CONFIG_USER_ONLY */
1377 1332
1378 /* MIPS MT functions */ 1333 /* MIPS MT functions */
1379 -void do_mftgpr(uint32_t sel) 1334 +target_ulong do_mftgpr(target_ulong t0, uint32_t sel)
1380 { 1335 {
1381 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1336 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1382 1337
1383 - T0 = env->gpr[other_tc][sel]; 1338 + return env->gpr[other_tc][sel];
1384 } 1339 }
1385 1340
1386 -void do_mftlo(uint32_t sel) 1341 +target_ulong do_mftlo(target_ulong t0, uint32_t sel)
1387 { 1342 {
1388 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1343 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1389 1344
1390 - T0 = env->LO[other_tc][sel]; 1345 + return env->LO[other_tc][sel];
1391 } 1346 }
1392 1347
1393 -void do_mfthi(uint32_t sel) 1348 +target_ulong do_mfthi(target_ulong t0, uint32_t sel)
1394 { 1349 {
1395 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1350 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1396 1351
1397 - T0 = env->HI[other_tc][sel]; 1352 + return env->HI[other_tc][sel];
1398 } 1353 }
1399 1354
1400 -void do_mftacx(uint32_t sel) 1355 +target_ulong do_mftacx(target_ulong t0, uint32_t sel)
1401 { 1356 {
1402 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1357 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1403 1358
1404 - T0 = env->ACX[other_tc][sel]; 1359 + return env->ACX[other_tc][sel];
1405 } 1360 }
1406 1361
1407 -void do_mftdsp(void) 1362 +target_ulong do_mftdsp(target_ulong t0)
1408 { 1363 {
1409 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1364 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1410 1365
1411 - T0 = env->DSPControl[other_tc]; 1366 + return env->DSPControl[other_tc];
1412 } 1367 }
1413 1368
1414 -void do_mttgpr(uint32_t sel) 1369 +void do_mttgpr(target_ulong t0, uint32_t sel)
1415 { 1370 {
1416 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1371 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1417 1372
1418 - T0 = env->gpr[other_tc][sel]; 1373 + env->gpr[other_tc][sel] = t0;
1419 } 1374 }
1420 1375
1421 -void do_mttlo(uint32_t sel) 1376 +void do_mttlo(target_ulong t0, uint32_t sel)
1422 { 1377 {
1423 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1378 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1424 1379
1425 - T0 = env->LO[other_tc][sel]; 1380 + env->LO[other_tc][sel] = t0;
1426 } 1381 }
1427 1382
1428 -void do_mtthi(uint32_t sel) 1383 +void do_mtthi(target_ulong t0, uint32_t sel)
1429 { 1384 {
1430 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1385 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1431 1386
1432 - T0 = env->HI[other_tc][sel]; 1387 + env->HI[other_tc][sel] = t0;
1433 } 1388 }
1434 1389
1435 -void do_mttacx(uint32_t sel) 1390 +void do_mttacx(target_ulong t0, uint32_t sel)
1436 { 1391 {
1437 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1392 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1438 1393
1439 - T0 = env->ACX[other_tc][sel]; 1394 + env->ACX[other_tc][sel] = t0;
1440 } 1395 }
1441 1396
1442 -void do_mttdsp(void) 1397 +void do_mttdsp(target_ulong t0)
1443 { 1398 {
1444 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 1399 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1445 1400
1446 - T0 = env->DSPControl[other_tc]; 1401 + env->DSPControl[other_tc] = t0;
1447 } 1402 }
1448 1403
1449 /* MIPS MT functions */ 1404 /* MIPS MT functions */
1450 -void do_dmt(void) 1405 +target_ulong do_dmt(target_ulong t0)
1451 { 1406 {
1452 // TODO 1407 // TODO
1453 - T0 = 0;  
1454 - // rt = T0 1408 + t0 = 0;
  1409 + // rt = t0
  1410 +
  1411 + return t0;
1455 } 1412 }
1456 1413
1457 -void do_emt(void) 1414 +target_ulong do_emt(target_ulong t0)
1458 { 1415 {
1459 // TODO 1416 // TODO
1460 - T0 = 0;  
1461 - // rt = T0 1417 + t0 = 0;
  1418 + // rt = t0
  1419 +
  1420 + return t0;
1462 } 1421 }
1463 1422
1464 -void do_dvpe(void) 1423 +target_ulong do_dvpe(target_ulong t0)
1465 { 1424 {
1466 // TODO 1425 // TODO
1467 - T0 = 0;  
1468 - // rt = T0 1426 + t0 = 0;
  1427 + // rt = t0
  1428 +
  1429 + return t0;
1469 } 1430 }
1470 1431
1471 -void do_evpe(void) 1432 +target_ulong do_evpe(target_ulong t0)
1472 { 1433 {
1473 // TODO 1434 // TODO
1474 - T0 = 0;  
1475 - // rt = T0 1435 + t0 = 0;
  1436 + // rt = t0
  1437 +
  1438 + return t0;
1476 } 1439 }
1477 1440
1478 -void do_fork(void) 1441 +target_ulong do_fork(target_ulong t0, target_ulong t1)
1479 { 1442 {
1480 - // T0 = rt, T1 = rs  
1481 - T0 = 0; 1443 + // t0 = rt, t1 = rs
  1444 + t0 = 0;
1482 // TODO: store to TC register 1445 // TODO: store to TC register
  1446 +
  1447 + return t0;
1483 } 1448 }
1484 1449
1485 -void do_yield(void) 1450 +target_ulong do_yield(target_ulong t0)
1486 { 1451 {
1487 - if (T0 < 0) { 1452 + if (t0 < 0) {
1488 /* No scheduling policy implemented. */ 1453 /* No scheduling policy implemented. */
1489 - if (T0 != -2) { 1454 + if (t0 != -2) {
1490 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && 1455 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1491 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) { 1456 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
1492 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); 1457 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
@@ -1494,20 +1459,20 @@ void do_yield(void) @@ -1494,20 +1459,20 @@ void do_yield(void)
1494 do_raise_exception(EXCP_THREAD); 1459 do_raise_exception(EXCP_THREAD);
1495 } 1460 }
1496 } 1461 }
1497 - } else if (T0 == 0) { 1462 + } else if (t0 == 0) {
1498 if (0 /* TODO: TC underflow */) { 1463 if (0 /* TODO: TC underflow */) {
1499 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); 1464 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1500 do_raise_exception(EXCP_THREAD); 1465 do_raise_exception(EXCP_THREAD);
1501 } else { 1466 } else {
1502 // TODO: Deallocate TC 1467 // TODO: Deallocate TC
1503 } 1468 }
1504 - } else if (T0 > 0) { 1469 + } else if (t0 > 0) {
1505 /* Yield qualifier inputs not implemented. */ 1470 /* Yield qualifier inputs not implemented. */
1506 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); 1471 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1507 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; 1472 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1508 do_raise_exception(EXCP_THREAD); 1473 do_raise_exception(EXCP_THREAD);
1509 } 1474 }
1510 - T0 = env->CP0_YQMask; 1475 + return env->CP0_YQMask;
1511 } 1476 }
1512 1477
1513 /* CP1 functions */ 1478 /* CP1 functions */
@@ -1673,33 +1638,23 @@ void r4k_do_tlbr (void) @@ -1673,33 +1638,23 @@ void r4k_do_tlbr (void)
1673 1638
1674 #endif /* !CONFIG_USER_ONLY */ 1639 #endif /* !CONFIG_USER_ONLY */
1675 1640
1676 -void dump_ldst (const unsigned char *func)  
1677 -{  
1678 - if (loglevel)  
1679 - fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);  
1680 -}  
1681 -  
1682 -void dump_sc (void)  
1683 -{  
1684 - if (loglevel) {  
1685 - fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,  
1686 - T1, T0, env->CP0_LLAddr);  
1687 - }  
1688 -}  
1689 -  
1690 /* Specials */ 1641 /* Specials */
1691 -void do_di (void) 1642 +target_ulong do_di (target_ulong t0)
1692 { 1643 {
1693 - T0 = env->CP0_Status;  
1694 - env->CP0_Status = T0 & ~(1 << CP0St_IE); 1644 + t0 = env->CP0_Status;
  1645 + env->CP0_Status = t0 & ~(1 << CP0St_IE);
1695 cpu_mips_update_irq(env); 1646 cpu_mips_update_irq(env);
  1647 +
  1648 + return t0;
1696 } 1649 }
1697 1650
1698 -void do_ei (void) 1651 +target_ulong do_ei (target_ulong t0)
1699 { 1652 {
1700 - T0 = env->CP0_Status;  
1701 - env->CP0_Status = T0 | (1 << CP0St_IE); 1653 + t0 = env->CP0_Status;
  1654 + env->CP0_Status = t0 | (1 << CP0St_IE);
1702 cpu_mips_update_irq(env); 1655 cpu_mips_update_irq(env);
  1656 +
  1657 + return t0;
1703 } 1658 }
1704 1659
1705 void debug_pre_eret (void) 1660 void debug_pre_eret (void)
@@ -1729,7 +1684,7 @@ void debug_post_eret (void) @@ -1729,7 +1684,7 @@ void debug_post_eret (void)
1729 } 1684 }
1730 } 1685 }
1731 1686
1732 -void do_eret (void) 1687 +void do_eret (target_ulong t0)
1733 { 1688 {
1734 if (loglevel & CPU_LOG_EXEC) 1689 if (loglevel & CPU_LOG_EXEC)
1735 debug_pre_eret(); 1690 debug_pre_eret();
@@ -1746,7 +1701,7 @@ void do_eret (void) @@ -1746,7 +1701,7 @@ void do_eret (void)
1746 env->CP0_LLAddr = 1; 1701 env->CP0_LLAddr = 1;
1747 } 1702 }
1748 1703
1749 -void do_deret (void) 1704 +void do_deret (target_ulong t0)
1750 { 1705 {
1751 if (loglevel & CPU_LOG_EXEC) 1706 if (loglevel & CPU_LOG_EXEC)
1752 debug_pre_eret(); 1707 debug_pre_eret();
@@ -1758,82 +1713,90 @@ void do_deret (void) @@ -1758,82 +1713,90 @@ void do_deret (void)
1758 env->CP0_LLAddr = 1; 1713 env->CP0_LLAddr = 1;
1759 } 1714 }
1760 1715
1761 -void do_rdhwr_cpunum(void) 1716 +target_ulong do_rdhwr_cpunum(target_ulong t0)
1762 { 1717 {
1763 if ((env->hflags & MIPS_HFLAG_CP0) || 1718 if ((env->hflags & MIPS_HFLAG_CP0) ||
1764 (env->CP0_HWREna & (1 << 0))) 1719 (env->CP0_HWREna & (1 << 0)))
1765 - T0 = env->CP0_EBase & 0x3ff; 1720 + t0 = env->CP0_EBase & 0x3ff;
1766 else 1721 else
1767 do_raise_exception(EXCP_RI); 1722 do_raise_exception(EXCP_RI);
  1723 +
  1724 + return t0;
1768 } 1725 }
1769 1726
1770 -void do_rdhwr_synci_step(void) 1727 +target_ulong do_rdhwr_synci_step(target_ulong t0)
1771 { 1728 {
1772 if ((env->hflags & MIPS_HFLAG_CP0) || 1729 if ((env->hflags & MIPS_HFLAG_CP0) ||
1773 (env->CP0_HWREna & (1 << 1))) 1730 (env->CP0_HWREna & (1 << 1)))
1774 - T0 = env->SYNCI_Step; 1731 + t0 = env->SYNCI_Step;
1775 else 1732 else
1776 do_raise_exception(EXCP_RI); 1733 do_raise_exception(EXCP_RI);
  1734 +
  1735 + return t0;
1777 } 1736 }
1778 1737
1779 -void do_rdhwr_cc(void) 1738 +target_ulong do_rdhwr_cc(target_ulong t0)
1780 { 1739 {
1781 if ((env->hflags & MIPS_HFLAG_CP0) || 1740 if ((env->hflags & MIPS_HFLAG_CP0) ||
1782 (env->CP0_HWREna & (1 << 2))) 1741 (env->CP0_HWREna & (1 << 2)))
1783 - T0 = env->CP0_Count; 1742 + t0 = env->CP0_Count;
1784 else 1743 else
1785 do_raise_exception(EXCP_RI); 1744 do_raise_exception(EXCP_RI);
  1745 +
  1746 + return t0;
1786 } 1747 }
1787 1748
1788 -void do_rdhwr_ccres(void) 1749 +target_ulong do_rdhwr_ccres(target_ulong t0)
1789 { 1750 {
1790 if ((env->hflags & MIPS_HFLAG_CP0) || 1751 if ((env->hflags & MIPS_HFLAG_CP0) ||
1791 (env->CP0_HWREna & (1 << 3))) 1752 (env->CP0_HWREna & (1 << 3)))
1792 - T0 = env->CCRes; 1753 + t0 = env->CCRes;
1793 else 1754 else
1794 do_raise_exception(EXCP_RI); 1755 do_raise_exception(EXCP_RI);
  1756 +
  1757 + return t0;
1795 } 1758 }
1796 1759
1797 /* Bitfield operations. */ 1760 /* Bitfield operations. */
1798 -void do_ext(uint32_t pos, uint32_t size) 1761 +target_ulong do_ext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1799 { 1762 {
1800 - T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0)); 1763 + return (int32_t)((t1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
1801 } 1764 }
1802 1765
1803 -void do_ins(uint32_t pos, uint32_t size) 1766 +target_ulong do_ins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1804 { 1767 {
1805 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; 1768 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
1806 1769
1807 - T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask)); 1770 + return (int32_t)((t0 & ~mask) | ((t1 << pos) & mask));
1808 } 1771 }
1809 1772
1810 -void do_wsbh(void) 1773 +target_ulong do_wsbh(target_ulong t0, target_ulong t1)
1811 { 1774 {
1812 - T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF)); 1775 + return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF));
1813 } 1776 }
1814 1777
1815 #if defined(TARGET_MIPS64) 1778 #if defined(TARGET_MIPS64)
1816 -void do_dext(uint32_t pos, uint32_t size) 1779 +target_ulong do_dext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1817 { 1780 {
1818 - T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL); 1781 + return (t1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
1819 } 1782 }
1820 1783
1821 -void do_dins(uint32_t pos, uint32_t size) 1784 +target_ulong do_dins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
1822 { 1785 {
1823 target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos; 1786 target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
1824 1787
1825 - T0 = (T0 & ~mask) | ((T1 << pos) & mask); 1788 + return (t0 & ~mask) | ((t1 << pos) & mask);
1826 } 1789 }
1827 1790
1828 -void do_dsbh(void) 1791 +target_ulong do_dsbh(target_ulong t0, target_ulong t1)
1829 { 1792 {
1830 - T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); 1793 + return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL);
1831 } 1794 }
1832 1795
1833 -void do_dshd(void) 1796 +target_ulong do_dshd(target_ulong t0, target_ulong t1)
1834 { 1797 {
1835 - T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);  
1836 - T0 = (T1 << 32) | (T1 >> 32); 1798 + t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL);
  1799 + return (t1 << 32) | (t1 >> 32);
1837 } 1800 }
1838 #endif 1801 #endif
1839 1802
@@ -1955,51 +1918,53 @@ unsigned int ieee_rm[] = { @@ -1955,51 +1918,53 @@ unsigned int ieee_rm[] = {
1955 #define RESTORE_ROUNDING_MODE \ 1918 #define RESTORE_ROUNDING_MODE \
1956 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status) 1919 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
1957 1920
1958 -void do_cfc1 (uint32_t reg) 1921 +target_ulong do_cfc1 (target_ulong t0, uint32_t reg)
1959 { 1922 {
1960 switch (reg) { 1923 switch (reg) {
1961 case 0: 1924 case 0:
1962 - T0 = (int32_t)env->fpu->fcr0; 1925 + t0 = (int32_t)env->fpu->fcr0;
1963 break; 1926 break;
1964 case 25: 1927 case 25:
1965 - T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); 1928 + t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
1966 break; 1929 break;
1967 case 26: 1930 case 26:
1968 - T0 = env->fpu->fcr31 & 0x0003f07c; 1931 + t0 = env->fpu->fcr31 & 0x0003f07c;
1969 break; 1932 break;
1970 case 28: 1933 case 28:
1971 - T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); 1934 + t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
1972 break; 1935 break;
1973 default: 1936 default:
1974 - T0 = (int32_t)env->fpu->fcr31; 1937 + t0 = (int32_t)env->fpu->fcr31;
1975 break; 1938 break;
1976 } 1939 }
  1940 +
  1941 + return t0;
1977 } 1942 }
1978 1943
1979 -void do_ctc1 (uint32_t reg) 1944 +void do_ctc1 (target_ulong t0, uint32_t reg)
1980 { 1945 {
1981 switch(reg) { 1946 switch(reg) {
1982 case 25: 1947 case 25:
1983 - if (T0 & 0xffffff00) 1948 + if (t0 & 0xffffff00)
1984 return; 1949 return;
1985 - env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |  
1986 - ((T0 & 0x1) << 23); 1950 + env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
  1951 + ((t0 & 0x1) << 23);
1987 break; 1952 break;
1988 case 26: 1953 case 26:
1989 - if (T0 & 0x007c0000) 1954 + if (t0 & 0x007c0000)
1990 return; 1955 return;
1991 - env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); 1956 + env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
1992 break; 1957 break;
1993 case 28: 1958 case 28:
1994 - if (T0 & 0x007c0000) 1959 + if (t0 & 0x007c0000)
1995 return; 1960 return;
1996 - env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |  
1997 - ((T0 & 0x4) << 22); 1961 + env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
  1962 + ((t0 & 0x4) << 22);
1998 break; 1963 break;
1999 case 31: 1964 case 31:
2000 - if (T0 & 0x007c0000) 1965 + if (t0 & 0x007c0000)
2001 return; 1966 return;
2002 - env->fpu->fcr31 = T0; 1967 + env->fpu->fcr31 = t0;
2003 break; 1968 break;
2004 default: 1969 default:
2005 return; 1970 return;
target-mips/translate.c
  View file @be24bb4
@@ -428,22 +428,74 @@ static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[2]; @@ -428,22 +428,74 @@ static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[2];
428 /* FPU TNs, global for now. */ 428 /* FPU TNs, global for now. */
429 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3]; 429 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
430 430
431 -static inline void tcg_gen_helper_0_1i(void *func, TCGv arg) 431 +static inline void tcg_gen_helper_0_i(void *func, TCGv arg)
432 { 432 {
433 - TCGv t = tcg_const_i32(arg); 433 + TCGv tmp = tcg_const_i32(arg);
434 434
435 - tcg_gen_helper_0_1(func, t);  
436 - tcg_temp_free(t); 435 + tcg_gen_helper_0_1(func, tmp);
  436 + tcg_temp_free(tmp);
437 } 437 }
438 438
439 -static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2) 439 +static inline void tcg_gen_helper_0_ii(void *func, TCGv arg1, TCGv arg2)
440 { 440 {
441 - TCGv t1 = tcg_const_i32(arg1);  
442 - TCGv t2 = tcg_const_i32(arg2); 441 + TCGv tmp1 = tcg_const_i32(arg1);
  442 + TCGv tmp2 = tcg_const_i32(arg2);
443 443
444 - tcg_gen_helper_0_2(func, t1, t2);  
445 - tcg_temp_free(t1);  
446 - tcg_temp_free(t2); 444 + tcg_gen_helper_0_2(func, tmp1, tmp2);
  445 + tcg_temp_free(tmp1);
  446 + tcg_temp_free(tmp2);
  447 +}
  448 +
  449 +static inline void tcg_gen_helper_0_1i(void *func, TCGv arg1, TCGv arg2)
  450 +{
  451 + TCGv tmp = tcg_const_i32(arg2);
  452 +
  453 + tcg_gen_helper_0_2(func, arg1, tmp);
  454 + tcg_temp_free(tmp);
  455 +}
  456 +
  457 +static inline void tcg_gen_helper_0_2i(void *func, TCGv arg1, TCGv arg2, TCGv arg3)
  458 +{
  459 + TCGv tmp = tcg_const_i32(arg3);
  460 +
  461 + tcg_gen_helper_0_3(func, arg1, arg2, tmp);
  462 + tcg_temp_free(tmp);
  463 +}
  464 +
  465 +static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4)
  466 +{
  467 + TCGv tmp1 = tcg_const_i32(arg3);
  468 + TCGv tmp2 = tcg_const_i32(arg3);
  469 +
  470 + tcg_gen_helper_0_4(func, arg1, arg2, tmp1, tmp2);
  471 + tcg_temp_free(tmp1);
  472 + tcg_temp_free(tmp2);
  473 +}
  474 +
  475 +static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, TCGv arg2)
  476 +{
  477 + TCGv tmp = tcg_const_i32(arg2);
  478 +
  479 + tcg_gen_helper_1_2(func, ret, arg1, tmp);
  480 + tcg_temp_free(tmp);
  481 +}
  482 +
  483 +static inline void tcg_gen_helper_1_2i(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
  484 +{
  485 + TCGv tmp = tcg_const_i32(arg3);
  486 +
  487 + tcg_gen_helper_1_3(func, ret, arg1, arg2, tmp);
  488 + tcg_temp_free(tmp);
  489 +}
  490 +
  491 +static inline void tcg_gen_helper_1_2ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4)
  492 +{
  493 + TCGv tmp1 = tcg_const_i32(arg3);
  494 + TCGv tmp2 = tcg_const_i32(arg3);
  495 +
  496 + tcg_gen_helper_1_4(func, ret, arg1, arg2, tmp1, tmp2);
  497 + tcg_temp_free(tmp1);
  498 + tcg_temp_free(tmp2);
447 } 499 }
448 500
449 typedef struct DisasContext { 501 typedef struct DisasContext {
@@ -540,37 +592,44 @@ static inline void gen_store_HI (TCGv t, int reg) @@ -540,37 +592,44 @@ static inline void gen_store_HI (TCGv t, int reg)
540 } 592 }
541 593
542 /* Moves to/from shadow registers. */ 594 /* Moves to/from shadow registers. */
543 -static inline void gen_load_srsgpr (TCGv t, int reg) 595 +static inline void gen_load_srsgpr (int from, int to)
544 { 596 {
545 - if (reg == 0)  
546 - tcg_gen_movi_tl(t, 0); 597 + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  598 +
  599 + if (from == 0)
  600 + tcg_gen_movi_tl(r_tmp1, 0);
547 else { 601 else {
548 - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); 602 + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
549 603
550 - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));  
551 - tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);  
552 - tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);  
553 - tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);  
554 - tcg_gen_add_i32(r_tmp, cpu_env, r_tmp); 604 + tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
  605 + tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
  606 + tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
  607 + tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
  608 + tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
555 609
556 - tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg);  
557 - tcg_temp_free(r_tmp); 610 + tcg_gen_ld_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * from);
  611 + tcg_temp_free(r_tmp2);
558 } 612 }
  613 + gen_store_gpr(r_tmp1, to);
  614 + tcg_temp_free(r_tmp1);
559 } 615 }
560 616
561 -static inline void gen_store_srsgpr (TCGv t, int reg) 617 +static inline void gen_store_srsgpr (int from, int to)
562 { 618 {
563 - if (reg != 0) {  
564 - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);  
565 -  
566 - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));  
567 - tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);  
568 - tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);  
569 - tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);  
570 - tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);  
571 -  
572 - tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg);  
573 - tcg_temp_free(r_tmp); 619 + if (to != 0) {
  620 + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  621 + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
  622 +
  623 + gen_load_gpr(r_tmp1, from);
  624 + tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
  625 + tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
  626 + tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
  627 + tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
  628 + tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
  629 +
  630 + tcg_gen_st_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * to);
  631 + tcg_temp_free(r_tmp1);
  632 + tcg_temp_free(r_tmp2);
574 } 633 }
575 } 634 }
576 635
@@ -666,7 +725,7 @@ static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = { \ @@ -666,7 +725,7 @@ static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = { \
666 }; \ 725 }; \
667 static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ 726 static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
668 { \ 727 { \
669 - tcg_gen_helper_0_1i(fcmp ## type ## _ ## fmt ## _table[n], cc); \ 728 + tcg_gen_helper_0_i(fcmp ## type ## _ ## fmt ## _table[n], cc); \
670 } 729 }
671 730
672 FOP_CONDS(, d) 731 FOP_CONDS(, d)
@@ -679,16 +738,16 @@ FOP_CONDS(abs, ps) @@ -679,16 +738,16 @@ FOP_CONDS(abs, ps)
679 738
680 /* Tests */ 739 /* Tests */
681 #define OP_COND(name, cond) \ 740 #define OP_COND(name, cond) \
682 -void glue(gen_op_, name) (void) \ 741 +void glue(gen_op_, name) (TCGv t0, TCGv t1) \
683 { \ 742 { \
684 int l1 = gen_new_label(); \ 743 int l1 = gen_new_label(); \
685 int l2 = gen_new_label(); \ 744 int l2 = gen_new_label(); \
686 \ 745 \
687 - tcg_gen_brcond_tl(cond, cpu_T[0], cpu_T[1], l1); \  
688 - tcg_gen_movi_tl(cpu_T[0], 0); \ 746 + tcg_gen_brcond_tl(cond, t0, t1, l1); \
  747 + tcg_gen_movi_tl(t0, 0); \
689 tcg_gen_br(l2); \ 748 tcg_gen_br(l2); \
690 gen_set_label(l1); \ 749 gen_set_label(l1); \
691 - tcg_gen_movi_tl(cpu_T[0], 1); \ 750 + tcg_gen_movi_tl(t0, 1); \
692 gen_set_label(l2); \ 751 gen_set_label(l2); \
693 } 752 }
694 OP_COND(eq, TCG_COND_EQ); 753 OP_COND(eq, TCG_COND_EQ);
@@ -700,16 +759,16 @@ OP_COND(ltu, TCG_COND_LTU); @@ -700,16 +759,16 @@ OP_COND(ltu, TCG_COND_LTU);
700 #undef OP_COND 759 #undef OP_COND
701 760
702 #define OP_CONDI(name, cond) \ 761 #define OP_CONDI(name, cond) \
703 -void glue(gen_op_, name) (target_ulong val) \ 762 +void glue(gen_op_, name) (TCGv t, target_ulong val) \
704 { \ 763 { \
705 int l1 = gen_new_label(); \ 764 int l1 = gen_new_label(); \
706 int l2 = gen_new_label(); \ 765 int l2 = gen_new_label(); \
707 \ 766 \
708 - tcg_gen_brcondi_tl(cond, cpu_T[0], val, l1); \  
709 - tcg_gen_movi_tl(cpu_T[0], 0); \ 767 + tcg_gen_brcondi_tl(cond, t, val, l1); \
  768 + tcg_gen_movi_tl(t, 0); \
710 tcg_gen_br(l2); \ 769 tcg_gen_br(l2); \
711 gen_set_label(l1); \ 770 gen_set_label(l1); \
712 - tcg_gen_movi_tl(cpu_T[0], 1); \ 771 + tcg_gen_movi_tl(t, 1); \
713 gen_set_label(l2); \ 772 gen_set_label(l2); \
714 } 773 }
715 OP_CONDI(lti, TCG_COND_LT); 774 OP_CONDI(lti, TCG_COND_LT);
@@ -717,16 +776,16 @@ OP_CONDI(ltiu, TCG_COND_LTU); @@ -717,16 +776,16 @@ OP_CONDI(ltiu, TCG_COND_LTU);
717 #undef OP_CONDI 776 #undef OP_CONDI
718 777
719 #define OP_CONDZ(name, cond) \ 778 #define OP_CONDZ(name, cond) \
720 -void glue(gen_op_, name) (void) \ 779 +void glue(gen_op_, name) (TCGv t) \
721 { \ 780 { \
722 int l1 = gen_new_label(); \ 781 int l1 = gen_new_label(); \
723 int l2 = gen_new_label(); \ 782 int l2 = gen_new_label(); \
724 \ 783 \
725 - tcg_gen_brcondi_tl(cond, cpu_T[0], 0, l1); \  
726 - tcg_gen_movi_tl(cpu_T[0], 0); \ 784 + tcg_gen_brcondi_tl(cond, t, 0, l1); \
  785 + tcg_gen_movi_tl(t, 0); \
727 tcg_gen_br(l2); \ 786 tcg_gen_br(l2); \
728 gen_set_label(l1); \ 787 gen_set_label(l1); \
729 - tcg_gen_movi_tl(cpu_T[0], 1); \ 788 + tcg_gen_movi_tl(t, 1); \
730 gen_set_label(l2); \ 789 gen_set_label(l2); \
731 } 790 }
732 OP_CONDZ(gez, TCG_COND_GE); 791 OP_CONDZ(gez, TCG_COND_GE);
@@ -840,7 +899,7 @@ static always_inline void @@ -840,7 +899,7 @@ static always_inline void
840 generate_exception_err (DisasContext *ctx, int excp, int err) 899 generate_exception_err (DisasContext *ctx, int excp, int err)
841 { 900 {
842 save_cpu_state(ctx, 1); 901 save_cpu_state(ctx, 1);
843 - tcg_gen_helper_0_2ii(do_raise_exception_err, excp, err); 902 + tcg_gen_helper_0_ii(do_raise_exception_err, excp, err);
844 tcg_gen_helper_0_0(do_interrupt_restart); 903 tcg_gen_helper_0_0(do_interrupt_restart);
845 tcg_gen_exit_tb(0); 904 tcg_gen_exit_tb(0);
846 } 905 }
@@ -849,15 +908,15 @@ static always_inline void @@ -849,15 +908,15 @@ static always_inline void
849 generate_exception (DisasContext *ctx, int excp) 908 generate_exception (DisasContext *ctx, int excp)
850 { 909 {
851 save_cpu_state(ctx, 1); 910 save_cpu_state(ctx, 1);
852 - tcg_gen_helper_0_1i(do_raise_exception, excp); 911 + tcg_gen_helper_0_i(do_raise_exception, excp);
853 tcg_gen_helper_0_0(do_interrupt_restart); 912 tcg_gen_helper_0_0(do_interrupt_restart);
854 tcg_gen_exit_tb(0); 913 tcg_gen_exit_tb(0);
855 } 914 }
856 915
857 /* Addresses computation */ 916 /* Addresses computation */
858 -static inline void gen_op_addr_add (void) 917 +static inline void gen_op_addr_add (TCGv t0, TCGv t1)
859 { 918 {
860 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 919 + tcg_gen_add_tl(t0, t0, t1);
861 920
862 #if defined(TARGET_MIPS64) 921 #if defined(TARGET_MIPS64)
863 /* For compatibility with 32-bit code, data reference in user mode 922 /* For compatibility with 32-bit code, data reference in user mode
@@ -874,7 +933,7 @@ static inline void gen_op_addr_add (void) @@ -874,7 +933,7 @@ static inline void gen_op_addr_add (void)
874 tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX)); 933 tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
875 tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1); 934 tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
876 tcg_temp_free(r_tmp); 935 tcg_temp_free(r_tmp);
877 - tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]); 936 + tcg_gen_ext32s_i64(t0, t0);
878 gen_set_label(l1); 937 gen_set_label(l1);
879 } 938 }
880 #endif 939 #endif
@@ -946,9 +1005,9 @@ static always_inline void check_mips_64(DisasContext *ctx) @@ -946,9 +1005,9 @@ static always_inline void check_mips_64(DisasContext *ctx)
946 1005
947 /* load/store instructions. */ 1006 /* load/store instructions. */
948 #define OP_LD(insn,fname) \ 1007 #define OP_LD(insn,fname) \
949 -void inline op_ldst_##insn(DisasContext *ctx) \ 1008 +void inline op_ldst_##insn(TCGv t0, DisasContext *ctx) \
950 { \ 1009 { \
951 - tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \ 1010 + tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
952 } 1011 }
953 OP_LD(lb,ld8s); 1012 OP_LD(lb,ld8s);
954 OP_LD(lbu,ld8u); 1013 OP_LD(lbu,ld8u);
@@ -962,9 +1021,9 @@ OP_LD(ld,ld64); @@ -962,9 +1021,9 @@ OP_LD(ld,ld64);
962 #undef OP_LD 1021 #undef OP_LD
963 1022
964 #define OP_ST(insn,fname) \ 1023 #define OP_ST(insn,fname) \
965 -void inline op_ldst_##insn(DisasContext *ctx) \ 1024 +void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
966 { \ 1025 { \
967 - tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \ 1026 + tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
968 } 1027 }
969 OP_ST(sb,st8); 1028 OP_ST(sb,st8);
970 OP_ST(sh,st16); 1029 OP_ST(sh,st16);
@@ -975,11 +1034,11 @@ OP_ST(sd,st64); @@ -975,11 +1034,11 @@ OP_ST(sd,st64);
975 #undef OP_ST 1034 #undef OP_ST
976 1035
977 #define OP_LD_ATOMIC(insn,fname) \ 1036 #define OP_LD_ATOMIC(insn,fname) \
978 -void inline op_ldst_##insn(DisasContext *ctx) \ 1037 +void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
979 { \ 1038 { \
980 - tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); \  
981 - tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \  
982 - tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUState, CP0_LLAddr)); \ 1039 + tcg_gen_mov_tl(t1, t0); \
  1040 + tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
  1041 + tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
983 } 1042 }
984 OP_LD_ATOMIC(ll,ld32s); 1043 OP_LD_ATOMIC(ll,ld32s);
985 #if defined(TARGET_MIPS64) 1044 #if defined(TARGET_MIPS64)
@@ -988,26 +1047,26 @@ OP_LD_ATOMIC(lld,ld64); @@ -988,26 +1047,26 @@ OP_LD_ATOMIC(lld,ld64);
988 #undef OP_LD_ATOMIC 1047 #undef OP_LD_ATOMIC
989 1048
990 #define OP_ST_ATOMIC(insn,fname,almask) \ 1049 #define OP_ST_ATOMIC(insn,fname,almask) \
991 -void inline op_ldst_##insn(DisasContext *ctx) \ 1050 +void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
992 { \ 1051 { \
993 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \ 1052 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
994 int l1 = gen_new_label(); \ 1053 int l1 = gen_new_label(); \
995 int l2 = gen_new_label(); \ 1054 int l2 = gen_new_label(); \
996 int l3 = gen_new_label(); \ 1055 int l3 = gen_new_label(); \
997 \ 1056 \
998 - tcg_gen_andi_tl(r_tmp, cpu_T[0], almask); \ 1057 + tcg_gen_andi_tl(r_tmp, t0, almask); \
999 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \ 1058 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
1000 - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ 1059 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
1001 generate_exception(ctx, EXCP_AdES); \ 1060 generate_exception(ctx, EXCP_AdES); \
1002 gen_set_label(l1); \ 1061 gen_set_label(l1); \
1003 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ 1062 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1004 - tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \ 1063 + tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
1005 tcg_temp_free(r_tmp); \ 1064 tcg_temp_free(r_tmp); \
1006 - tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \  
1007 - tcg_gen_movi_tl(cpu_T[0], 1); \ 1065 + tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
  1066 + tcg_gen_movi_tl(t0, 1); \
1008 tcg_gen_br(l3); \ 1067 tcg_gen_br(l3); \
1009 gen_set_label(l2); \ 1068 gen_set_label(l2); \
1010 - tcg_gen_movi_tl(cpu_T[0], 0); \ 1069 + tcg_gen_movi_tl(t0, 0); \
1011 gen_set_label(l3); \ 1070 gen_set_label(l3); \
1012 } 1071 }
1013 OP_ST_ATOMIC(sc,st32,0x3); 1072 OP_ST_ATOMIC(sc,st32,0x3);
@@ -1029,141 +1088,141 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, @@ -1029,141 +1088,141 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1029 } else { 1088 } else {
1030 gen_load_gpr(cpu_T[0], base); 1089 gen_load_gpr(cpu_T[0], base);
1031 tcg_gen_movi_tl(cpu_T[1], offset); 1090 tcg_gen_movi_tl(cpu_T[1], offset);
1032 - gen_op_addr_add(); 1091 + gen_op_addr_add(cpu_T[0], cpu_T[1]);
1033 } 1092 }
1034 /* Don't do NOP if destination is zero: we must perform the actual 1093 /* Don't do NOP if destination is zero: we must perform the actual
1035 memory access. */ 1094 memory access. */
1036 switch (opc) { 1095 switch (opc) {
1037 #if defined(TARGET_MIPS64) 1096 #if defined(TARGET_MIPS64)
1038 case OPC_LWU: 1097 case OPC_LWU:
1039 - op_ldst_lwu(ctx); 1098 + op_ldst_lwu(cpu_T[0], ctx);
1040 gen_store_gpr(cpu_T[0], rt); 1099 gen_store_gpr(cpu_T[0], rt);
1041 opn = "lwu"; 1100 opn = "lwu";
1042 break; 1101 break;
1043 case OPC_LD: 1102 case OPC_LD:
1044 - op_ldst_ld(ctx); 1103 + op_ldst_ld(cpu_T[0], ctx);
1045 gen_store_gpr(cpu_T[0], rt); 1104 gen_store_gpr(cpu_T[0], rt);
1046 opn = "ld"; 1105 opn = "ld";
1047 break; 1106 break;
1048 case OPC_LLD: 1107 case OPC_LLD:
1049 - op_ldst_lld(ctx); 1108 + op_ldst_lld(cpu_T[0], cpu_T[1], ctx);
1050 gen_store_gpr(cpu_T[0], rt); 1109 gen_store_gpr(cpu_T[0], rt);
1051 opn = "lld"; 1110 opn = "lld";
1052 break; 1111 break;
1053 case OPC_SD: 1112 case OPC_SD:
1054 gen_load_gpr(cpu_T[1], rt); 1113 gen_load_gpr(cpu_T[1], rt);
1055 - op_ldst_sd(ctx); 1114 + op_ldst_sd(cpu_T[0], cpu_T[1], ctx);
1056 opn = "sd"; 1115 opn = "sd";
1057 break; 1116 break;
1058 case OPC_SCD: 1117 case OPC_SCD:
1059 save_cpu_state(ctx, 1); 1118 save_cpu_state(ctx, 1);
1060 gen_load_gpr(cpu_T[1], rt); 1119 gen_load_gpr(cpu_T[1], rt);
1061 - op_ldst_scd(ctx); 1120 + op_ldst_scd(cpu_T[0], cpu_T[1], ctx);
1062 gen_store_gpr(cpu_T[0], rt); 1121 gen_store_gpr(cpu_T[0], rt);
1063 opn = "scd"; 1122 opn = "scd";
1064 break; 1123 break;
1065 case OPC_LDL: 1124 case OPC_LDL:
1066 save_cpu_state(ctx, 1); 1125 save_cpu_state(ctx, 1);
1067 gen_load_gpr(cpu_T[1], rt); 1126 gen_load_gpr(cpu_T[1], rt);
1068 - tcg_gen_helper_0_1i(do_ldl, ctx->mem_idx); 1127 + tcg_gen_helper_1_2i(do_ldl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
1069 gen_store_gpr(cpu_T[1], rt); 1128 gen_store_gpr(cpu_T[1], rt);
1070 opn = "ldl"; 1129 opn = "ldl";
1071 break; 1130 break;
1072 case OPC_SDL: 1131 case OPC_SDL:
1073 save_cpu_state(ctx, 1); 1132 save_cpu_state(ctx, 1);
1074 gen_load_gpr(cpu_T[1], rt); 1133 gen_load_gpr(cpu_T[1], rt);
1075 - tcg_gen_helper_0_1i(do_sdl, ctx->mem_idx); 1134 + tcg_gen_helper_0_2i(do_sdl, cpu_T[0], cpu_T[1], ctx->mem_idx);
1076 opn = "sdl"; 1135 opn = "sdl";
1077 break; 1136 break;
1078 case OPC_LDR: 1137 case OPC_LDR:
1079 save_cpu_state(ctx, 1); 1138 save_cpu_state(ctx, 1);
1080 gen_load_gpr(cpu_T[1], rt); 1139 gen_load_gpr(cpu_T[1], rt);
1081 - tcg_gen_helper_0_1i(do_ldr, ctx->mem_idx); 1140 + tcg_gen_helper_1_2i(do_ldr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
1082 gen_store_gpr(cpu_T[1], rt); 1141 gen_store_gpr(cpu_T[1], rt);
1083 opn = "ldr"; 1142 opn = "ldr";
1084 break; 1143 break;
1085 case OPC_SDR: 1144 case OPC_SDR:
1086 save_cpu_state(ctx, 1); 1145 save_cpu_state(ctx, 1);
1087 gen_load_gpr(cpu_T[1], rt); 1146 gen_load_gpr(cpu_T[1], rt);
1088 - tcg_gen_helper_0_1i(do_sdr, ctx->mem_idx); 1147 + tcg_gen_helper_0_2i(do_sdr, cpu_T[0], cpu_T[1], ctx->mem_idx);
1089 opn = "sdr"; 1148 opn = "sdr";
1090 break; 1149 break;
1091 #endif 1150 #endif
1092 case OPC_LW: 1151 case OPC_LW:
1093 - op_ldst_lw(ctx); 1152 + op_ldst_lw(cpu_T[0], ctx);
1094 gen_store_gpr(cpu_T[0], rt); 1153 gen_store_gpr(cpu_T[0], rt);
1095 opn = "lw"; 1154 opn = "lw";
1096 break; 1155 break;
1097 case OPC_SW: 1156 case OPC_SW:
1098 gen_load_gpr(cpu_T[1], rt); 1157 gen_load_gpr(cpu_T[1], rt);
1099 - op_ldst_sw(ctx); 1158 + op_ldst_sw(cpu_T[0], cpu_T[1], ctx);
1100 opn = "sw"; 1159 opn = "sw";
1101 break; 1160 break;
1102 case OPC_LH: 1161 case OPC_LH:
1103 - op_ldst_lh(ctx); 1162 + op_ldst_lh(cpu_T[0], ctx);
1104 gen_store_gpr(cpu_T[0], rt); 1163 gen_store_gpr(cpu_T[0], rt);
1105 opn = "lh"; 1164 opn = "lh";
1106 break; 1165 break;
1107 case OPC_SH: 1166 case OPC_SH:
1108 gen_load_gpr(cpu_T[1], rt); 1167 gen_load_gpr(cpu_T[1], rt);
1109 - op_ldst_sh(ctx); 1168 + op_ldst_sh(cpu_T[0], cpu_T[1], ctx);
1110 opn = "sh"; 1169 opn = "sh";
1111 break; 1170 break;
1112 case OPC_LHU: 1171 case OPC_LHU:
1113 - op_ldst_lhu(ctx); 1172 + op_ldst_lhu(cpu_T[0], ctx);
1114 gen_store_gpr(cpu_T[0], rt); 1173 gen_store_gpr(cpu_T[0], rt);
1115 opn = "lhu"; 1174 opn = "lhu";
1116 break; 1175 break;
1117 case OPC_LB: 1176 case OPC_LB:
1118 - op_ldst_lb(ctx); 1177 + op_ldst_lb(cpu_T[0], ctx);
1119 gen_store_gpr(cpu_T[0], rt); 1178 gen_store_gpr(cpu_T[0], rt);
1120 opn = "lb"; 1179 opn = "lb";
1121 break; 1180 break;
1122 case OPC_SB: 1181 case OPC_SB:
1123 gen_load_gpr(cpu_T[1], rt); 1182 gen_load_gpr(cpu_T[1], rt);
1124 - op_ldst_sb(ctx); 1183 + op_ldst_sb(cpu_T[0], cpu_T[1], ctx);
1125 opn = "sb"; 1184 opn = "sb";
1126 break; 1185 break;
1127 case OPC_LBU: 1186 case OPC_LBU:
1128 - op_ldst_lbu(ctx); 1187 + op_ldst_lbu(cpu_T[0], ctx);
1129 gen_store_gpr(cpu_T[0], rt); 1188 gen_store_gpr(cpu_T[0], rt);
1130 opn = "lbu"; 1189 opn = "lbu";
1131 break; 1190 break;
1132 case OPC_LWL: 1191 case OPC_LWL:
1133 save_cpu_state(ctx, 1); 1192 save_cpu_state(ctx, 1);
1134 gen_load_gpr(cpu_T[1], rt); 1193 gen_load_gpr(cpu_T[1], rt);
1135 - tcg_gen_helper_0_1i(do_lwl, ctx->mem_idx); 1194 + tcg_gen_helper_1_2i(do_lwl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
1136 gen_store_gpr(cpu_T[1], rt); 1195 gen_store_gpr(cpu_T[1], rt);
1137 opn = "lwl"; 1196 opn = "lwl";
1138 break; 1197 break;
1139 case OPC_SWL: 1198 case OPC_SWL:
1140 save_cpu_state(ctx, 1); 1199 save_cpu_state(ctx, 1);
1141 gen_load_gpr(cpu_T[1], rt); 1200 gen_load_gpr(cpu_T[1], rt);
1142 - tcg_gen_helper_0_1i(do_swl, ctx->mem_idx); 1201 + tcg_gen_helper_0_2i(do_swl, cpu_T[0], cpu_T[1], ctx->mem_idx);
1143 opn = "swr"; 1202 opn = "swr";
1144 break; 1203 break;
1145 case OPC_LWR: 1204 case OPC_LWR:
1146 save_cpu_state(ctx, 1); 1205 save_cpu_state(ctx, 1);
1147 gen_load_gpr(cpu_T[1], rt); 1206 gen_load_gpr(cpu_T[1], rt);
1148 - tcg_gen_helper_0_1i(do_lwr, ctx->mem_idx); 1207 + tcg_gen_helper_1_2i(do_lwr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
1149 gen_store_gpr(cpu_T[1], rt); 1208 gen_store_gpr(cpu_T[1], rt);
1150 opn = "lwr"; 1209 opn = "lwr";
1151 break; 1210 break;
1152 case OPC_SWR: 1211 case OPC_SWR:
1153 save_cpu_state(ctx, 1); 1212 save_cpu_state(ctx, 1);
1154 gen_load_gpr(cpu_T[1], rt); 1213 gen_load_gpr(cpu_T[1], rt);
1155 - tcg_gen_helper_0_1i(do_swr, ctx->mem_idx); 1214 + tcg_gen_helper_0_2i(do_swr, cpu_T[0], cpu_T[1], ctx->mem_idx);
1156 opn = "swr"; 1215 opn = "swr";
1157 break; 1216 break;
1158 case OPC_LL: 1217 case OPC_LL:
1159 - op_ldst_ll(ctx); 1218 + op_ldst_ll(cpu_T[0], cpu_T[1], ctx);
1160 gen_store_gpr(cpu_T[0], rt); 1219 gen_store_gpr(cpu_T[0], rt);
1161 opn = "ll"; 1220 opn = "ll";
1162 break; 1221 break;
1163 case OPC_SC: 1222 case OPC_SC:
1164 save_cpu_state(ctx, 1); 1223 save_cpu_state(ctx, 1);
1165 gen_load_gpr(cpu_T[1], rt); 1224 gen_load_gpr(cpu_T[1], rt);
1166 - op_ldst_sc(ctx); 1225 + op_ldst_sc(cpu_T[0], cpu_T[1], ctx);
1167 gen_store_gpr(cpu_T[0], rt); 1226 gen_store_gpr(cpu_T[0], rt);
1168 opn = "sc"; 1227 opn = "sc";
1169 break; 1228 break;
@@ -1188,7 +1247,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, @@ -1188,7 +1247,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1188 } else { 1247 } else {
1189 gen_load_gpr(cpu_T[0], base); 1248 gen_load_gpr(cpu_T[0], base);
1190 tcg_gen_movi_tl(cpu_T[1], offset); 1249 tcg_gen_movi_tl(cpu_T[1], offset);
1191 - gen_op_addr_add(); 1250 + gen_op_addr_add(cpu_T[0], cpu_T[1]);
1192 } 1251 }
1193 /* Don't do NOP if destination is zero: we must perform the actual 1252 /* Don't do NOP if destination is zero: we must perform the actual
1194 memory access. */ 1253 memory access. */
@@ -1245,7 +1304,6 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1245,7 +1304,6 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1245 case OPC_SLTI: 1304 case OPC_SLTI:
1246 case OPC_SLTIU: 1305 case OPC_SLTIU:
1247 uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 1306 uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1248 - tcg_gen_movi_tl(cpu_T[1], uimm);  
1249 /* Fall through. */ 1307 /* Fall through. */
1250 case OPC_ANDI: 1308 case OPC_ANDI:
1251 case OPC_ORI: 1309 case OPC_ORI:
@@ -1334,11 +1392,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1334,11 +1392,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1334 break; 1392 break;
1335 #endif 1393 #endif
1336 case OPC_SLTI: 1394 case OPC_SLTI:
1337 - gen_op_lti(uimm); 1395 + gen_op_lti(cpu_T[0], uimm);
1338 opn = "slti"; 1396 opn = "slti";
1339 break; 1397 break;
1340 case OPC_SLTIU: 1398 case OPC_SLTIU:
1341 - gen_op_ltiu(uimm); 1399 + gen_op_ltiu(cpu_T[0], uimm);
1342 opn = "sltiu"; 1400 opn = "sltiu";
1343 break; 1401 break;
1344 case OPC_ANDI: 1402 case OPC_ANDI:
@@ -1645,11 +1703,11 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, @@ -1645,11 +1703,11 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1645 break; 1703 break;
1646 #endif 1704 #endif
1647 case OPC_SLT: 1705 case OPC_SLT:
1648 - gen_op_lt(); 1706 + gen_op_lt(cpu_T[0], cpu_T[1]);
1649 opn = "slt"; 1707 opn = "slt";
1650 break; 1708 break;
1651 case OPC_SLTU: 1709 case OPC_SLTU:
1652 - gen_op_ltu(); 1710 + gen_op_ltu(cpu_T[0], cpu_T[1]);
1653 opn = "sltu"; 1711 opn = "sltu";
1654 break; 1712 break;
1655 case OPC_AND: 1713 case OPC_AND:
@@ -2031,11 +2089,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, @@ -2031,11 +2089,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
2031 opn = "ddivu"; 2089 opn = "ddivu";
2032 break; 2090 break;
2033 case OPC_DMULT: 2091 case OPC_DMULT:
2034 - tcg_gen_helper_0_0(do_dmult); 2092 + tcg_gen_helper_0_2(do_dmult, cpu_T[0], cpu_T[1]);
2035 opn = "dmult"; 2093 opn = "dmult";
2036 break; 2094 break;
2037 case OPC_DMULTU: 2095 case OPC_DMULTU:
2038 - tcg_gen_helper_0_0(do_dmultu); 2096 + tcg_gen_helper_0_2(do_dmultu, cpu_T[0], cpu_T[1]);
2039 opn = "dmultu"; 2097 opn = "dmultu";
2040 break; 2098 break;
2041 #endif 2099 #endif
@@ -2181,59 +2239,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, @@ -2181,59 +2239,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2181 2239
2182 switch (opc) { 2240 switch (opc) {
2183 case OPC_VR54XX_MULS: 2241 case OPC_VR54XX_MULS:
2184 - tcg_gen_helper_0_0(do_muls); 2242 + tcg_gen_helper_1_2(do_muls, cpu_T[0], cpu_T[0], cpu_T[1]);
2185 opn = "muls"; 2243 opn = "muls";
2186 break; 2244 break;
2187 case OPC_VR54XX_MULSU: 2245 case OPC_VR54XX_MULSU:
2188 - tcg_gen_helper_0_0(do_mulsu); 2246 + tcg_gen_helper_1_2(do_mulsu, cpu_T[0], cpu_T[0], cpu_T[1]);
2189 opn = "mulsu"; 2247 opn = "mulsu";
2190 break; 2248 break;
2191 case OPC_VR54XX_MACC: 2249 case OPC_VR54XX_MACC:
2192 - tcg_gen_helper_0_0(do_macc); 2250 + tcg_gen_helper_1_2(do_macc, cpu_T[0], cpu_T[0], cpu_T[1]);
2193 opn = "macc"; 2251 opn = "macc";
2194 break; 2252 break;
2195 case OPC_VR54XX_MACCU: 2253 case OPC_VR54XX_MACCU:
2196 - tcg_gen_helper_0_0(do_maccu); 2254 + tcg_gen_helper_1_2(do_maccu, cpu_T[0], cpu_T[0], cpu_T[1]);
2197 opn = "maccu"; 2255 opn = "maccu";
2198 break; 2256 break;
2199 case OPC_VR54XX_MSAC: 2257 case OPC_VR54XX_MSAC:
2200 - tcg_gen_helper_0_0(do_msac); 2258 + tcg_gen_helper_1_2(do_msac, cpu_T[0], cpu_T[0], cpu_T[1]);
2201 opn = "msac"; 2259 opn = "msac";
2202 break; 2260 break;
2203 case OPC_VR54XX_MSACU: 2261 case OPC_VR54XX_MSACU:
2204 - tcg_gen_helper_0_0(do_msacu); 2262 + tcg_gen_helper_1_2(do_msacu, cpu_T[0], cpu_T[0], cpu_T[1]);
2205 opn = "msacu"; 2263 opn = "msacu";
2206 break; 2264 break;
2207 case OPC_VR54XX_MULHI: 2265 case OPC_VR54XX_MULHI:
2208 - tcg_gen_helper_0_0(do_mulhi); 2266 + tcg_gen_helper_1_2(do_mulhi, cpu_T[0], cpu_T[0], cpu_T[1]);
2209 opn = "mulhi"; 2267 opn = "mulhi";
2210 break; 2268 break;
2211 case OPC_VR54XX_MULHIU: 2269 case OPC_VR54XX_MULHIU:
2212 - tcg_gen_helper_0_0(do_mulhiu); 2270 + tcg_gen_helper_1_2(do_mulhiu, cpu_T[0], cpu_T[0], cpu_T[1]);
2213 opn = "mulhiu"; 2271 opn = "mulhiu";
2214 break; 2272 break;
2215 case OPC_VR54XX_MULSHI: 2273 case OPC_VR54XX_MULSHI:
2216 - tcg_gen_helper_0_0(do_mulshi); 2274 + tcg_gen_helper_1_2(do_mulshi, cpu_T[0], cpu_T[0], cpu_T[1]);
2217 opn = "mulshi"; 2275 opn = "mulshi";
2218 break; 2276 break;
2219 case OPC_VR54XX_MULSHIU: 2277 case OPC_VR54XX_MULSHIU:
2220 - tcg_gen_helper_0_0(do_mulshiu); 2278 + tcg_gen_helper_1_2(do_mulshiu, cpu_T[0], cpu_T[0], cpu_T[1]);
2221 opn = "mulshiu"; 2279 opn = "mulshiu";
2222 break; 2280 break;
2223 case OPC_VR54XX_MACCHI: 2281 case OPC_VR54XX_MACCHI:
2224 - tcg_gen_helper_0_0(do_macchi); 2282 + tcg_gen_helper_1_2(do_macchi, cpu_T[0], cpu_T[0], cpu_T[1]);
2225 opn = "macchi"; 2283 opn = "macchi";
2226 break; 2284 break;
2227 case OPC_VR54XX_MACCHIU: 2285 case OPC_VR54XX_MACCHIU:
2228 - tcg_gen_helper_0_0(do_macchiu); 2286 + tcg_gen_helper_1_2(do_macchiu, cpu_T[0], cpu_T[0], cpu_T[1]);
2229 opn = "macchiu"; 2287 opn = "macchiu";
2230 break; 2288 break;
2231 case OPC_VR54XX_MSACHI: 2289 case OPC_VR54XX_MSACHI:
2232 - tcg_gen_helper_0_0(do_msachi); 2290 + tcg_gen_helper_1_2(do_msachi, cpu_T[0], cpu_T[0], cpu_T[1]);
2233 opn = "msachi"; 2291 opn = "msachi";
2234 break; 2292 break;
2235 case OPC_VR54XX_MSACHIU: 2293 case OPC_VR54XX_MSACHIU:
2236 - tcg_gen_helper_0_0(do_msachiu); 2294 + tcg_gen_helper_1_2(do_msachiu, cpu_T[0], cpu_T[0], cpu_T[1]);
2237 opn = "msachiu"; 2295 opn = "msachiu";
2238 break; 2296 break;
2239 default: 2297 default:
@@ -2257,20 +2315,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, @@ -2257,20 +2315,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
2257 gen_load_gpr(cpu_T[0], rs); 2315 gen_load_gpr(cpu_T[0], rs);
2258 switch (opc) { 2316 switch (opc) {
2259 case OPC_CLO: 2317 case OPC_CLO:
2260 - tcg_gen_helper_0_0(do_clo); 2318 + tcg_gen_helper_1_1(do_clo, cpu_T[0], cpu_T[0]);
2261 opn = "clo"; 2319 opn = "clo";
2262 break; 2320 break;
2263 case OPC_CLZ: 2321 case OPC_CLZ:
2264 - tcg_gen_helper_0_0(do_clz); 2322 + tcg_gen_helper_1_1(do_clz, cpu_T[0], cpu_T[0]);
2265 opn = "clz"; 2323 opn = "clz";
2266 break; 2324 break;
2267 #if defined(TARGET_MIPS64) 2325 #if defined(TARGET_MIPS64)
2268 case OPC_DCLO: 2326 case OPC_DCLO:
2269 - tcg_gen_helper_0_0(do_dclo); 2327 + tcg_gen_helper_1_1(do_dclo, cpu_T[0], cpu_T[0]);
2270 opn = "dclo"; 2328 opn = "dclo";
2271 break; 2329 break;
2272 case OPC_DCLZ: 2330 case OPC_DCLZ:
2273 - tcg_gen_helper_0_0(do_dclz); 2331 + tcg_gen_helper_1_1(do_dclz, cpu_T[0], cpu_T[0]);
2274 opn = "dclz"; 2332 opn = "dclz";
2275 break; 2333 break;
2276 #endif 2334 #endif
@@ -2288,6 +2346,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, @@ -2288,6 +2346,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2288 int rs, int rt, int16_t imm) 2346 int rs, int rt, int16_t imm)
2289 { 2347 {
2290 int cond; 2348 int cond;
  2349 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2350 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2291 2351
2292 cond = 0; 2352 cond = 0;
2293 /* Load needed operands */ 2353 /* Load needed operands */
@@ -2300,8 +2360,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, @@ -2300,8 +2360,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2300 case OPC_TNE: 2360 case OPC_TNE:
2301 /* Compare two registers */ 2361 /* Compare two registers */
2302 if (rs != rt) { 2362 if (rs != rt) {
2303 - gen_load_gpr(cpu_T[0], rs);  
2304 - gen_load_gpr(cpu_T[1], rt); 2363 + gen_load_gpr(t0, rs);
  2364 + gen_load_gpr(t1, rt);
2305 cond = 1; 2365 cond = 1;
2306 } 2366 }
2307 break; 2367 break;
@@ -2313,8 +2373,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, @@ -2313,8 +2373,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2313 case OPC_TNEI: 2373 case OPC_TNEI:
2314 /* Compare register to immediate */ 2374 /* Compare register to immediate */
2315 if (rs != 0 || imm != 0) { 2375 if (rs != 0 || imm != 0) {
2316 - gen_load_gpr(cpu_T[0], rs);  
2317 - tcg_gen_movi_tl(cpu_T[1], (int32_t)imm); 2376 + gen_load_gpr(t0, rs);
  2377 + tcg_gen_movi_tl(t1, (int32_t)imm);
2318 cond = 1; 2378 cond = 1;
2319 } 2379 }
2320 break; 2380 break;
@@ -2328,7 +2388,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, @@ -2328,7 +2388,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2328 case OPC_TGEU: /* rs >= rs unsigned */ 2388 case OPC_TGEU: /* rs >= rs unsigned */
2329 case OPC_TGEIU: /* r0 >= 0 unsigned */ 2389 case OPC_TGEIU: /* r0 >= 0 unsigned */
2330 /* Always trap */ 2390 /* Always trap */
2331 - tcg_gen_movi_tl(cpu_T[0], 1); 2391 + tcg_gen_movi_tl(t0, 1);
2332 break; 2392 break;
2333 case OPC_TLT: /* rs < rs */ 2393 case OPC_TLT: /* rs < rs */
2334 case OPC_TLTI: /* r0 < 0 */ 2394 case OPC_TLTI: /* r0 < 0 */
@@ -2337,53 +2397,56 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, @@ -2337,53 +2397,56 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2337 case OPC_TNE: /* rs != rs */ 2397 case OPC_TNE: /* rs != rs */
2338 case OPC_TNEI: /* r0 != 0 */ 2398 case OPC_TNEI: /* r0 != 0 */
2339 /* Never trap: treat as NOP. */ 2399 /* Never trap: treat as NOP. */
2340 - return; 2400 + goto out;
2341 default: 2401 default:
2342 MIPS_INVAL("trap"); 2402 MIPS_INVAL("trap");
2343 generate_exception(ctx, EXCP_RI); 2403 generate_exception(ctx, EXCP_RI);
2344 - return; 2404 + goto out;
2345 } 2405 }
2346 } else { 2406 } else {
2347 switch (opc) { 2407 switch (opc) {
2348 case OPC_TEQ: 2408 case OPC_TEQ:
2349 case OPC_TEQI: 2409 case OPC_TEQI:
2350 - gen_op_eq(); 2410 + gen_op_eq(t0, t1);
2351 break; 2411 break;
2352 case OPC_TGE: 2412 case OPC_TGE:
2353 case OPC_TGEI: 2413 case OPC_TGEI:
2354 - gen_op_ge(); 2414 + gen_op_ge(t0, t1);
2355 break; 2415 break;
2356 case OPC_TGEU: 2416 case OPC_TGEU:
2357 case OPC_TGEIU: 2417 case OPC_TGEIU:
2358 - gen_op_geu(); 2418 + gen_op_geu(t0, t1);
2359 break; 2419 break;
2360 case OPC_TLT: 2420 case OPC_TLT:
2361 case OPC_TLTI: 2421 case OPC_TLTI:
2362 - gen_op_lt(); 2422 + gen_op_lt(t0, t1);
2363 break; 2423 break;
2364 case OPC_TLTU: 2424 case OPC_TLTU:
2365 case OPC_TLTIU: 2425 case OPC_TLTIU:
2366 - gen_op_ltu(); 2426 + gen_op_ltu(t0, t1);
2367 break; 2427 break;
2368 case OPC_TNE: 2428 case OPC_TNE:
2369 case OPC_TNEI: 2429 case OPC_TNEI:
2370 - gen_op_ne(); 2430 + gen_op_ne(t0, t1);
2371 break; 2431 break;
2372 default: 2432 default:
2373 MIPS_INVAL("trap"); 2433 MIPS_INVAL("trap");
2374 generate_exception(ctx, EXCP_RI); 2434 generate_exception(ctx, EXCP_RI);
2375 - return; 2435 + goto out;
2376 } 2436 }
2377 } 2437 }
2378 save_cpu_state(ctx, 1); 2438 save_cpu_state(ctx, 1);
2379 { 2439 {
2380 int l1 = gen_new_label(); 2440 int l1 = gen_new_label();
2381 2441
2382 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);  
2383 - tcg_gen_helper_0_1i(do_raise_exception, EXCP_TRAP); 2442 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
  2443 + tcg_gen_helper_0_i(do_raise_exception, EXCP_TRAP);
2384 gen_set_label(l1); 2444 gen_set_label(l1);
2385 } 2445 }
2386 ctx->bstate = BS_STOP; 2446 ctx->bstate = BS_STOP;
  2447 + out:
  2448 + tcg_temp_free(t0);
  2449 + tcg_temp_free(t1);
2387 } 2450 }
2388 2451
2389 static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2452 static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
@@ -2546,69 +2609,69 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, @@ -2546,69 +2609,69 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2546 } else { 2609 } else {
2547 switch (opc) { 2610 switch (opc) {
2548 case OPC_BEQ: 2611 case OPC_BEQ:
2549 - gen_op_eq(); 2612 + gen_op_eq(cpu_T[0], cpu_T[1]);
2550 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx, 2613 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2551 regnames[rs], regnames[rt], btarget); 2614 regnames[rs], regnames[rt], btarget);
2552 goto not_likely; 2615 goto not_likely;
2553 case OPC_BEQL: 2616 case OPC_BEQL:
2554 - gen_op_eq(); 2617 + gen_op_eq(cpu_T[0], cpu_T[1]);
2555 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx, 2618 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2556 regnames[rs], regnames[rt], btarget); 2619 regnames[rs], regnames[rt], btarget);
2557 goto likely; 2620 goto likely;
2558 case OPC_BNE: 2621 case OPC_BNE:
2559 - gen_op_ne(); 2622 + gen_op_ne(cpu_T[0], cpu_T[1]);
2560 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx, 2623 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2561 regnames[rs], regnames[rt], btarget); 2624 regnames[rs], regnames[rt], btarget);
2562 goto not_likely; 2625 goto not_likely;
2563 case OPC_BNEL: 2626 case OPC_BNEL:
2564 - gen_op_ne(); 2627 + gen_op_ne(cpu_T[0], cpu_T[1]);
2565 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx, 2628 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2566 regnames[rs], regnames[rt], btarget); 2629 regnames[rs], regnames[rt], btarget);
2567 goto likely; 2630 goto likely;
2568 case OPC_BGEZ: 2631 case OPC_BGEZ:
2569 - gen_op_gez(); 2632 + gen_op_gez(cpu_T[0]);
2570 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget); 2633 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
2571 goto not_likely; 2634 goto not_likely;
2572 case OPC_BGEZL: 2635 case OPC_BGEZL:
2573 - gen_op_gez(); 2636 + gen_op_gez(cpu_T[0]);
2574 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget); 2637 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2575 goto likely; 2638 goto likely;
2576 case OPC_BGEZAL: 2639 case OPC_BGEZAL:
2577 - gen_op_gez(); 2640 + gen_op_gez(cpu_T[0]);
2578 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget); 2641 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
2579 blink = 31; 2642 blink = 31;
2580 goto not_likely; 2643 goto not_likely;
2581 case OPC_BGEZALL: 2644 case OPC_BGEZALL:
2582 - gen_op_gez(); 2645 + gen_op_gez(cpu_T[0]);
2583 blink = 31; 2646 blink = 31;
2584 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget); 2647 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
2585 goto likely; 2648 goto likely;
2586 case OPC_BGTZ: 2649 case OPC_BGTZ:
2587 - gen_op_gtz(); 2650 + gen_op_gtz(cpu_T[0]);
2588 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget); 2651 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
2589 goto not_likely; 2652 goto not_likely;
2590 case OPC_BGTZL: 2653 case OPC_BGTZL:
2591 - gen_op_gtz(); 2654 + gen_op_gtz(cpu_T[0]);
2592 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget); 2655 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2593 goto likely; 2656 goto likely;
2594 case OPC_BLEZ: 2657 case OPC_BLEZ:
2595 - gen_op_lez(); 2658 + gen_op_lez(cpu_T[0]);
2596 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget); 2659 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
2597 goto not_likely; 2660 goto not_likely;
2598 case OPC_BLEZL: 2661 case OPC_BLEZL:
2599 - gen_op_lez(); 2662 + gen_op_lez(cpu_T[0]);
2600 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget); 2663 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2601 goto likely; 2664 goto likely;
2602 case OPC_BLTZ: 2665 case OPC_BLTZ:
2603 - gen_op_ltz(); 2666 + gen_op_ltz(cpu_T[0]);
2604 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget); 2667 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
2605 goto not_likely; 2668 goto not_likely;
2606 case OPC_BLTZL: 2669 case OPC_BLTZL:
2607 - gen_op_ltz(); 2670 + gen_op_ltz(cpu_T[0]);
2608 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget); 2671 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2609 goto likely; 2672 goto likely;
2610 case OPC_BLTZAL: 2673 case OPC_BLTZAL:
2611 - gen_op_ltz(); 2674 + gen_op_ltz(cpu_T[0]);
2612 blink = 31; 2675 blink = 31;
2613 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget); 2676 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
2614 not_likely: 2677 not_likely:
@@ -2616,7 +2679,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, @@ -2616,7 +2679,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2616 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond)); 2679 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
2617 break; 2680 break;
2618 case OPC_BLTZALL: 2681 case OPC_BLTZALL:
2619 - gen_op_ltz(); 2682 + gen_op_ltz(cpu_T[0]);
2620 blink = 31; 2683 blink = 31;
2621 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget); 2684 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
2622 likely: 2685 likely:
@@ -2648,49 +2711,49 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, @@ -2648,49 +2711,49 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2648 case OPC_EXT: 2711 case OPC_EXT:
2649 if (lsb + msb > 31) 2712 if (lsb + msb > 31)
2650 goto fail; 2713 goto fail;
2651 - tcg_gen_helper_0_2ii(do_ext, lsb, msb + 1); 2714 + tcg_gen_helper_1_2ii(do_ext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1);
2652 break; 2715 break;
2653 #if defined(TARGET_MIPS64) 2716 #if defined(TARGET_MIPS64)
2654 case OPC_DEXTM: 2717 case OPC_DEXTM:
2655 if (lsb + msb > 63) 2718 if (lsb + msb > 63)
2656 goto fail; 2719 goto fail;
2657 - tcg_gen_helper_0_2ii(do_dext, lsb, msb + 1 + 32); 2720 + tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1 + 32);
2658 break; 2721 break;
2659 case OPC_DEXTU: 2722 case OPC_DEXTU:
2660 if (lsb + msb > 63) 2723 if (lsb + msb > 63)
2661 goto fail; 2724 goto fail;
2662 - tcg_gen_helper_0_2ii(do_dext, lsb + 32, msb + 1); 2725 + tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb + 1);
2663 break; 2726 break;
2664 case OPC_DEXT: 2727 case OPC_DEXT:
2665 if (lsb + msb > 63) 2728 if (lsb + msb > 63)
2666 goto fail; 2729 goto fail;
2667 - tcg_gen_helper_0_2ii(do_dext, lsb, msb + 1); 2730 + tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1);
2668 break; 2731 break;
2669 #endif 2732 #endif
2670 case OPC_INS: 2733 case OPC_INS:
2671 if (lsb > msb) 2734 if (lsb > msb)
2672 goto fail; 2735 goto fail;
2673 gen_load_gpr(cpu_T[0], rt); 2736 gen_load_gpr(cpu_T[0], rt);
2674 - tcg_gen_helper_0_2ii(do_ins, lsb, msb - lsb + 1); 2737 + tcg_gen_helper_1_2ii(do_ins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1);
2675 break; 2738 break;
2676 #if defined(TARGET_MIPS64) 2739 #if defined(TARGET_MIPS64)
2677 case OPC_DINSM: 2740 case OPC_DINSM:
2678 if (lsb > msb) 2741 if (lsb > msb)
2679 goto fail; 2742 goto fail;
2680 gen_load_gpr(cpu_T[0], rt); 2743 gen_load_gpr(cpu_T[0], rt);
2681 - tcg_gen_helper_0_2ii(do_dins, lsb, msb - lsb + 1 + 32); 2744 + tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1 + 32);
2682 break; 2745 break;
2683 case OPC_DINSU: 2746 case OPC_DINSU:
2684 if (lsb > msb) 2747 if (lsb > msb)
2685 goto fail; 2748 goto fail;
2686 gen_load_gpr(cpu_T[0], rt); 2749 gen_load_gpr(cpu_T[0], rt);
2687 - tcg_gen_helper_0_2ii(do_dins, lsb + 32, msb - lsb + 1); 2750 + tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb - lsb + 1);
2688 break; 2751 break;
2689 case OPC_DINS: 2752 case OPC_DINS:
2690 if (lsb > msb) 2753 if (lsb > msb)
2691 goto fail; 2754 goto fail;
2692 gen_load_gpr(cpu_T[0], rt); 2755 gen_load_gpr(cpu_T[0], rt);
2693 - tcg_gen_helper_0_2ii(do_dins, lsb, msb - lsb + 1); 2756 + tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1);
2694 break; 2757 break;
2695 #endif 2758 #endif
2696 default: 2759 default:
@@ -2750,17 +2813,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2750,17 +2813,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2750 break; 2813 break;
2751 case 1: 2814 case 1:
2752 check_insn(env, ctx, ASE_MT); 2815 check_insn(env, ctx, ASE_MT);
2753 - tcg_gen_helper_0_0(do_mfc0_mvpcontrol); 2816 + tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]);
2754 rn = "MVPControl"; 2817 rn = "MVPControl";
2755 break; 2818 break;
2756 case 2: 2819 case 2:
2757 check_insn(env, ctx, ASE_MT); 2820 check_insn(env, ctx, ASE_MT);
2758 - tcg_gen_helper_0_0(do_mfc0_mvpconf0); 2821 + tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]);
2759 rn = "MVPConf0"; 2822 rn = "MVPConf0";
2760 break; 2823 break;
2761 case 3: 2824 case 3:
2762 check_insn(env, ctx, ASE_MT); 2825 check_insn(env, ctx, ASE_MT);
2763 - tcg_gen_helper_0_0(do_mfc0_mvpconf1); 2826 + tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]);
2764 rn = "MVPConf1"; 2827 rn = "MVPConf1";
2765 break; 2828 break;
2766 default: 2829 default:
@@ -2770,7 +2833,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2770,7 +2833,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2770 case 1: 2833 case 1:
2771 switch (sel) { 2834 switch (sel) {
2772 case 0: 2835 case 0:
2773 - tcg_gen_helper_0_0(do_mfc0_random); 2836 + tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]);
2774 rn = "Random"; 2837 rn = "Random";
2775 break; 2838 break;
2776 case 1: 2839 case 1:
@@ -2821,37 +2884,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2821,37 +2884,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2821 break; 2884 break;
2822 case 1: 2885 case 1:
2823 check_insn(env, ctx, ASE_MT); 2886 check_insn(env, ctx, ASE_MT);
2824 - tcg_gen_helper_0_0(do_mfc0_tcstatus); 2887 + tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]);
2825 rn = "TCStatus"; 2888 rn = "TCStatus";
2826 break; 2889 break;
2827 case 2: 2890 case 2:
2828 check_insn(env, ctx, ASE_MT); 2891 check_insn(env, ctx, ASE_MT);
2829 - tcg_gen_helper_0_0(do_mfc0_tcbind); 2892 + tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]);
2830 rn = "TCBind"; 2893 rn = "TCBind";
2831 break; 2894 break;
2832 case 3: 2895 case 3:
2833 check_insn(env, ctx, ASE_MT); 2896 check_insn(env, ctx, ASE_MT);
2834 - tcg_gen_helper_0_0(do_mfc0_tcrestart); 2897 + tcg_gen_helper_1_1(do_mfc0_tcrestart, cpu_T[0], cpu_T[0]);
2835 rn = "TCRestart"; 2898 rn = "TCRestart";
2836 break; 2899 break;
2837 case 4: 2900 case 4:
2838 check_insn(env, ctx, ASE_MT); 2901 check_insn(env, ctx, ASE_MT);
2839 - tcg_gen_helper_0_0(do_mfc0_tchalt); 2902 + tcg_gen_helper_1_1(do_mfc0_tchalt, cpu_T[0], cpu_T[0]);
2840 rn = "TCHalt"; 2903 rn = "TCHalt";
2841 break; 2904 break;
2842 case 5: 2905 case 5:
2843 check_insn(env, ctx, ASE_MT); 2906 check_insn(env, ctx, ASE_MT);
2844 - tcg_gen_helper_0_0(do_mfc0_tccontext); 2907 + tcg_gen_helper_1_1(do_mfc0_tccontext, cpu_T[0], cpu_T[0]);
2845 rn = "TCContext"; 2908 rn = "TCContext";
2846 break; 2909 break;
2847 case 6: 2910 case 6:
2848 check_insn(env, ctx, ASE_MT); 2911 check_insn(env, ctx, ASE_MT);
2849 - tcg_gen_helper_0_0(do_mfc0_tcschedule); 2912 + tcg_gen_helper_1_1(do_mfc0_tcschedule, cpu_T[0], cpu_T[0]);
2850 rn = "TCSchedule"; 2913 rn = "TCSchedule";
2851 break; 2914 break;
2852 case 7: 2915 case 7:
2853 check_insn(env, ctx, ASE_MT); 2916 check_insn(env, ctx, ASE_MT);
2854 - tcg_gen_helper_0_0(do_mfc0_tcschefback); 2917 + tcg_gen_helper_1_1(do_mfc0_tcschefback, cpu_T[0], cpu_T[0]);
2855 rn = "TCScheFBack"; 2918 rn = "TCScheFBack";
2856 break; 2919 break;
2857 default: 2920 default:
@@ -2877,7 +2940,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2877,7 +2940,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2877 rn = "Context"; 2940 rn = "Context";
2878 break; 2941 break;
2879 case 1: 2942 case 1:
2880 -// tcg_gen_helper_0_0(do_mfc0_contextconfig); /* SmartMIPS ASE */ 2943 +// tcg_gen_helper_1_1(do_mfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */
2881 rn = "ContextConfig"; 2944 rn = "ContextConfig";
2882 // break; 2945 // break;
2883 default: 2946 default:
@@ -2959,7 +3022,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2959,7 +3022,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2959 case 9: 3022 case 9:
2960 switch (sel) { 3023 switch (sel) {
2961 case 0: 3024 case 0:
2962 - tcg_gen_helper_0_0(do_mfc0_count); 3025 + tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]);
2963 rn = "Count"; 3026 rn = "Count";
2964 break; 3027 break;
2965 /* 6,7 are implementation dependent */ 3028 /* 6,7 are implementation dependent */
@@ -3085,7 +3148,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3085,7 +3148,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3085 case 17: 3148 case 17:
3086 switch (sel) { 3149 switch (sel) {
3087 case 0: 3150 case 0:
3088 - tcg_gen_helper_0_0(do_mfc0_lladdr); 3151 + tcg_gen_helper_1_1(do_mfc0_lladdr, cpu_T[0], cpu_T[0]);
3089 rn = "LLAddr"; 3152 rn = "LLAddr";
3090 break; 3153 break;
3091 default: 3154 default:
@@ -3095,7 +3158,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3095,7 +3158,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3095 case 18: 3158 case 18:
3096 switch (sel) { 3159 switch (sel) {
3097 case 0 ... 7: 3160 case 0 ... 7:
3098 - tcg_gen_helper_0_1i(do_mfc0_watchlo, sel); 3161 + tcg_gen_helper_1_1i(do_mfc0_watchlo, cpu_T[0], cpu_T[0], sel);
3099 rn = "WatchLo"; 3162 rn = "WatchLo";
3100 break; 3163 break;
3101 default: 3164 default:
@@ -3105,7 +3168,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3105,7 +3168,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3105 case 19: 3168 case 19:
3106 switch (sel) { 3169 switch (sel) {
3107 case 0 ...7: 3170 case 0 ...7:
3108 - tcg_gen_helper_0_1i(do_mfc0_watchhi, sel); 3171 + tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel);
3109 rn = "WatchHi"; 3172 rn = "WatchHi";
3110 break; 3173 break;
3111 default: 3174 default:
@@ -3144,23 +3207,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3144,23 +3207,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3144 case 23: 3207 case 23:
3145 switch (sel) { 3208 switch (sel) {
3146 case 0: 3209 case 0:
3147 - tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */ 3210 + tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */
3148 rn = "Debug"; 3211 rn = "Debug";
3149 break; 3212 break;
3150 case 1: 3213 case 1:
3151 -// tcg_gen_helper_0_0(do_mfc0_tracecontrol); /* PDtrace support */ 3214 +// tcg_gen_helper_1_1(do_mfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */
3152 rn = "TraceControl"; 3215 rn = "TraceControl";
3153 // break; 3216 // break;
3154 case 2: 3217 case 2:
3155 -// tcg_gen_helper_0_0(do_mfc0_tracecontrol2); /* PDtrace support */ 3218 +// tcg_gen_helper_1_1(do_mfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */
3156 rn = "TraceControl2"; 3219 rn = "TraceControl2";
3157 // break; 3220 // break;
3158 case 3: 3221 case 3:
3159 -// tcg_gen_helper_0_0(do_mfc0_usertracedata); /* PDtrace support */ 3222 +// tcg_gen_helper_1_1(do_mfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */
3160 rn = "UserTraceData"; 3223 rn = "UserTraceData";
3161 // break; 3224 // break;
3162 case 4: 3225 case 4:
3163 -// tcg_gen_helper_0_0(do_mfc0_debug); /* PDtrace support */ 3226 +// tcg_gen_helper_1_1(do_mfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */
3164 rn = "TraceBPC"; 3227 rn = "TraceBPC";
3165 // break; 3228 // break;
3166 default: 3229 default:
@@ -3186,31 +3249,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3186,31 +3249,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3186 rn = "Performance0"; 3249 rn = "Performance0";
3187 break; 3250 break;
3188 case 1: 3251 case 1:
3189 -// tcg_gen_helper_0_0(do_mfc0_performance1); 3252 +// tcg_gen_helper_1_1(do_mfc0_performance1, cpu_T[0], cpu_T[0]);
3190 rn = "Performance1"; 3253 rn = "Performance1";
3191 // break; 3254 // break;
3192 case 2: 3255 case 2:
3193 -// tcg_gen_helper_0_0(do_mfc0_performance2); 3256 +// tcg_gen_helper_1_1(do_mfc0_performance2, cpu_T[0], cpu_T[0]);
3194 rn = "Performance2"; 3257 rn = "Performance2";
3195 // break; 3258 // break;
3196 case 3: 3259 case 3:
3197 -// tcg_gen_helper_0_0(do_mfc0_performance3); 3260 +// tcg_gen_helper_1_1(do_mfc0_performance3, cpu_T[0], cpu_T[0]);
3198 rn = "Performance3"; 3261 rn = "Performance3";
3199 // break; 3262 // break;
3200 case 4: 3263 case 4:
3201 -// tcg_gen_helper_0_0(do_mfc0_performance4); 3264 +// tcg_gen_helper_1_1(do_mfc0_performance4, cpu_T[0], cpu_T[0]);
3202 rn = "Performance4"; 3265 rn = "Performance4";
3203 // break; 3266 // break;
3204 case 5: 3267 case 5:
3205 -// tcg_gen_helper_0_0(do_mfc0_performance5); 3268 +// tcg_gen_helper_1_1(do_mfc0_performance5, cpu_T[0], cpu_T[0]);
3206 rn = "Performance5"; 3269 rn = "Performance5";
3207 // break; 3270 // break;
3208 case 6: 3271 case 6:
3209 -// tcg_gen_helper_0_0(do_mfc0_performance6); 3272 +// tcg_gen_helper_1_1(do_mfc0_performance6, cpu_T[0], cpu_T[0]);
3210 rn = "Performance6"; 3273 rn = "Performance6";
3211 // break; 3274 // break;
3212 case 7: 3275 case 7:
3213 -// tcg_gen_helper_0_0(do_mfc0_performance7); 3276 +// tcg_gen_helper_1_1(do_mfc0_performance7, cpu_T[0], cpu_T[0]);
3214 rn = "Performance7"; 3277 rn = "Performance7";
3215 // break; 3278 // break;
3216 default: 3279 default:
@@ -3324,12 +3387,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3324,12 +3387,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3324 case 0: 3387 case 0:
3325 switch (sel) { 3388 switch (sel) {
3326 case 0: 3389 case 0:
3327 - tcg_gen_helper_0_0(do_mtc0_index); 3390 + tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]);
3328 rn = "Index"; 3391 rn = "Index";
3329 break; 3392 break;
3330 case 1: 3393 case 1:
3331 check_insn(env, ctx, ASE_MT); 3394 check_insn(env, ctx, ASE_MT);
3332 - tcg_gen_helper_0_0(do_mtc0_mvpcontrol); 3395 + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]);
3333 rn = "MVPControl"; 3396 rn = "MVPControl";
3334 break; 3397 break;
3335 case 2: 3398 case 2:
@@ -3354,22 +3417,22 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3354,22 +3417,22 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3354 break; 3417 break;
3355 case 1: 3418 case 1:
3356 check_insn(env, ctx, ASE_MT); 3419 check_insn(env, ctx, ASE_MT);
3357 - tcg_gen_helper_0_0(do_mtc0_vpecontrol); 3420 + tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]);
3358 rn = "VPEControl"; 3421 rn = "VPEControl";
3359 break; 3422 break;
3360 case 2: 3423 case 2:
3361 check_insn(env, ctx, ASE_MT); 3424 check_insn(env, ctx, ASE_MT);
3362 - tcg_gen_helper_0_0(do_mtc0_vpeconf0); 3425 + tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]);
3363 rn = "VPEConf0"; 3426 rn = "VPEConf0";
3364 break; 3427 break;
3365 case 3: 3428 case 3:
3366 check_insn(env, ctx, ASE_MT); 3429 check_insn(env, ctx, ASE_MT);
3367 - tcg_gen_helper_0_0(do_mtc0_vpeconf1); 3430 + tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]);
3368 rn = "VPEConf1"; 3431 rn = "VPEConf1";
3369 break; 3432 break;
3370 case 4: 3433 case 4:
3371 check_insn(env, ctx, ASE_MT); 3434 check_insn(env, ctx, ASE_MT);
3372 - tcg_gen_helper_0_0(do_mtc0_yqmask); 3435 + tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]);
3373 rn = "YQMask"; 3436 rn = "YQMask";
3374 break; 3437 break;
3375 case 5: 3438 case 5:
@@ -3384,7 +3447,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3384,7 +3447,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3384 break; 3447 break;
3385 case 7: 3448 case 7:
3386 check_insn(env, ctx, ASE_MT); 3449 check_insn(env, ctx, ASE_MT);
3387 - tcg_gen_helper_0_0(do_mtc0_vpeopt); 3450 + tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]);
3388 rn = "VPEOpt"; 3451 rn = "VPEOpt";
3389 break; 3452 break;
3390 default: 3453 default:
@@ -3394,42 +3457,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3394,42 +3457,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3394 case 2: 3457 case 2:
3395 switch (sel) { 3458 switch (sel) {
3396 case 0: 3459 case 0:
3397 - tcg_gen_helper_0_0(do_mtc0_entrylo0); 3460 + tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]);
3398 rn = "EntryLo0"; 3461 rn = "EntryLo0";
3399 break; 3462 break;
3400 case 1: 3463 case 1:
3401 check_insn(env, ctx, ASE_MT); 3464 check_insn(env, ctx, ASE_MT);
3402 - tcg_gen_helper_0_0(do_mtc0_tcstatus); 3465 + tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]);
3403 rn = "TCStatus"; 3466 rn = "TCStatus";
3404 break; 3467 break;
3405 case 2: 3468 case 2:
3406 check_insn(env, ctx, ASE_MT); 3469 check_insn(env, ctx, ASE_MT);
3407 - tcg_gen_helper_0_0(do_mtc0_tcbind); 3470 + tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]);
3408 rn = "TCBind"; 3471 rn = "TCBind";
3409 break; 3472 break;
3410 case 3: 3473 case 3:
3411 check_insn(env, ctx, ASE_MT); 3474 check_insn(env, ctx, ASE_MT);
3412 - tcg_gen_helper_0_0(do_mtc0_tcrestart); 3475 + tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]);
3413 rn = "TCRestart"; 3476 rn = "TCRestart";
3414 break; 3477 break;
3415 case 4: 3478 case 4:
3416 check_insn(env, ctx, ASE_MT); 3479 check_insn(env, ctx, ASE_MT);
3417 - tcg_gen_helper_0_0(do_mtc0_tchalt); 3480 + tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]);
3418 rn = "TCHalt"; 3481 rn = "TCHalt";
3419 break; 3482 break;
3420 case 5: 3483 case 5:
3421 check_insn(env, ctx, ASE_MT); 3484 check_insn(env, ctx, ASE_MT);
3422 - tcg_gen_helper_0_0(do_mtc0_tccontext); 3485 + tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]);
3423 rn = "TCContext"; 3486 rn = "TCContext";
3424 break; 3487 break;
3425 case 6: 3488 case 6:
3426 check_insn(env, ctx, ASE_MT); 3489 check_insn(env, ctx, ASE_MT);
3427 - tcg_gen_helper_0_0(do_mtc0_tcschedule); 3490 + tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]);
3428 rn = "TCSchedule"; 3491 rn = "TCSchedule";
3429 break; 3492 break;
3430 case 7: 3493 case 7:
3431 check_insn(env, ctx, ASE_MT); 3494 check_insn(env, ctx, ASE_MT);
3432 - tcg_gen_helper_0_0(do_mtc0_tcschefback); 3495 + tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]);
3433 rn = "TCScheFBack"; 3496 rn = "TCScheFBack";
3434 break; 3497 break;
3435 default: 3498 default:
@@ -3439,7 +3502,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3439,7 +3502,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3439 case 3: 3502 case 3:
3440 switch (sel) { 3503 switch (sel) {
3441 case 0: 3504 case 0:
3442 - tcg_gen_helper_0_0(do_mtc0_entrylo1); 3505 + tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]);
3443 rn = "EntryLo1"; 3506 rn = "EntryLo1";
3444 break; 3507 break;
3445 default: 3508 default:
@@ -3449,11 +3512,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3449,11 +3512,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3449 case 4: 3512 case 4:
3450 switch (sel) { 3513 switch (sel) {
3451 case 0: 3514 case 0:
3452 - tcg_gen_helper_0_0(do_mtc0_context); 3515 + tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]);
3453 rn = "Context"; 3516 rn = "Context";
3454 break; 3517 break;
3455 case 1: 3518 case 1:
3456 -// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */ 3519 +// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */
3457 rn = "ContextConfig"; 3520 rn = "ContextConfig";
3458 // break; 3521 // break;
3459 default: 3522 default:
@@ -3463,12 +3526,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3463,12 +3526,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3463 case 5: 3526 case 5:
3464 switch (sel) { 3527 switch (sel) {
3465 case 0: 3528 case 0:
3466 - tcg_gen_helper_0_0(do_mtc0_pagemask); 3529 + tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]);
3467 rn = "PageMask"; 3530 rn = "PageMask";
3468 break; 3531 break;
3469 case 1: 3532 case 1:
3470 check_insn(env, ctx, ISA_MIPS32R2); 3533 check_insn(env, ctx, ISA_MIPS32R2);
3471 - tcg_gen_helper_0_0(do_mtc0_pagegrain); 3534 + tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]);
3472 rn = "PageGrain"; 3535 rn = "PageGrain";
3473 break; 3536 break;
3474 default: 3537 default:
@@ -3478,32 +3541,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3478,32 +3541,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3478 case 6: 3541 case 6:
3479 switch (sel) { 3542 switch (sel) {
3480 case 0: 3543 case 0:
3481 - tcg_gen_helper_0_0(do_mtc0_wired); 3544 + tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]);
3482 rn = "Wired"; 3545 rn = "Wired";
3483 break; 3546 break;
3484 case 1: 3547 case 1:
3485 check_insn(env, ctx, ISA_MIPS32R2); 3548 check_insn(env, ctx, ISA_MIPS32R2);
3486 - tcg_gen_helper_0_0(do_mtc0_srsconf0); 3549 + tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]);
3487 rn = "SRSConf0"; 3550 rn = "SRSConf0";
3488 break; 3551 break;
3489 case 2: 3552 case 2:
3490 check_insn(env, ctx, ISA_MIPS32R2); 3553 check_insn(env, ctx, ISA_MIPS32R2);
3491 - tcg_gen_helper_0_0(do_mtc0_srsconf1); 3554 + tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]);
3492 rn = "SRSConf1"; 3555 rn = "SRSConf1";
3493 break; 3556 break;
3494 case 3: 3557 case 3:
3495 check_insn(env, ctx, ISA_MIPS32R2); 3558 check_insn(env, ctx, ISA_MIPS32R2);
3496 - tcg_gen_helper_0_0(do_mtc0_srsconf2); 3559 + tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]);
3497 rn = "SRSConf2"; 3560 rn = "SRSConf2";
3498 break; 3561 break;
3499 case 4: 3562 case 4:
3500 check_insn(env, ctx, ISA_MIPS32R2); 3563 check_insn(env, ctx, ISA_MIPS32R2);
3501 - tcg_gen_helper_0_0(do_mtc0_srsconf3); 3564 + tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]);
3502 rn = "SRSConf3"; 3565 rn = "SRSConf3";
3503 break; 3566 break;
3504 case 5: 3567 case 5:
3505 check_insn(env, ctx, ISA_MIPS32R2); 3568 check_insn(env, ctx, ISA_MIPS32R2);
3506 - tcg_gen_helper_0_0(do_mtc0_srsconf4); 3569 + tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]);
3507 rn = "SRSConf4"; 3570 rn = "SRSConf4";
3508 break; 3571 break;
3509 default: 3572 default:
@@ -3514,7 +3577,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3514,7 +3577,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3514 switch (sel) { 3577 switch (sel) {
3515 case 0: 3578 case 0:
3516 check_insn(env, ctx, ISA_MIPS32R2); 3579 check_insn(env, ctx, ISA_MIPS32R2);
3517 - tcg_gen_helper_0_0(do_mtc0_hwrena); 3580 + tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]);
3518 rn = "HWREna"; 3581 rn = "HWREna";
3519 break; 3582 break;
3520 default: 3583 default:
@@ -3528,7 +3591,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3528,7 +3591,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3528 case 9: 3591 case 9:
3529 switch (sel) { 3592 switch (sel) {
3530 case 0: 3593 case 0:
3531 - tcg_gen_helper_0_0(do_mtc0_count); 3594 + tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]);
3532 rn = "Count"; 3595 rn = "Count";
3533 break; 3596 break;
3534 /* 6,7 are implementation dependent */ 3597 /* 6,7 are implementation dependent */
@@ -3541,7 +3604,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3541,7 +3604,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3541 case 10: 3604 case 10:
3542 switch (sel) { 3605 switch (sel) {
3543 case 0: 3606 case 0:
3544 - tcg_gen_helper_0_0(do_mtc0_entryhi); 3607 + tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]);
3545 rn = "EntryHi"; 3608 rn = "EntryHi";
3546 break; 3609 break;
3547 default: 3610 default:
@@ -3551,7 +3614,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3551,7 +3614,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3551 case 11: 3614 case 11:
3552 switch (sel) { 3615 switch (sel) {
3553 case 0: 3616 case 0:
3554 - tcg_gen_helper_0_0(do_mtc0_compare); 3617 + tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]);
3555 rn = "Compare"; 3618 rn = "Compare";
3556 break; 3619 break;
3557 /* 6,7 are implementation dependent */ 3620 /* 6,7 are implementation dependent */
@@ -3564,7 +3627,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3564,7 +3627,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3564 case 12: 3627 case 12:
3565 switch (sel) { 3628 switch (sel) {
3566 case 0: 3629 case 0:
3567 - tcg_gen_helper_0_0(do_mtc0_status); 3630 + tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]);
3568 /* BS_STOP isn't good enough here, hflags may have changed. */ 3631 /* BS_STOP isn't good enough here, hflags may have changed. */
3569 gen_save_pc(ctx->pc + 4); 3632 gen_save_pc(ctx->pc + 4);
3570 ctx->bstate = BS_EXCP; 3633 ctx->bstate = BS_EXCP;
@@ -3572,14 +3635,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3572,14 +3635,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3572 break; 3635 break;
3573 case 1: 3636 case 1:
3574 check_insn(env, ctx, ISA_MIPS32R2); 3637 check_insn(env, ctx, ISA_MIPS32R2);
3575 - tcg_gen_helper_0_0(do_mtc0_intctl); 3638 + tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]);
3576 /* Stop translation as we may have switched the execution mode */ 3639 /* Stop translation as we may have switched the execution mode */
3577 ctx->bstate = BS_STOP; 3640 ctx->bstate = BS_STOP;
3578 rn = "IntCtl"; 3641 rn = "IntCtl";
3579 break; 3642 break;
3580 case 2: 3643 case 2:
3581 check_insn(env, ctx, ISA_MIPS32R2); 3644 check_insn(env, ctx, ISA_MIPS32R2);
3582 - tcg_gen_helper_0_0(do_mtc0_srsctl); 3645 + tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]);
3583 /* Stop translation as we may have switched the execution mode */ 3646 /* Stop translation as we may have switched the execution mode */
3584 ctx->bstate = BS_STOP; 3647 ctx->bstate = BS_STOP;
3585 rn = "SRSCtl"; 3648 rn = "SRSCtl";
@@ -3598,7 +3661,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3598,7 +3661,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3598 case 13: 3661 case 13:
3599 switch (sel) { 3662 switch (sel) {
3600 case 0: 3663 case 0:
3601 - tcg_gen_helper_0_0(do_mtc0_cause); 3664 + tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]);
3602 rn = "Cause"; 3665 rn = "Cause";
3603 break; 3666 break;
3604 default: 3667 default:
@@ -3625,7 +3688,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3625,7 +3688,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3625 break; 3688 break;
3626 case 1: 3689 case 1:
3627 check_insn(env, ctx, ISA_MIPS32R2); 3690 check_insn(env, ctx, ISA_MIPS32R2);
3628 - tcg_gen_helper_0_0(do_mtc0_ebase); 3691 + tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]);
3629 rn = "EBase"; 3692 rn = "EBase";
3630 break; 3693 break;
3631 default: 3694 default:
@@ -3635,7 +3698,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3635,7 +3698,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3635 case 16: 3698 case 16:
3636 switch (sel) { 3699 switch (sel) {
3637 case 0: 3700 case 0:
3638 - tcg_gen_helper_0_0(do_mtc0_config0); 3701 + tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]);
3639 rn = "Config"; 3702 rn = "Config";
3640 /* Stop translation as we may have switched the execution mode */ 3703 /* Stop translation as we may have switched the execution mode */
3641 ctx->bstate = BS_STOP; 3704 ctx->bstate = BS_STOP;
@@ -3645,7 +3708,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3645,7 +3708,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3645 rn = "Config1"; 3708 rn = "Config1";
3646 break; 3709 break;
3647 case 2: 3710 case 2:
3648 - tcg_gen_helper_0_0(do_mtc0_config2); 3711 + tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]);
3649 rn = "Config2"; 3712 rn = "Config2";
3650 /* Stop translation as we may have switched the execution mode */ 3713 /* Stop translation as we may have switched the execution mode */
3651 ctx->bstate = BS_STOP; 3714 ctx->bstate = BS_STOP;
@@ -3682,7 +3745,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3682,7 +3745,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3682 case 18: 3745 case 18:
3683 switch (sel) { 3746 switch (sel) {
3684 case 0 ... 7: 3747 case 0 ... 7:
3685 - tcg_gen_helper_0_1i(do_mtc0_watchlo, sel); 3748 + tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel);
3686 rn = "WatchLo"; 3749 rn = "WatchLo";
3687 break; 3750 break;
3688 default: 3751 default:
@@ -3692,7 +3755,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3692,7 +3755,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3692 case 19: 3755 case 19:
3693 switch (sel) { 3756 switch (sel) {
3694 case 0 ... 7: 3757 case 0 ... 7:
3695 - tcg_gen_helper_0_1i(do_mtc0_watchhi, sel); 3758 + tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel);
3696 rn = "WatchHi"; 3759 rn = "WatchHi";
3697 break; 3760 break;
3698 default: 3761 default:
@@ -3704,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3704,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3704 case 0: 3767 case 0:
3705 #if defined(TARGET_MIPS64) 3768 #if defined(TARGET_MIPS64)
3706 check_insn(env, ctx, ISA_MIPS3); 3769 check_insn(env, ctx, ISA_MIPS3);
3707 - tcg_gen_helper_0_0(do_mtc0_xcontext); 3770 + tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]);
3708 rn = "XContext"; 3771 rn = "XContext";
3709 break; 3772 break;
3710 #endif 3773 #endif
@@ -3716,7 +3779,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3716,7 +3779,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3716 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 3779 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3717 switch (sel) { 3780 switch (sel) {
3718 case 0: 3781 case 0:
3719 - tcg_gen_helper_0_0(do_mtc0_framemask); 3782 + tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]);
3720 rn = "Framemask"; 3783 rn = "Framemask";
3721 break; 3784 break;
3722 default: 3785 default:
@@ -3730,20 +3793,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3730,20 +3793,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3730 case 23: 3793 case 23:
3731 switch (sel) { 3794 switch (sel) {
3732 case 0: 3795 case 0:
3733 - tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */ 3796 + tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */
3734 /* BS_STOP isn't good enough here, hflags may have changed. */ 3797 /* BS_STOP isn't good enough here, hflags may have changed. */
3735 gen_save_pc(ctx->pc + 4); 3798 gen_save_pc(ctx->pc + 4);
3736 ctx->bstate = BS_EXCP; 3799 ctx->bstate = BS_EXCP;
3737 rn = "Debug"; 3800 rn = "Debug";
3738 break; 3801 break;
3739 case 1: 3802 case 1:
3740 -// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */ 3803 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */
3741 rn = "TraceControl"; 3804 rn = "TraceControl";
3742 /* Stop translation as we may have switched the execution mode */ 3805 /* Stop translation as we may have switched the execution mode */
3743 ctx->bstate = BS_STOP; 3806 ctx->bstate = BS_STOP;
3744 // break; 3807 // break;
3745 case 2: 3808 case 2:
3746 -// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */ 3809 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */
3747 rn = "TraceControl2"; 3810 rn = "TraceControl2";
3748 /* Stop translation as we may have switched the execution mode */ 3811 /* Stop translation as we may have switched the execution mode */
3749 ctx->bstate = BS_STOP; 3812 ctx->bstate = BS_STOP;
@@ -3751,13 +3814,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3751,13 +3814,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3751 case 3: 3814 case 3:
3752 /* Stop translation as we may have switched the execution mode */ 3815 /* Stop translation as we may have switched the execution mode */
3753 ctx->bstate = BS_STOP; 3816 ctx->bstate = BS_STOP;
3754 -// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */ 3817 +// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */
3755 rn = "UserTraceData"; 3818 rn = "UserTraceData";
3756 /* Stop translation as we may have switched the execution mode */ 3819 /* Stop translation as we may have switched the execution mode */
3757 ctx->bstate = BS_STOP; 3820 ctx->bstate = BS_STOP;
3758 // break; 3821 // break;
3759 case 4: 3822 case 4:
3760 -// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */ 3823 +// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */
3761 /* Stop translation as we may have switched the execution mode */ 3824 /* Stop translation as we may have switched the execution mode */
3762 ctx->bstate = BS_STOP; 3825 ctx->bstate = BS_STOP;
3763 rn = "TraceBPC"; 3826 rn = "TraceBPC";
@@ -3780,35 +3843,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3780,35 +3843,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3780 case 25: 3843 case 25:
3781 switch (sel) { 3844 switch (sel) {
3782 case 0: 3845 case 0:
3783 - tcg_gen_helper_0_0(do_mtc0_performance0); 3846 + tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]);
3784 rn = "Performance0"; 3847 rn = "Performance0";
3785 break; 3848 break;
3786 case 1: 3849 case 1:
3787 -// tcg_gen_helper_0_0(do_mtc0_performance1); 3850 +// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]);
3788 rn = "Performance1"; 3851 rn = "Performance1";
3789 // break; 3852 // break;
3790 case 2: 3853 case 2:
3791 -// tcg_gen_helper_0_0(do_mtc0_performance2); 3854 +// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]);
3792 rn = "Performance2"; 3855 rn = "Performance2";
3793 // break; 3856 // break;
3794 case 3: 3857 case 3:
3795 -// tcg_gen_helper_0_0(do_mtc0_performance3); 3858 +// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]);
3796 rn = "Performance3"; 3859 rn = "Performance3";
3797 // break; 3860 // break;
3798 case 4: 3861 case 4:
3799 -// tcg_gen_helper_0_0(do_mtc0_performance4); 3862 +// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]);
3800 rn = "Performance4"; 3863 rn = "Performance4";
3801 // break; 3864 // break;
3802 case 5: 3865 case 5:
3803 -// tcg_gen_helper_0_0(do_mtc0_performance5); 3866 +// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]);
3804 rn = "Performance5"; 3867 rn = "Performance5";
3805 // break; 3868 // break;
3806 case 6: 3869 case 6:
3807 -// tcg_gen_helper_0_0(do_mtc0_performance6); 3870 +// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]);
3808 rn = "Performance6"; 3871 rn = "Performance6";
3809 // break; 3872 // break;
3810 case 7: 3873 case 7:
3811 -// tcg_gen_helper_0_0(do_mtc0_performance7); 3874 +// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]);
3812 rn = "Performance7"; 3875 rn = "Performance7";
3813 // break; 3876 // break;
3814 default: 3877 default:
@@ -3835,14 +3898,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3835,14 +3898,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3835 case 2: 3898 case 2:
3836 case 4: 3899 case 4:
3837 case 6: 3900 case 6:
3838 - tcg_gen_helper_0_0(do_mtc0_taglo); 3901 + tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]);
3839 rn = "TagLo"; 3902 rn = "TagLo";
3840 break; 3903 break;
3841 case 1: 3904 case 1:
3842 case 3: 3905 case 3:
3843 case 5: 3906 case 5:
3844 case 7: 3907 case 7:
3845 - tcg_gen_helper_0_0(do_mtc0_datalo); 3908 + tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]);
3846 rn = "DataLo"; 3909 rn = "DataLo";
3847 break; 3910 break;
3848 default: 3911 default:
@@ -3855,14 +3918,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3855,14 +3918,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3855 case 2: 3918 case 2:
3856 case 4: 3919 case 4:
3857 case 6: 3920 case 6:
3858 - tcg_gen_helper_0_0(do_mtc0_taghi); 3921 + tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]);
3859 rn = "TagHi"; 3922 rn = "TagHi";
3860 break; 3923 break;
3861 case 1: 3924 case 1:
3862 case 3: 3925 case 3:
3863 case 5: 3926 case 5:
3864 case 7: 3927 case 7:
3865 - tcg_gen_helper_0_0(do_mtc0_datahi); 3928 + tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]);
3866 rn = "DataHi"; 3929 rn = "DataHi";
3867 break; 3930 break;
3868 default: 3931 default:
@@ -3931,17 +3994,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3931,17 +3994,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3931 break; 3994 break;
3932 case 1: 3995 case 1:
3933 check_insn(env, ctx, ASE_MT); 3996 check_insn(env, ctx, ASE_MT);
3934 - tcg_gen_helper_0_0(do_mfc0_mvpcontrol); 3997 + tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]);
3935 rn = "MVPControl"; 3998 rn = "MVPControl";
3936 break; 3999 break;
3937 case 2: 4000 case 2:
3938 check_insn(env, ctx, ASE_MT); 4001 check_insn(env, ctx, ASE_MT);
3939 - tcg_gen_helper_0_0(do_mfc0_mvpconf0); 4002 + tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]);
3940 rn = "MVPConf0"; 4003 rn = "MVPConf0";
3941 break; 4004 break;
3942 case 3: 4005 case 3:
3943 check_insn(env, ctx, ASE_MT); 4006 check_insn(env, ctx, ASE_MT);
3944 - tcg_gen_helper_0_0(do_mfc0_mvpconf1); 4007 + tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]);
3945 rn = "MVPConf1"; 4008 rn = "MVPConf1";
3946 break; 4009 break;
3947 default: 4010 default:
@@ -3951,7 +4014,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3951,7 +4014,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3951 case 1: 4014 case 1:
3952 switch (sel) { 4015 switch (sel) {
3953 case 0: 4016 case 0:
3954 - tcg_gen_helper_0_0(do_mfc0_random); 4017 + tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]);
3955 rn = "Random"; 4018 rn = "Random";
3956 break; 4019 break;
3957 case 1: 4020 case 1:
@@ -4001,37 +4064,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4001,37 +4064,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4001 break; 4064 break;
4002 case 1: 4065 case 1:
4003 check_insn(env, ctx, ASE_MT); 4066 check_insn(env, ctx, ASE_MT);
4004 - tcg_gen_helper_0_0(do_mfc0_tcstatus); 4067 + tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]);
4005 rn = "TCStatus"; 4068 rn = "TCStatus";
4006 break; 4069 break;
4007 case 2: 4070 case 2:
4008 check_insn(env, ctx, ASE_MT); 4071 check_insn(env, ctx, ASE_MT);
4009 - tcg_gen_helper_0_0(do_mfc0_tcbind); 4072 + tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]);
4010 rn = "TCBind"; 4073 rn = "TCBind";
4011 break; 4074 break;
4012 case 3: 4075 case 3:
4013 check_insn(env, ctx, ASE_MT); 4076 check_insn(env, ctx, ASE_MT);
4014 - tcg_gen_helper_0_0(do_dmfc0_tcrestart); 4077 + tcg_gen_helper_1_1(do_dmfc0_tcrestart, cpu_T[0], cpu_T[0]);
4015 rn = "TCRestart"; 4078 rn = "TCRestart";
4016 break; 4079 break;
4017 case 4: 4080 case 4:
4018 check_insn(env, ctx, ASE_MT); 4081 check_insn(env, ctx, ASE_MT);
4019 - tcg_gen_helper_0_0(do_dmfc0_tchalt); 4082 + tcg_gen_helper_1_1(do_dmfc0_tchalt, cpu_T[0], cpu_T[0]);
4020 rn = "TCHalt"; 4083 rn = "TCHalt";
4021 break; 4084 break;
4022 case 5: 4085 case 5:
4023 check_insn(env, ctx, ASE_MT); 4086 check_insn(env, ctx, ASE_MT);
4024 - tcg_gen_helper_0_0(do_dmfc0_tccontext); 4087 + tcg_gen_helper_1_1(do_dmfc0_tccontext, cpu_T[0], cpu_T[0]);
4025 rn = "TCContext"; 4088 rn = "TCContext";
4026 break; 4089 break;
4027 case 6: 4090 case 6:
4028 check_insn(env, ctx, ASE_MT); 4091 check_insn(env, ctx, ASE_MT);
4029 - tcg_gen_helper_0_0(do_dmfc0_tcschedule); 4092 + tcg_gen_helper_1_1(do_dmfc0_tcschedule, cpu_T[0], cpu_T[0]);
4030 rn = "TCSchedule"; 4093 rn = "TCSchedule";
4031 break; 4094 break;
4032 case 7: 4095 case 7:
4033 check_insn(env, ctx, ASE_MT); 4096 check_insn(env, ctx, ASE_MT);
4034 - tcg_gen_helper_0_0(do_dmfc0_tcschefback); 4097 + tcg_gen_helper_1_1(do_dmfc0_tcschefback, cpu_T[0], cpu_T[0]);
4035 rn = "TCScheFBack"; 4098 rn = "TCScheFBack";
4036 break; 4099 break;
4037 default: 4100 default:
@@ -4055,7 +4118,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4055,7 +4118,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4055 rn = "Context"; 4118 rn = "Context";
4056 break; 4119 break;
4057 case 1: 4120 case 1:
4058 -// tcg_gen_helper_0_0(do_dmfc0_contextconfig); /* SmartMIPS ASE */ 4121 +// tcg_gen_helper_1_1(do_dmfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */
4059 rn = "ContextConfig"; 4122 rn = "ContextConfig";
4060 // break; 4123 // break;
4061 default: 4124 default:
@@ -4136,7 +4199,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4136,7 +4199,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4136 case 9: 4199 case 9:
4137 switch (sel) { 4200 switch (sel) {
4138 case 0: 4201 case 0:
4139 - tcg_gen_helper_0_0(do_mfc0_count); 4202 + tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]);
4140 rn = "Count"; 4203 rn = "Count";
4141 break; 4204 break;
4142 /* 6,7 are implementation dependent */ 4205 /* 6,7 are implementation dependent */
@@ -4259,7 +4322,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4259,7 +4322,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4259 case 17: 4322 case 17:
4260 switch (sel) { 4323 switch (sel) {
4261 case 0: 4324 case 0:
4262 - tcg_gen_helper_0_0(do_dmfc0_lladdr); 4325 + tcg_gen_helper_1_1(do_dmfc0_lladdr, cpu_T[0], cpu_T[0]);
4263 rn = "LLAddr"; 4326 rn = "LLAddr";
4264 break; 4327 break;
4265 default: 4328 default:
@@ -4269,7 +4332,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4269,7 +4332,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4269 case 18: 4332 case 18:
4270 switch (sel) { 4333 switch (sel) {
4271 case 0 ... 7: 4334 case 0 ... 7:
4272 - tcg_gen_helper_0_1i(do_dmfc0_watchlo, sel); 4335 + tcg_gen_helper_1_1i(do_dmfc0_watchlo, cpu_T[0], cpu_T[0], sel);
4273 rn = "WatchLo"; 4336 rn = "WatchLo";
4274 break; 4337 break;
4275 default: 4338 default:
@@ -4279,7 +4342,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4279,7 +4342,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4279 case 19: 4342 case 19:
4280 switch (sel) { 4343 switch (sel) {
4281 case 0 ... 7: 4344 case 0 ... 7:
4282 - tcg_gen_helper_0_1i(do_mfc0_watchhi, sel); 4345 + tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel);
4283 rn = "WatchHi"; 4346 rn = "WatchHi";
4284 break; 4347 break;
4285 default: 4348 default:
@@ -4315,23 +4378,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4315,23 +4378,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4315 case 23: 4378 case 23:
4316 switch (sel) { 4379 switch (sel) {
4317 case 0: 4380 case 0:
4318 - tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */ 4381 + tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */
4319 rn = "Debug"; 4382 rn = "Debug";
4320 break; 4383 break;
4321 case 1: 4384 case 1:
4322 -// tcg_gen_helper_0_0(do_dmfc0_tracecontrol); /* PDtrace support */ 4385 +// tcg_gen_helper_1_1(do_dmfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */
4323 rn = "TraceControl"; 4386 rn = "TraceControl";
4324 // break; 4387 // break;
4325 case 2: 4388 case 2:
4326 -// tcg_gen_helper_0_0(do_dmfc0_tracecontrol2); /* PDtrace support */ 4389 +// tcg_gen_helper_1_1(do_dmfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */
4327 rn = "TraceControl2"; 4390 rn = "TraceControl2";
4328 // break; 4391 // break;
4329 case 3: 4392 case 3:
4330 -// tcg_gen_helper_0_0(do_dmfc0_usertracedata); /* PDtrace support */ 4393 +// tcg_gen_helper_1_1(do_dmfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */
4331 rn = "UserTraceData"; 4394 rn = "UserTraceData";
4332 // break; 4395 // break;
4333 case 4: 4396 case 4:
4334 -// tcg_gen_helper_0_0(do_dmfc0_debug); /* PDtrace support */ 4397 +// tcg_gen_helper_1_1(do_dmfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */
4335 rn = "TraceBPC"; 4398 rn = "TraceBPC";
4336 // break; 4399 // break;
4337 default: 4400 default:
@@ -4356,31 +4419,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4356,31 +4419,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4356 rn = "Performance0"; 4419 rn = "Performance0";
4357 break; 4420 break;
4358 case 1: 4421 case 1:
4359 -// tcg_gen_helper_0_0(do_dmfc0_performance1); 4422 +// tcg_gen_helper_1_1(do_dmfc0_performance1, cpu_T[0], cpu_T[0]);
4360 rn = "Performance1"; 4423 rn = "Performance1";
4361 // break; 4424 // break;
4362 case 2: 4425 case 2:
4363 -// tcg_gen_helper_0_0(do_dmfc0_performance2); 4426 +// tcg_gen_helper_1_1(do_dmfc0_performance2, cpu_T[0], cpu_T[0]);
4364 rn = "Performance2"; 4427 rn = "Performance2";
4365 // break; 4428 // break;
4366 case 3: 4429 case 3:
4367 -// tcg_gen_helper_0_0(do_dmfc0_performance3); 4430 +// tcg_gen_helper_1_1(do_dmfc0_performance3, cpu_T[0], cpu_T[0]);
4368 rn = "Performance3"; 4431 rn = "Performance3";
4369 // break; 4432 // break;
4370 case 4: 4433 case 4:
4371 -// tcg_gen_helper_0_0(do_dmfc0_performance4); 4434 +// tcg_gen_helper_1_1(do_dmfc0_performance4, cpu_T[0], cpu_T[0]);
4372 rn = "Performance4"; 4435 rn = "Performance4";
4373 // break; 4436 // break;
4374 case 5: 4437 case 5:
4375 -// tcg_gen_helper_0_0(do_dmfc0_performance5); 4438 +// tcg_gen_helper_1_1(do_dmfc0_performance5, cpu_T[0], cpu_T[0]);
4376 rn = "Performance5"; 4439 rn = "Performance5";
4377 // break; 4440 // break;
4378 case 6: 4441 case 6:
4379 -// tcg_gen_helper_0_0(do_dmfc0_performance6); 4442 +// tcg_gen_helper_1_1(do_dmfc0_performance6, cpu_T[0], cpu_T[0]);
4380 rn = "Performance6"; 4443 rn = "Performance6";
4381 // break; 4444 // break;
4382 case 7: 4445 case 7:
4383 -// tcg_gen_helper_0_0(do_dmfc0_performance7); 4446 +// tcg_gen_helper_1_1(do_dmfc0_performance7, cpu_T[0], cpu_T[0]);
4384 rn = "Performance7"; 4447 rn = "Performance7";
4385 // break; 4448 // break;
4386 default: 4449 default:
@@ -4493,12 +4556,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4493,12 +4556,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4493 case 0: 4556 case 0:
4494 switch (sel) { 4557 switch (sel) {
4495 case 0: 4558 case 0:
4496 - tcg_gen_helper_0_0(do_mtc0_index); 4559 + tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]);
4497 rn = "Index"; 4560 rn = "Index";
4498 break; 4561 break;
4499 case 1: 4562 case 1:
4500 check_insn(env, ctx, ASE_MT); 4563 check_insn(env, ctx, ASE_MT);
4501 - tcg_gen_helper_0_0(do_mtc0_mvpcontrol); 4564 + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]);
4502 rn = "MVPControl"; 4565 rn = "MVPControl";
4503 break; 4566 break;
4504 case 2: 4567 case 2:
@@ -4523,22 +4586,22 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4523,22 +4586,22 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4523 break; 4586 break;
4524 case 1: 4587 case 1:
4525 check_insn(env, ctx, ASE_MT); 4588 check_insn(env, ctx, ASE_MT);
4526 - tcg_gen_helper_0_0(do_mtc0_vpecontrol); 4589 + tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]);
4527 rn = "VPEControl"; 4590 rn = "VPEControl";
4528 break; 4591 break;
4529 case 2: 4592 case 2:
4530 check_insn(env, ctx, ASE_MT); 4593 check_insn(env, ctx, ASE_MT);
4531 - tcg_gen_helper_0_0(do_mtc0_vpeconf0); 4594 + tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]);
4532 rn = "VPEConf0"; 4595 rn = "VPEConf0";
4533 break; 4596 break;
4534 case 3: 4597 case 3:
4535 check_insn(env, ctx, ASE_MT); 4598 check_insn(env, ctx, ASE_MT);
4536 - tcg_gen_helper_0_0(do_mtc0_vpeconf1); 4599 + tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]);
4537 rn = "VPEConf1"; 4600 rn = "VPEConf1";
4538 break; 4601 break;
4539 case 4: 4602 case 4:
4540 check_insn(env, ctx, ASE_MT); 4603 check_insn(env, ctx, ASE_MT);
4541 - tcg_gen_helper_0_0(do_mtc0_yqmask); 4604 + tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]);
4542 rn = "YQMask"; 4605 rn = "YQMask";
4543 break; 4606 break;
4544 case 5: 4607 case 5:
@@ -4553,7 +4616,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4553,7 +4616,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4553 break; 4616 break;
4554 case 7: 4617 case 7:
4555 check_insn(env, ctx, ASE_MT); 4618 check_insn(env, ctx, ASE_MT);
4556 - tcg_gen_helper_0_0(do_mtc0_vpeopt); 4619 + tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]);
4557 rn = "VPEOpt"; 4620 rn = "VPEOpt";
4558 break; 4621 break;
4559 default: 4622 default:
@@ -4563,42 +4626,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4563,42 +4626,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4563 case 2: 4626 case 2:
4564 switch (sel) { 4627 switch (sel) {
4565 case 0: 4628 case 0:
4566 - tcg_gen_helper_0_0(do_mtc0_entrylo0); 4629 + tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]);
4567 rn = "EntryLo0"; 4630 rn = "EntryLo0";
4568 break; 4631 break;
4569 case 1: 4632 case 1:
4570 check_insn(env, ctx, ASE_MT); 4633 check_insn(env, ctx, ASE_MT);
4571 - tcg_gen_helper_0_0(do_mtc0_tcstatus); 4634 + tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]);
4572 rn = "TCStatus"; 4635 rn = "TCStatus";
4573 break; 4636 break;
4574 case 2: 4637 case 2:
4575 check_insn(env, ctx, ASE_MT); 4638 check_insn(env, ctx, ASE_MT);
4576 - tcg_gen_helper_0_0(do_mtc0_tcbind); 4639 + tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]);
4577 rn = "TCBind"; 4640 rn = "TCBind";
4578 break; 4641 break;
4579 case 3: 4642 case 3:
4580 check_insn(env, ctx, ASE_MT); 4643 check_insn(env, ctx, ASE_MT);
4581 - tcg_gen_helper_0_0(do_mtc0_tcrestart); 4644 + tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]);
4582 rn = "TCRestart"; 4645 rn = "TCRestart";
4583 break; 4646 break;
4584 case 4: 4647 case 4:
4585 check_insn(env, ctx, ASE_MT); 4648 check_insn(env, ctx, ASE_MT);
4586 - tcg_gen_helper_0_0(do_mtc0_tchalt); 4649 + tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]);
4587 rn = "TCHalt"; 4650 rn = "TCHalt";
4588 break; 4651 break;
4589 case 5: 4652 case 5:
4590 check_insn(env, ctx, ASE_MT); 4653 check_insn(env, ctx, ASE_MT);
4591 - tcg_gen_helper_0_0(do_mtc0_tccontext); 4654 + tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]);
4592 rn = "TCContext"; 4655 rn = "TCContext";
4593 break; 4656 break;
4594 case 6: 4657 case 6:
4595 check_insn(env, ctx, ASE_MT); 4658 check_insn(env, ctx, ASE_MT);
4596 - tcg_gen_helper_0_0(do_mtc0_tcschedule); 4659 + tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]);
4597 rn = "TCSchedule"; 4660 rn = "TCSchedule";
4598 break; 4661 break;
4599 case 7: 4662 case 7:
4600 check_insn(env, ctx, ASE_MT); 4663 check_insn(env, ctx, ASE_MT);
4601 - tcg_gen_helper_0_0(do_mtc0_tcschefback); 4664 + tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]);
4602 rn = "TCScheFBack"; 4665 rn = "TCScheFBack";
4603 break; 4666 break;
4604 default: 4667 default:
@@ -4608,7 +4671,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4608,7 +4671,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4608 case 3: 4671 case 3:
4609 switch (sel) { 4672 switch (sel) {
4610 case 0: 4673 case 0:
4611 - tcg_gen_helper_0_0(do_mtc0_entrylo1); 4674 + tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]);
4612 rn = "EntryLo1"; 4675 rn = "EntryLo1";
4613 break; 4676 break;
4614 default: 4677 default:
@@ -4618,11 +4681,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4618,11 +4681,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4618 case 4: 4681 case 4:
4619 switch (sel) { 4682 switch (sel) {
4620 case 0: 4683 case 0:
4621 - tcg_gen_helper_0_0(do_mtc0_context); 4684 + tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]);
4622 rn = "Context"; 4685 rn = "Context";
4623 break; 4686 break;
4624 case 1: 4687 case 1:
4625 -// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */ 4688 +// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */
4626 rn = "ContextConfig"; 4689 rn = "ContextConfig";
4627 // break; 4690 // break;
4628 default: 4691 default:
@@ -4632,12 +4695,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4632,12 +4695,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4632 case 5: 4695 case 5:
4633 switch (sel) { 4696 switch (sel) {
4634 case 0: 4697 case 0:
4635 - tcg_gen_helper_0_0(do_mtc0_pagemask); 4698 + tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]);
4636 rn = "PageMask"; 4699 rn = "PageMask";
4637 break; 4700 break;
4638 case 1: 4701 case 1:
4639 check_insn(env, ctx, ISA_MIPS32R2); 4702 check_insn(env, ctx, ISA_MIPS32R2);
4640 - tcg_gen_helper_0_0(do_mtc0_pagegrain); 4703 + tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]);
4641 rn = "PageGrain"; 4704 rn = "PageGrain";
4642 break; 4705 break;
4643 default: 4706 default:
@@ -4647,32 +4710,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4647,32 +4710,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4647 case 6: 4710 case 6:
4648 switch (sel) { 4711 switch (sel) {
4649 case 0: 4712 case 0:
4650 - tcg_gen_helper_0_0(do_mtc0_wired); 4713 + tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]);
4651 rn = "Wired"; 4714 rn = "Wired";
4652 break; 4715 break;
4653 case 1: 4716 case 1:
4654 check_insn(env, ctx, ISA_MIPS32R2); 4717 check_insn(env, ctx, ISA_MIPS32R2);
4655 - tcg_gen_helper_0_0(do_mtc0_srsconf0); 4718 + tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]);
4656 rn = "SRSConf0"; 4719 rn = "SRSConf0";
4657 break; 4720 break;
4658 case 2: 4721 case 2:
4659 check_insn(env, ctx, ISA_MIPS32R2); 4722 check_insn(env, ctx, ISA_MIPS32R2);
4660 - tcg_gen_helper_0_0(do_mtc0_srsconf1); 4723 + tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]);
4661 rn = "SRSConf1"; 4724 rn = "SRSConf1";
4662 break; 4725 break;
4663 case 3: 4726 case 3:
4664 check_insn(env, ctx, ISA_MIPS32R2); 4727 check_insn(env, ctx, ISA_MIPS32R2);
4665 - tcg_gen_helper_0_0(do_mtc0_srsconf2); 4728 + tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]);
4666 rn = "SRSConf2"; 4729 rn = "SRSConf2";
4667 break; 4730 break;
4668 case 4: 4731 case 4:
4669 check_insn(env, ctx, ISA_MIPS32R2); 4732 check_insn(env, ctx, ISA_MIPS32R2);
4670 - tcg_gen_helper_0_0(do_mtc0_srsconf3); 4733 + tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]);
4671 rn = "SRSConf3"; 4734 rn = "SRSConf3";
4672 break; 4735 break;
4673 case 5: 4736 case 5:
4674 check_insn(env, ctx, ISA_MIPS32R2); 4737 check_insn(env, ctx, ISA_MIPS32R2);
4675 - tcg_gen_helper_0_0(do_mtc0_srsconf4); 4738 + tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]);
4676 rn = "SRSConf4"; 4739 rn = "SRSConf4";
4677 break; 4740 break;
4678 default: 4741 default:
@@ -4683,7 +4746,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4683,7 +4746,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4683 switch (sel) { 4746 switch (sel) {
4684 case 0: 4747 case 0:
4685 check_insn(env, ctx, ISA_MIPS32R2); 4748 check_insn(env, ctx, ISA_MIPS32R2);
4686 - tcg_gen_helper_0_0(do_mtc0_hwrena); 4749 + tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]);
4687 rn = "HWREna"; 4750 rn = "HWREna";
4688 break; 4751 break;
4689 default: 4752 default:
@@ -4697,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4697,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4697 case 9: 4760 case 9:
4698 switch (sel) { 4761 switch (sel) {
4699 case 0: 4762 case 0:
4700 - tcg_gen_helper_0_0(do_mtc0_count); 4763 + tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]);
4701 rn = "Count"; 4764 rn = "Count";
4702 break; 4765 break;
4703 /* 6,7 are implementation dependent */ 4766 /* 6,7 are implementation dependent */
@@ -4710,7 +4773,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4710,7 +4773,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4710 case 10: 4773 case 10:
4711 switch (sel) { 4774 switch (sel) {
4712 case 0: 4775 case 0:
4713 - tcg_gen_helper_0_0(do_mtc0_entryhi); 4776 + tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]);
4714 rn = "EntryHi"; 4777 rn = "EntryHi";
4715 break; 4778 break;
4716 default: 4779 default:
@@ -4720,7 +4783,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4720,7 +4783,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4720 case 11: 4783 case 11:
4721 switch (sel) { 4784 switch (sel) {
4722 case 0: 4785 case 0:
4723 - tcg_gen_helper_0_0(do_mtc0_compare); 4786 + tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]);
4724 rn = "Compare"; 4787 rn = "Compare";
4725 break; 4788 break;
4726 /* 6,7 are implementation dependent */ 4789 /* 6,7 are implementation dependent */
@@ -4733,7 +4796,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4733,7 +4796,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4733 case 12: 4796 case 12:
4734 switch (sel) { 4797 switch (sel) {
4735 case 0: 4798 case 0:
4736 - tcg_gen_helper_0_0(do_mtc0_status); 4799 + tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]);
4737 /* BS_STOP isn't good enough here, hflags may have changed. */ 4800 /* BS_STOP isn't good enough here, hflags may have changed. */
4738 gen_save_pc(ctx->pc + 4); 4801 gen_save_pc(ctx->pc + 4);
4739 ctx->bstate = BS_EXCP; 4802 ctx->bstate = BS_EXCP;
@@ -4741,14 +4804,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4741,14 +4804,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4741 break; 4804 break;
4742 case 1: 4805 case 1:
4743 check_insn(env, ctx, ISA_MIPS32R2); 4806 check_insn(env, ctx, ISA_MIPS32R2);
4744 - tcg_gen_helper_0_0(do_mtc0_intctl); 4807 + tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]);
4745 /* Stop translation as we may have switched the execution mode */ 4808 /* Stop translation as we may have switched the execution mode */
4746 ctx->bstate = BS_STOP; 4809 ctx->bstate = BS_STOP;
4747 rn = "IntCtl"; 4810 rn = "IntCtl";
4748 break; 4811 break;
4749 case 2: 4812 case 2:
4750 check_insn(env, ctx, ISA_MIPS32R2); 4813 check_insn(env, ctx, ISA_MIPS32R2);
4751 - tcg_gen_helper_0_0(do_mtc0_srsctl); 4814 + tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]);
4752 /* Stop translation as we may have switched the execution mode */ 4815 /* Stop translation as we may have switched the execution mode */
4753 ctx->bstate = BS_STOP; 4816 ctx->bstate = BS_STOP;
4754 rn = "SRSCtl"; 4817 rn = "SRSCtl";
@@ -4767,7 +4830,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4767,7 +4830,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4767 case 13: 4830 case 13:
4768 switch (sel) { 4831 switch (sel) {
4769 case 0: 4832 case 0:
4770 - tcg_gen_helper_0_0(do_mtc0_cause); 4833 + tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]);
4771 rn = "Cause"; 4834 rn = "Cause";
4772 break; 4835 break;
4773 default: 4836 default:
@@ -4794,7 +4857,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4794,7 +4857,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4794 break; 4857 break;
4795 case 1: 4858 case 1:
4796 check_insn(env, ctx, ISA_MIPS32R2); 4859 check_insn(env, ctx, ISA_MIPS32R2);
4797 - tcg_gen_helper_0_0(do_mtc0_ebase); 4860 + tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]);
4798 rn = "EBase"; 4861 rn = "EBase";
4799 break; 4862 break;
4800 default: 4863 default:
@@ -4804,7 +4867,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4804,7 +4867,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4804 case 16: 4867 case 16:
4805 switch (sel) { 4868 switch (sel) {
4806 case 0: 4869 case 0:
4807 - tcg_gen_helper_0_0(do_mtc0_config0); 4870 + tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]);
4808 rn = "Config"; 4871 rn = "Config";
4809 /* Stop translation as we may have switched the execution mode */ 4872 /* Stop translation as we may have switched the execution mode */
4810 ctx->bstate = BS_STOP; 4873 ctx->bstate = BS_STOP;
@@ -4814,7 +4877,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4814,7 +4877,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4814 rn = "Config1"; 4877 rn = "Config1";
4815 break; 4878 break;
4816 case 2: 4879 case 2:
4817 - tcg_gen_helper_0_0(do_mtc0_config2); 4880 + tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]);
4818 rn = "Config2"; 4881 rn = "Config2";
4819 /* Stop translation as we may have switched the execution mode */ 4882 /* Stop translation as we may have switched the execution mode */
4820 ctx->bstate = BS_STOP; 4883 ctx->bstate = BS_STOP;
@@ -4842,7 +4905,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4842,7 +4905,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4842 case 18: 4905 case 18:
4843 switch (sel) { 4906 switch (sel) {
4844 case 0 ... 7: 4907 case 0 ... 7:
4845 - tcg_gen_helper_0_1i(do_mtc0_watchlo, sel); 4908 + tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel);
4846 rn = "WatchLo"; 4909 rn = "WatchLo";
4847 break; 4910 break;
4848 default: 4911 default:
@@ -4852,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4852,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4852 case 19: 4915 case 19:
4853 switch (sel) { 4916 switch (sel) {
4854 case 0 ... 7: 4917 case 0 ... 7:
4855 - tcg_gen_helper_0_1i(do_mtc0_watchhi, sel); 4918 + tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel);
4856 rn = "WatchHi"; 4919 rn = "WatchHi";
4857 break; 4920 break;
4858 default: 4921 default:
@@ -4863,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4863,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4863 switch (sel) { 4926 switch (sel) {
4864 case 0: 4927 case 0:
4865 check_insn(env, ctx, ISA_MIPS3); 4928 check_insn(env, ctx, ISA_MIPS3);
4866 - tcg_gen_helper_0_0(do_mtc0_xcontext); 4929 + tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]);
4867 rn = "XContext"; 4930 rn = "XContext";
4868 break; 4931 break;
4869 default: 4932 default:
@@ -4874,7 +4937,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4874,7 +4937,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4874 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 4937 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4875 switch (sel) { 4938 switch (sel) {
4876 case 0: 4939 case 0:
4877 - tcg_gen_helper_0_0(do_mtc0_framemask); 4940 + tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]);
4878 rn = "Framemask"; 4941 rn = "Framemask";
4879 break; 4942 break;
4880 default: 4943 default:
@@ -4888,32 +4951,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4888,32 +4951,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4888 case 23: 4951 case 23:
4889 switch (sel) { 4952 switch (sel) {
4890 case 0: 4953 case 0:
4891 - tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */ 4954 + tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */
4892 /* BS_STOP isn't good enough here, hflags may have changed. */ 4955 /* BS_STOP isn't good enough here, hflags may have changed. */
4893 gen_save_pc(ctx->pc + 4); 4956 gen_save_pc(ctx->pc + 4);
4894 ctx->bstate = BS_EXCP; 4957 ctx->bstate = BS_EXCP;
4895 rn = "Debug"; 4958 rn = "Debug";
4896 break; 4959 break;
4897 case 1: 4960 case 1:
4898 -// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */ 4961 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */
4899 /* Stop translation as we may have switched the execution mode */ 4962 /* Stop translation as we may have switched the execution mode */
4900 ctx->bstate = BS_STOP; 4963 ctx->bstate = BS_STOP;
4901 rn = "TraceControl"; 4964 rn = "TraceControl";
4902 // break; 4965 // break;
4903 case 2: 4966 case 2:
4904 -// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */ 4967 +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */
4905 /* Stop translation as we may have switched the execution mode */ 4968 /* Stop translation as we may have switched the execution mode */
4906 ctx->bstate = BS_STOP; 4969 ctx->bstate = BS_STOP;
4907 rn = "TraceControl2"; 4970 rn = "TraceControl2";
4908 // break; 4971 // break;
4909 case 3: 4972 case 3:
4910 -// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */ 4973 +// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */
4911 /* Stop translation as we may have switched the execution mode */ 4974 /* Stop translation as we may have switched the execution mode */
4912 ctx->bstate = BS_STOP; 4975 ctx->bstate = BS_STOP;
4913 rn = "UserTraceData"; 4976 rn = "UserTraceData";
4914 // break; 4977 // break;
4915 case 4: 4978 case 4:
4916 -// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */ 4979 +// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */
4917 /* Stop translation as we may have switched the execution mode */ 4980 /* Stop translation as we may have switched the execution mode */
4918 ctx->bstate = BS_STOP; 4981 ctx->bstate = BS_STOP;
4919 rn = "TraceBPC"; 4982 rn = "TraceBPC";
@@ -4936,35 +4999,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4936,35 +4999,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4936 case 25: 4999 case 25:
4937 switch (sel) { 5000 switch (sel) {
4938 case 0: 5001 case 0:
4939 - tcg_gen_helper_0_0(do_mtc0_performance0); 5002 + tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]);
4940 rn = "Performance0"; 5003 rn = "Performance0";
4941 break; 5004 break;
4942 case 1: 5005 case 1:
4943 -// tcg_gen_helper_0_0(do_mtc0_performance1); 5006 +// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]);
4944 rn = "Performance1"; 5007 rn = "Performance1";
4945 // break; 5008 // break;
4946 case 2: 5009 case 2:
4947 -// tcg_gen_helper_0_0(do_mtc0_performance2); 5010 +// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]);
4948 rn = "Performance2"; 5011 rn = "Performance2";
4949 // break; 5012 // break;
4950 case 3: 5013 case 3:
4951 -// tcg_gen_helper_0_0(do_mtc0_performance3); 5014 +// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]);
4952 rn = "Performance3"; 5015 rn = "Performance3";
4953 // break; 5016 // break;
4954 case 4: 5017 case 4:
4955 -// tcg_gen_helper_0_0(do_mtc0_performance4); 5018 +// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]);
4956 rn = "Performance4"; 5019 rn = "Performance4";
4957 // break; 5020 // break;
4958 case 5: 5021 case 5:
4959 -// tcg_gen_helper_0_0(do_mtc0_performance5); 5022 +// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]);
4960 rn = "Performance5"; 5023 rn = "Performance5";
4961 // break; 5024 // break;
4962 case 6: 5025 case 6:
4963 -// tcg_gen_helper_0_0(do_mtc0_performance6); 5026 +// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]);
4964 rn = "Performance6"; 5027 rn = "Performance6";
4965 // break; 5028 // break;
4966 case 7: 5029 case 7:
4967 -// tcg_gen_helper_0_0(do_mtc0_performance7); 5030 +// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]);
4968 rn = "Performance7"; 5031 rn = "Performance7";
4969 // break; 5032 // break;
4970 default: 5033 default:
@@ -4991,14 +5054,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4991,14 +5054,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4991 case 2: 5054 case 2:
4992 case 4: 5055 case 4:
4993 case 6: 5056 case 6:
4994 - tcg_gen_helper_0_0(do_mtc0_taglo); 5057 + tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]);
4995 rn = "TagLo"; 5058 rn = "TagLo";
4996 break; 5059 break;
4997 case 1: 5060 case 1:
4998 case 3: 5061 case 3:
4999 case 5: 5062 case 5:
5000 case 7: 5063 case 7:
5001 - tcg_gen_helper_0_0(do_mtc0_datalo); 5064 + tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]);
5002 rn = "DataLo"; 5065 rn = "DataLo";
5003 break; 5066 break;
5004 default: 5067 default:
@@ -5011,14 +5074,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -5011,14 +5074,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
5011 case 2: 5074 case 2:
5012 case 4: 5075 case 4:
5013 case 6: 5076 case 6:
5014 - tcg_gen_helper_0_0(do_mtc0_taghi); 5077 + tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]);
5015 rn = "TagHi"; 5078 rn = "TagHi";
5016 break; 5079 break;
5017 case 1: 5080 case 1:
5018 case 3: 5081 case 3:
5019 case 5: 5082 case 5:
5020 case 7: 5083 case 7:
5021 - tcg_gen_helper_0_0(do_mtc0_datahi); 5084 + tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]);
5022 rn = "DataHi"; 5085 rn = "DataHi";
5023 break; 5086 break;
5024 default: 5087 default:
@@ -5088,25 +5151,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5088,25 +5151,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5088 case 2: 5151 case 2:
5089 switch (sel) { 5152 switch (sel) {
5090 case 1: 5153 case 1:
5091 - tcg_gen_helper_0_0(do_mftc0_tcstatus); 5154 + tcg_gen_helper_1_1(do_mftc0_tcstatus, cpu_T[0], cpu_T[0]);
5092 break; 5155 break;
5093 case 2: 5156 case 2:
5094 - tcg_gen_helper_0_0(do_mftc0_tcbind); 5157 + tcg_gen_helper_1_1(do_mftc0_tcbind, cpu_T[0], cpu_T[0]);
5095 break; 5158 break;
5096 case 3: 5159 case 3:
5097 - tcg_gen_helper_0_0(do_mftc0_tcrestart); 5160 + tcg_gen_helper_1_1(do_mftc0_tcrestart, cpu_T[0], cpu_T[0]);
5098 break; 5161 break;
5099 case 4: 5162 case 4:
5100 - tcg_gen_helper_0_0(do_mftc0_tchalt); 5163 + tcg_gen_helper_1_1(do_mftc0_tchalt, cpu_T[0], cpu_T[0]);
5101 break; 5164 break;
5102 case 5: 5165 case 5:
5103 - tcg_gen_helper_0_0(do_mftc0_tccontext); 5166 + tcg_gen_helper_1_1(do_mftc0_tccontext, cpu_T[0], cpu_T[0]);
5104 break; 5167 break;
5105 case 6: 5168 case 6:
5106 - tcg_gen_helper_0_0(do_mftc0_tcschedule); 5169 + tcg_gen_helper_1_1(do_mftc0_tcschedule, cpu_T[0], cpu_T[0]);
5107 break; 5170 break;
5108 case 7: 5171 case 7:
5109 - tcg_gen_helper_0_0(do_mftc0_tcschefback); 5172 + tcg_gen_helper_1_1(do_mftc0_tcschefback, cpu_T[0], cpu_T[0]);
5110 break; 5173 break;
5111 default: 5174 default:
5112 gen_mfc0(env, ctx, rt, sel); 5175 gen_mfc0(env, ctx, rt, sel);
@@ -5116,7 +5179,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5116,7 +5179,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5116 case 10: 5179 case 10:
5117 switch (sel) { 5180 switch (sel) {
5118 case 0: 5181 case 0:
5119 - tcg_gen_helper_0_0(do_mftc0_entryhi); 5182 + tcg_gen_helper_1_1(do_mftc0_entryhi, cpu_T[0], cpu_T[0]);
5120 break; 5183 break;
5121 default: 5184 default:
5122 gen_mfc0(env, ctx, rt, sel); 5185 gen_mfc0(env, ctx, rt, sel);
@@ -5125,7 +5188,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5125,7 +5188,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5125 case 12: 5188 case 12:
5126 switch (sel) { 5189 switch (sel) {
5127 case 0: 5190 case 0:
5128 - tcg_gen_helper_0_0(do_mftc0_status); 5191 + tcg_gen_helper_1_1(do_mftc0_status, cpu_T[0], cpu_T[0]);
5129 break; 5192 break;
5130 default: 5193 default:
5131 gen_mfc0(env, ctx, rt, sel); 5194 gen_mfc0(env, ctx, rt, sel);
@@ -5134,7 +5197,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5134,7 +5197,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5134 case 23: 5197 case 23:
5135 switch (sel) { 5198 switch (sel) {
5136 case 0: 5199 case 0:
5137 - tcg_gen_helper_0_0(do_mftc0_debug); 5200 + tcg_gen_helper_1_1(do_mftc0_debug, cpu_T[0], cpu_T[0]);
5138 break; 5201 break;
5139 default: 5202 default:
5140 gen_mfc0(env, ctx, rt, sel); 5203 gen_mfc0(env, ctx, rt, sel);
@@ -5147,49 +5210,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5147,49 +5210,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5147 } else switch (sel) { 5210 } else switch (sel) {
5148 /* GPR registers. */ 5211 /* GPR registers. */
5149 case 0: 5212 case 0:
5150 - tcg_gen_helper_0_1i(do_mftgpr, rt); 5213 + tcg_gen_helper_1_1i(do_mftgpr, cpu_T[0], cpu_T[0], rt);
5151 break; 5214 break;
5152 /* Auxiliary CPU registers */ 5215 /* Auxiliary CPU registers */
5153 case 1: 5216 case 1:
5154 switch (rt) { 5217 switch (rt) {
5155 case 0: 5218 case 0:
5156 - tcg_gen_helper_0_1i(do_mftlo, 0); 5219 + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 0);
5157 break; 5220 break;
5158 case 1: 5221 case 1:
5159 - tcg_gen_helper_0_1i(do_mfthi, 0); 5222 + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 0);
5160 break; 5223 break;
5161 case 2: 5224 case 2:
5162 - tcg_gen_helper_0_1i(do_mftacx, 0); 5225 + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 0);
5163 break; 5226 break;
5164 case 4: 5227 case 4:
5165 - tcg_gen_helper_0_1i(do_mftlo, 1); 5228 + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 1);
5166 break; 5229 break;
5167 case 5: 5230 case 5:
5168 - tcg_gen_helper_0_1i(do_mfthi, 1); 5231 + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 1);
5169 break; 5232 break;
5170 case 6: 5233 case 6:
5171 - tcg_gen_helper_0_1i(do_mftacx, 1); 5234 + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 1);
5172 break; 5235 break;
5173 case 8: 5236 case 8:
5174 - tcg_gen_helper_0_1i(do_mftlo, 2); 5237 + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 2);
5175 break; 5238 break;
5176 case 9: 5239 case 9:
5177 - tcg_gen_helper_0_1i(do_mfthi, 2); 5240 + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 2);
5178 break; 5241 break;
5179 case 10: 5242 case 10:
5180 - tcg_gen_helper_0_1i(do_mftacx, 2); 5243 + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 2);
5181 break; 5244 break;
5182 case 12: 5245 case 12:
5183 - tcg_gen_helper_0_1i(do_mftlo, 3); 5246 + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 3);
5184 break; 5247 break;
5185 case 13: 5248 case 13:
5186 - tcg_gen_helper_0_1i(do_mfthi, 3); 5249 + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 3);
5187 break; 5250 break;
5188 case 14: 5251 case 14:
5189 - tcg_gen_helper_0_1i(do_mftacx, 3); 5252 + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 3);
5190 break; 5253 break;
5191 case 16: 5254 case 16:
5192 - tcg_gen_helper_0_0(do_mftdsp); 5255 + tcg_gen_helper_1_1(do_mftdsp, cpu_T[0], cpu_T[0]);
5193 break; 5256 break;
5194 default: 5257 default:
5195 goto die; 5258 goto die;
@@ -5208,7 +5271,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5208,7 +5271,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5208 break; 5271 break;
5209 case 3: 5272 case 3:
5210 /* XXX: For now we support only a single FPU context. */ 5273 /* XXX: For now we support only a single FPU context. */
5211 - tcg_gen_helper_0_1i(do_cfc1, rt); 5274 + tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], rt);
5212 break; 5275 break;
5213 /* COP2: Not implemented. */ 5276 /* COP2: Not implemented. */
5214 case 4: 5277 case 4:
@@ -5252,25 +5315,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5252,25 +5315,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5252 case 2: 5315 case 2:
5253 switch (sel) { 5316 switch (sel) {
5254 case 1: 5317 case 1:
5255 - tcg_gen_helper_0_0(do_mttc0_tcstatus); 5318 + tcg_gen_helper_0_1(do_mttc0_tcstatus, cpu_T[0]);
5256 break; 5319 break;
5257 case 2: 5320 case 2:
5258 - tcg_gen_helper_0_0(do_mttc0_tcbind); 5321 + tcg_gen_helper_0_1(do_mttc0_tcbind, cpu_T[0]);
5259 break; 5322 break;
5260 case 3: 5323 case 3:
5261 - tcg_gen_helper_0_0(do_mttc0_tcrestart); 5324 + tcg_gen_helper_0_1(do_mttc0_tcrestart, cpu_T[0]);
5262 break; 5325 break;
5263 case 4: 5326 case 4:
5264 - tcg_gen_helper_0_0(do_mttc0_tchalt); 5327 + tcg_gen_helper_0_1(do_mttc0_tchalt, cpu_T[0]);
5265 break; 5328 break;
5266 case 5: 5329 case 5:
5267 - tcg_gen_helper_0_0(do_mttc0_tccontext); 5330 + tcg_gen_helper_0_1(do_mttc0_tccontext, cpu_T[0]);
5268 break; 5331 break;
5269 case 6: 5332 case 6:
5270 - tcg_gen_helper_0_0(do_mttc0_tcschedule); 5333 + tcg_gen_helper_0_1(do_mttc0_tcschedule, cpu_T[0]);
5271 break; 5334 break;
5272 case 7: 5335 case 7:
5273 - tcg_gen_helper_0_0(do_mttc0_tcschefback); 5336 + tcg_gen_helper_0_1(do_mttc0_tcschefback, cpu_T[0]);
5274 break; 5337 break;
5275 default: 5338 default:
5276 gen_mtc0(env, ctx, rd, sel); 5339 gen_mtc0(env, ctx, rd, sel);
@@ -5280,7 +5343,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5280,7 +5343,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5280 case 10: 5343 case 10:
5281 switch (sel) { 5344 switch (sel) {
5282 case 0: 5345 case 0:
5283 - tcg_gen_helper_0_0(do_mttc0_entryhi); 5346 + tcg_gen_helper_0_1(do_mttc0_entryhi, cpu_T[0]);
5284 break; 5347 break;
5285 default: 5348 default:
5286 gen_mtc0(env, ctx, rd, sel); 5349 gen_mtc0(env, ctx, rd, sel);
@@ -5289,7 +5352,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5289,7 +5352,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5289 case 12: 5352 case 12:
5290 switch (sel) { 5353 switch (sel) {
5291 case 0: 5354 case 0:
5292 - tcg_gen_helper_0_0(do_mttc0_status); 5355 + tcg_gen_helper_0_1(do_mttc0_status, cpu_T[0]);
5293 break; 5356 break;
5294 default: 5357 default:
5295 gen_mtc0(env, ctx, rd, sel); 5358 gen_mtc0(env, ctx, rd, sel);
@@ -5298,7 +5361,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5298,7 +5361,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5298 case 23: 5361 case 23:
5299 switch (sel) { 5362 switch (sel) {
5300 case 0: 5363 case 0:
5301 - tcg_gen_helper_0_0(do_mttc0_debug); 5364 + tcg_gen_helper_0_1(do_mttc0_debug, cpu_T[0]);
5302 break; 5365 break;
5303 default: 5366 default:
5304 gen_mtc0(env, ctx, rd, sel); 5367 gen_mtc0(env, ctx, rd, sel);
@@ -5311,49 +5374,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5311,49 +5374,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5311 } else switch (sel) { 5374 } else switch (sel) {
5312 /* GPR registers. */ 5375 /* GPR registers. */
5313 case 0: 5376 case 0:
5314 - tcg_gen_helper_0_1i(do_mttgpr, rd); 5377 + tcg_gen_helper_0_1i(do_mttgpr, cpu_T[0], rd);
5315 break; 5378 break;
5316 /* Auxiliary CPU registers */ 5379 /* Auxiliary CPU registers */
5317 case 1: 5380 case 1:
5318 switch (rd) { 5381 switch (rd) {
5319 case 0: 5382 case 0:
5320 - tcg_gen_helper_0_1i(do_mttlo, 0); 5383 + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 0);
5321 break; 5384 break;
5322 case 1: 5385 case 1:
5323 - tcg_gen_helper_0_1i(do_mtthi, 0); 5386 + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 0);
5324 break; 5387 break;
5325 case 2: 5388 case 2:
5326 - tcg_gen_helper_0_1i(do_mttacx, 0); 5389 + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 0);
5327 break; 5390 break;
5328 case 4: 5391 case 4:
5329 - tcg_gen_helper_0_1i(do_mttlo, 1); 5392 + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 1);
5330 break; 5393 break;
5331 case 5: 5394 case 5:
5332 - tcg_gen_helper_0_1i(do_mtthi, 1); 5395 + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 1);
5333 break; 5396 break;
5334 case 6: 5397 case 6:
5335 - tcg_gen_helper_0_1i(do_mttacx, 1); 5398 + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 1);
5336 break; 5399 break;
5337 case 8: 5400 case 8:
5338 - tcg_gen_helper_0_1i(do_mttlo, 2); 5401 + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 2);
5339 break; 5402 break;
5340 case 9: 5403 case 9:
5341 - tcg_gen_helper_0_1i(do_mtthi, 2); 5404 + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 2);
5342 break; 5405 break;
5343 case 10: 5406 case 10:
5344 - tcg_gen_helper_0_1i(do_mttacx, 2); 5407 + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 2);
5345 break; 5408 break;
5346 case 12: 5409 case 12:
5347 - tcg_gen_helper_0_1i(do_mttlo, 3); 5410 + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 3);
5348 break; 5411 break;
5349 case 13: 5412 case 13:
5350 - tcg_gen_helper_0_1i(do_mtthi, 3); 5413 + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 3);
5351 break; 5414 break;
5352 case 14: 5415 case 14:
5353 - tcg_gen_helper_0_1i(do_mttacx, 3); 5416 + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 3);
5354 break; 5417 break;
5355 case 16: 5418 case 16:
5356 - tcg_gen_helper_0_0(do_mttdsp); 5419 + tcg_gen_helper_0_1(do_mttdsp, cpu_T[0]);
5357 break; 5420 break;
5358 default: 5421 default:
5359 goto die; 5422 goto die;
@@ -5372,7 +5435,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5372,7 +5435,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5372 break; 5435 break;
5373 case 3: 5436 case 3:
5374 /* XXX: For now we support only a single FPU context. */ 5437 /* XXX: For now we support only a single FPU context. */
5375 - tcg_gen_helper_0_1i(do_ctc1, rd); 5438 + tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], rd);
5376 break; 5439 break;
5377 /* COP2: Not implemented. */ 5440 /* COP2: Not implemented. */
5378 case 4: 5441 case 4:
@@ -5484,7 +5547,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5484,7 +5547,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5484 opn = "eret"; 5547 opn = "eret";
5485 check_insn(env, ctx, ISA_MIPS2); 5548 check_insn(env, ctx, ISA_MIPS2);
5486 save_cpu_state(ctx, 1); 5549 save_cpu_state(ctx, 1);
5487 - tcg_gen_helper_0_0(do_eret); 5550 + tcg_gen_helper_0_1(do_eret, cpu_T[0]);
5488 ctx->bstate = BS_EXCP; 5551 ctx->bstate = BS_EXCP;
5489 break; 5552 break;
5490 case OPC_DERET: 5553 case OPC_DERET:
@@ -5495,7 +5558,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5495,7 +5558,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5495 generate_exception(ctx, EXCP_RI); 5558 generate_exception(ctx, EXCP_RI);
5496 } else { 5559 } else {
5497 save_cpu_state(ctx, 1); 5560 save_cpu_state(ctx, 1);
5498 - tcg_gen_helper_0_0(do_deret); 5561 + tcg_gen_helper_0_1(do_deret, cpu_T[0]);
5499 ctx->bstate = BS_EXCP; 5562 ctx->bstate = BS_EXCP;
5500 } 5563 }
5501 break; 5564 break;
@@ -5734,13 +5797,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) @@ -5734,13 +5797,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5734 opn = "mtc1"; 5797 opn = "mtc1";
5735 break; 5798 break;
5736 case OPC_CFC1: 5799 case OPC_CFC1:
5737 - tcg_gen_helper_0_1i(do_cfc1, fs); 5800 + tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], fs);
5738 gen_store_gpr(cpu_T[0], rt); 5801 gen_store_gpr(cpu_T[0], rt);
5739 opn = "cfc1"; 5802 opn = "cfc1";
5740 break; 5803 break;
5741 case OPC_CTC1: 5804 case OPC_CTC1:
5742 gen_load_gpr(cpu_T[0], rt); 5805 gen_load_gpr(cpu_T[0], rt);
5743 - tcg_gen_helper_0_1i(do_ctc1, fs); 5806 + tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], fs);
5744 opn = "ctc1"; 5807 opn = "ctc1";
5745 break; 5808 break;
5746 case OPC_DMFC1: 5809 case OPC_DMFC1:
@@ -6745,7 +6808,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, @@ -6745,7 +6808,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
6745 } else { 6808 } else {
6746 gen_load_gpr(cpu_T[0], base); 6809 gen_load_gpr(cpu_T[0], base);
6747 gen_load_gpr(cpu_T[1], index); 6810 gen_load_gpr(cpu_T[1], index);
6748 - gen_op_addr_add(); 6811 + gen_op_addr_add(cpu_T[0], cpu_T[1]);
6749 } 6812 }
6750 /* Don't do NOP if destination is zero: we must perform the actual 6813 /* Don't do NOP if destination is zero: we must perform the actual
6751 memory access. */ 6814 memory access. */
@@ -7069,7 +7132,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7069,7 +7132,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7069 MIPS_INVAL("PMON / selsl"); 7132 MIPS_INVAL("PMON / selsl");
7070 generate_exception(ctx, EXCP_RI); 7133 generate_exception(ctx, EXCP_RI);
7071 #else 7134 #else
7072 - tcg_gen_helper_0_1i(do_pmon, sa); 7135 + tcg_gen_helper_0_i(do_pmon, sa);
7073 #endif 7136 #endif
7074 break; 7137 break;
7075 case OPC_SYSCALL: 7138 case OPC_SYSCALL:
@@ -7187,7 +7250,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7187,7 +7250,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7187 switch (op2) { 7250 switch (op2) {
7188 case OPC_WSBH: 7251 case OPC_WSBH:
7189 gen_load_gpr(cpu_T[1], rt); 7252 gen_load_gpr(cpu_T[1], rt);
7190 - tcg_gen_helper_0_0(do_wsbh); 7253 + tcg_gen_helper_1_2(do_wsbh, cpu_T[0], cpu_T[0], cpu_T[1]);
7191 break; 7254 break;
7192 case OPC_SEB: 7255 case OPC_SEB:
7193 gen_load_gpr(cpu_T[1], rt); 7256 gen_load_gpr(cpu_T[1], rt);
@@ -7209,19 +7272,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7209,19 +7272,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7209 switch (rd) { 7272 switch (rd) {
7210 case 0: 7273 case 0:
7211 save_cpu_state(ctx, 1); 7274 save_cpu_state(ctx, 1);
7212 - tcg_gen_helper_0_0(do_rdhwr_cpunum); 7275 + tcg_gen_helper_1_1(do_rdhwr_cpunum, cpu_T[0], cpu_T[0]);
7213 break; 7276 break;
7214 case 1: 7277 case 1:
7215 save_cpu_state(ctx, 1); 7278 save_cpu_state(ctx, 1);
7216 - tcg_gen_helper_0_0(do_rdhwr_synci_step); 7279 + tcg_gen_helper_1_1(do_rdhwr_synci_step, cpu_T[0], cpu_T[0]);
7217 break; 7280 break;
7218 case 2: 7281 case 2:
7219 save_cpu_state(ctx, 1); 7282 save_cpu_state(ctx, 1);
7220 - tcg_gen_helper_0_0(do_rdhwr_cc); 7283 + tcg_gen_helper_1_1(do_rdhwr_cc, cpu_T[0], cpu_T[0]);
7221 break; 7284 break;
7222 case 3: 7285 case 3:
7223 save_cpu_state(ctx, 1); 7286 save_cpu_state(ctx, 1);
7224 - tcg_gen_helper_0_0(do_rdhwr_ccres); 7287 + tcg_gen_helper_1_1(do_rdhwr_ccres, cpu_T[0], cpu_T[0]);
7225 break; 7288 break;
7226 case 29: 7289 case 29:
7227 #if defined (CONFIG_USER_ONLY) 7290 #if defined (CONFIG_USER_ONLY)
@@ -7241,12 +7304,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7241,12 +7304,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7241 check_insn(env, ctx, ASE_MT); 7304 check_insn(env, ctx, ASE_MT);
7242 gen_load_gpr(cpu_T[0], rt); 7305 gen_load_gpr(cpu_T[0], rt);
7243 gen_load_gpr(cpu_T[1], rs); 7306 gen_load_gpr(cpu_T[1], rs);
7244 - tcg_gen_helper_0_0(do_fork); 7307 + tcg_gen_helper_1_2(do_fork, cpu_T[0], cpu_T[0], cpu_T[1]);
7245 break; 7308 break;
7246 case OPC_YIELD: 7309 case OPC_YIELD:
7247 check_insn(env, ctx, ASE_MT); 7310 check_insn(env, ctx, ASE_MT);
7248 gen_load_gpr(cpu_T[0], rs); 7311 gen_load_gpr(cpu_T[0], rs);
7249 - tcg_gen_helper_0_0(do_yield); 7312 + tcg_gen_helper_1_1(do_yield, cpu_T[0], cpu_T[0]);
7250 gen_store_gpr(cpu_T[0], rd); 7313 gen_store_gpr(cpu_T[0], rd);
7251 break; 7314 break;
7252 #if defined(TARGET_MIPS64) 7315 #if defined(TARGET_MIPS64)
@@ -7263,11 +7326,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7263,11 +7326,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7263 switch (op2) { 7326 switch (op2) {
7264 case OPC_DSBH: 7327 case OPC_DSBH:
7265 gen_load_gpr(cpu_T[1], rt); 7328 gen_load_gpr(cpu_T[1], rt);
7266 - tcg_gen_helper_0_0(do_dsbh); 7329 + tcg_gen_helper_1_2(do_dsbh, cpu_T[0], cpu_T[0], cpu_T[1]);
7267 break; 7330 break;
7268 case OPC_DSHD: 7331 case OPC_DSHD:
7269 gen_load_gpr(cpu_T[1], rt); 7332 gen_load_gpr(cpu_T[1], rt);
7270 - tcg_gen_helper_0_0(do_dshd); 7333 + tcg_gen_helper_1_2(do_dshd, cpu_T[0], cpu_T[0], cpu_T[1]);
7271 break; 7334 break;
7272 default: /* Invalid */ 7335 default: /* Invalid */
7273 MIPS_INVAL("dbshfl"); 7336 MIPS_INVAL("dbshfl");
@@ -7330,31 +7393,31 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7330,31 +7393,31 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7330 switch (op2) { 7393 switch (op2) {
7331 case OPC_DMT: 7394 case OPC_DMT:
7332 check_insn(env, ctx, ASE_MT); 7395 check_insn(env, ctx, ASE_MT);
7333 - tcg_gen_helper_0_0(do_dmt); 7396 + tcg_gen_helper_1_1(do_dmt, cpu_T[0], cpu_T[0]);
7334 break; 7397 break;
7335 case OPC_EMT: 7398 case OPC_EMT:
7336 check_insn(env, ctx, ASE_MT); 7399 check_insn(env, ctx, ASE_MT);
7337 - tcg_gen_helper_0_0(do_emt); 7400 + tcg_gen_helper_1_1(do_emt, cpu_T[0], cpu_T[0]);
7338 break; 7401 break;
7339 case OPC_DVPE: 7402 case OPC_DVPE:
7340 check_insn(env, ctx, ASE_MT); 7403 check_insn(env, ctx, ASE_MT);
7341 - tcg_gen_helper_0_0(do_dvpe); 7404 + tcg_gen_helper_1_1(do_dvpe, cpu_T[0], cpu_T[0]);
7342 break; 7405 break;
7343 case OPC_EVPE: 7406 case OPC_EVPE:
7344 check_insn(env, ctx, ASE_MT); 7407 check_insn(env, ctx, ASE_MT);
7345 - tcg_gen_helper_0_0(do_evpe); 7408 + tcg_gen_helper_1_1(do_evpe, cpu_T[0], cpu_T[0]);
7346 break; 7409 break;
7347 case OPC_DI: 7410 case OPC_DI:
7348 check_insn(env, ctx, ISA_MIPS32R2); 7411 check_insn(env, ctx, ISA_MIPS32R2);
7349 save_cpu_state(ctx, 1); 7412 save_cpu_state(ctx, 1);
7350 - tcg_gen_helper_0_0(do_di); 7413 + tcg_gen_helper_1_1(do_di, cpu_T[0], cpu_T[0]);
7351 /* Stop translation as we may have switched the execution mode */ 7414 /* Stop translation as we may have switched the execution mode */
7352 ctx->bstate = BS_STOP; 7415 ctx->bstate = BS_STOP;
7353 break; 7416 break;
7354 case OPC_EI: 7417 case OPC_EI:
7355 check_insn(env, ctx, ISA_MIPS32R2); 7418 check_insn(env, ctx, ISA_MIPS32R2);
7356 save_cpu_state(ctx, 1); 7419 save_cpu_state(ctx, 1);
7357 - tcg_gen_helper_0_0(do_ei); 7420 + tcg_gen_helper_1_1(do_ei, cpu_T[0], cpu_T[0]);
7358 /* Stop translation as we may have switched the execution mode */ 7421 /* Stop translation as we may have switched the execution mode */
7359 ctx->bstate = BS_STOP; 7422 ctx->bstate = BS_STOP;
7360 break; 7423 break;
@@ -7367,13 +7430,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7367,13 +7430,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7367 break; 7430 break;
7368 case OPC_RDPGPR: 7431 case OPC_RDPGPR:
7369 check_insn(env, ctx, ISA_MIPS32R2); 7432 check_insn(env, ctx, ISA_MIPS32R2);
7370 - gen_load_srsgpr(cpu_T[0], rt);  
7371 - gen_store_gpr(cpu_T[0], rd); 7433 + gen_load_srsgpr(rt, rd);
7372 break; 7434 break;
7373 case OPC_WRPGPR: 7435 case OPC_WRPGPR:
7374 check_insn(env, ctx, ISA_MIPS32R2); 7436 check_insn(env, ctx, ISA_MIPS32R2);
7375 - gen_load_gpr(cpu_T[0], rt);  
7376 - gen_store_srsgpr(cpu_T[0], rd); 7437 + gen_store_srsgpr(rt, rd);
7377 break; 7438 break;
7378 default: 7439 default:
7379 MIPS_INVAL("cp0"); 7440 MIPS_INVAL("cp0");
@@ -7643,7 +7704,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -7643,7 +7704,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7643 if (env->breakpoints[j] == ctx.pc) { 7704 if (env->breakpoints[j] == ctx.pc) {
7644 save_cpu_state(&ctx, 1); 7705 save_cpu_state(&ctx, 1);
7645 ctx.bstate = BS_BRANCH; 7706 ctx.bstate = BS_BRANCH;
7646 - tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG); 7707 + tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
7647 /* Include the breakpoint location or the tb won't 7708 /* Include the breakpoint location or the tb won't
7648 * be flushed when it must be. */ 7709 * be flushed when it must be. */
7649 ctx.pc += 4; 7710 ctx.pc += 4;
@@ -7685,7 +7746,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, @@ -7685,7 +7746,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7685 } 7746 }
7686 if (env->singlestep_enabled) { 7747 if (env->singlestep_enabled) {
7687 save_cpu_state(&ctx, ctx.bstate == BS_NONE); 7748 save_cpu_state(&ctx, ctx.bstate == BS_NONE);
7688 - tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG); 7749 + tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
7689 } else { 7750 } else {
7690 switch (ctx.bstate) { 7751 switch (ctx.bstate) {
7691 case BS_STOP: 7752 case BS_STOP: