Commit be24bb4f3007c3e07cbf1934f7e781493d876ab7
1 parent
ca88500f
Pass T0/T1 explicitly to helper functions, and clean up a few dyngen
leftovers. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
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4 changed files
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1130 additions
and
1105 deletions
target-mips/exec.h
... | ... | @@ -54,7 +54,6 @@ void dump_fpu(CPUState *env); |
54 | 54 | void fpu_dump_state(CPUState *env, FILE *f, |
55 | 55 | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
56 | 56 | int flags); |
57 | -void dump_sc (void); | |
58 | 57 | |
59 | 58 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
60 | 59 | int mmu_idx, int is_softmmu); | ... | ... |
target-mips/helper.h
... | ... | @@ -7,157 +7,157 @@ DEF_HELPER(void, do_raise_exception, (int excp)) |
7 | 7 | DEF_HELPER(void, do_interrupt_restart, (void)) |
8 | 8 | |
9 | 9 | #ifdef TARGET_MIPS64 |
10 | -DEF_HELPER(void, do_ldl, (int mem_idx)) | |
11 | -DEF_HELPER(void, do_ldr, (int mem_idx)) | |
12 | -DEF_HELPER(void, do_sdl, (int mem_idx)) | |
13 | -DEF_HELPER(void, do_sdr, (int mem_idx)) | |
10 | +DEF_HELPER(target_ulong, do_ldl, (target_ulong t0, target_ulong t1, int mem_idx)) | |
11 | +DEF_HELPER(target_ulong, do_ldr, (target_ulong t0, target_ulong t1, int mem_idx)) | |
12 | +DEF_HELPER(void, do_sdl, (target_ulong t0, target_ulong t1, int mem_idx)) | |
13 | +DEF_HELPER(void, do_sdr, (target_ulong t0, target_ulong t1, int mem_idx)) | |
14 | 14 | #endif |
15 | -DEF_HELPER(void, do_lwl, (int mem_idx)) | |
16 | -DEF_HELPER(void, do_lwr, (int mem_idx)) | |
17 | -DEF_HELPER(void, do_swl, (int mem_idx)) | |
18 | -DEF_HELPER(void, do_swr, (int mem_idx)) | |
15 | +DEF_HELPER(target_ulong, do_lwl, (target_ulong t0, target_ulong t1, int mem_idx)) | |
16 | +DEF_HELPER(target_ulong, do_lwr, (target_ulong t0, target_ulong t1, int mem_idx)) | |
17 | +DEF_HELPER(void, do_swl, (target_ulong t0, target_ulong t1, int mem_idx)) | |
18 | +DEF_HELPER(void, do_swr, (target_ulong t0, target_ulong t1, int mem_idx)) | |
19 | 19 | |
20 | -DEF_HELPER(void, do_clo, (void)) | |
21 | -DEF_HELPER(void, do_clz, (void)) | |
20 | +DEF_HELPER(target_ulong, do_clo, (target_ulong t0)) | |
21 | +DEF_HELPER(target_ulong, do_clz, (target_ulong t0)) | |
22 | 22 | #ifdef TARGET_MIPS64 |
23 | -DEF_HELPER(void, do_dclo, (void)) | |
24 | -DEF_HELPER(void, do_dclz, (void)) | |
25 | -DEF_HELPER(void, do_dmult, (void)) | |
26 | -DEF_HELPER(void, do_dmultu, (void)) | |
23 | +DEF_HELPER(target_ulong, do_dclo, (target_ulong t0)) | |
24 | +DEF_HELPER(target_ulong, do_dclz, (target_ulong t0)) | |
25 | +DEF_HELPER(void, do_dmult, (target_ulong t0, target_ulong t1)) | |
26 | +DEF_HELPER(void, do_dmultu, (target_ulong t0, target_ulong t1)) | |
27 | 27 | #endif |
28 | 28 | |
29 | -DEF_HELPER(void, do_muls, (void)) | |
30 | -DEF_HELPER(void, do_mulsu, (void)) | |
31 | -DEF_HELPER(void, do_macc, (void)) | |
32 | -DEF_HELPER(void, do_maccu, (void)) | |
33 | -DEF_HELPER(void, do_msac, (void)) | |
34 | -DEF_HELPER(void, do_msacu, (void)) | |
35 | -DEF_HELPER(void, do_mulhi, (void)) | |
36 | -DEF_HELPER(void, do_mulhiu, (void)) | |
37 | -DEF_HELPER(void, do_mulshi, (void)) | |
38 | -DEF_HELPER(void, do_mulshiu, (void)) | |
39 | -DEF_HELPER(void, do_macchi, (void)) | |
40 | -DEF_HELPER(void, do_macchiu, (void)) | |
41 | -DEF_HELPER(void, do_msachi, (void)) | |
42 | -DEF_HELPER(void, do_msachiu, (void)) | |
29 | +DEF_HELPER(target_ulong, do_muls, (target_ulong t0, target_ulong t1)) | |
30 | +DEF_HELPER(target_ulong, do_mulsu, (target_ulong t0, target_ulong t1)) | |
31 | +DEF_HELPER(target_ulong, do_macc, (target_ulong t0, target_ulong t1)) | |
32 | +DEF_HELPER(target_ulong, do_maccu, (target_ulong t0, target_ulong t1)) | |
33 | +DEF_HELPER(target_ulong, do_msac, (target_ulong t0, target_ulong t1)) | |
34 | +DEF_HELPER(target_ulong, do_msacu, (target_ulong t0, target_ulong t1)) | |
35 | +DEF_HELPER(target_ulong, do_mulhi, (target_ulong t0, target_ulong t1)) | |
36 | +DEF_HELPER(target_ulong, do_mulhiu, (target_ulong t0, target_ulong t1)) | |
37 | +DEF_HELPER(target_ulong, do_mulshi, (target_ulong t0, target_ulong t1)) | |
38 | +DEF_HELPER(target_ulong, do_mulshiu, (target_ulong t0, target_ulong t1)) | |
39 | +DEF_HELPER(target_ulong, do_macchi, (target_ulong t0, target_ulong t1)) | |
40 | +DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1)) | |
41 | +DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1)) | |
42 | +DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1)) | |
43 | 43 | |
44 | 44 | /* CP0 helpers */ |
45 | 45 | #ifndef CONFIG_USER_ONLY |
46 | -DEF_HELPER(void, do_mfc0_mvpcontrol, (void)) | |
47 | -DEF_HELPER(void, do_mfc0_mvpconf0, (void)) | |
48 | -DEF_HELPER(void, do_mfc0_mvpconf1, (void)) | |
49 | -DEF_HELPER(void, do_mfc0_random, (void)) | |
50 | -DEF_HELPER(void, do_mfc0_tcstatus, (void)) | |
51 | -DEF_HELPER(void, do_mftc0_tcstatus, (void)) | |
52 | -DEF_HELPER(void, do_mfc0_tcbind, (void)) | |
53 | -DEF_HELPER(void, do_mftc0_tcbind, (void)) | |
54 | -DEF_HELPER(void, do_mfc0_tcrestart, (void)) | |
55 | -DEF_HELPER(void, do_mftc0_tcrestart, (void)) | |
56 | -DEF_HELPER(void, do_mfc0_tchalt, (void)) | |
57 | -DEF_HELPER(void, do_mftc0_tchalt, (void)) | |
58 | -DEF_HELPER(void, do_mfc0_tccontext, (void)) | |
59 | -DEF_HELPER(void, do_mftc0_tccontext, (void)) | |
60 | -DEF_HELPER(void, do_mfc0_tcschedule, (void)) | |
61 | -DEF_HELPER(void, do_mftc0_tcschedule, (void)) | |
62 | -DEF_HELPER(void, do_mfc0_tcschefback, (void)) | |
63 | -DEF_HELPER(void, do_mftc0_tcschefback, (void)) | |
64 | -DEF_HELPER(void, do_mfc0_count, (void)) | |
65 | -DEF_HELPER(void, do_mftc0_entryhi, (void)) | |
66 | -DEF_HELPER(void, do_mftc0_status, (void)) | |
67 | -DEF_HELPER(void, do_mfc0_lladdr, (void)) | |
68 | -DEF_HELPER(void, do_mfc0_watchlo, (uint32_t sel)) | |
69 | -DEF_HELPER(void, do_mfc0_watchhi, (uint32_t sel)) | |
70 | -DEF_HELPER(void, do_mfc0_debug, (void)) | |
71 | -DEF_HELPER(void, do_mftc0_debug, (void)) | |
46 | +DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (target_ulong t0)) | |
47 | +DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (target_ulong t0)) | |
48 | +DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (target_ulong t0)) | |
49 | +DEF_HELPER(target_ulong, do_mfc0_random, (target_ulong t0)) | |
50 | +DEF_HELPER(target_ulong, do_mfc0_tcstatus, (target_ulong t0)) | |
51 | +DEF_HELPER(target_ulong, do_mftc0_tcstatus, (target_ulong t0)) | |
52 | +DEF_HELPER(target_ulong, do_mfc0_tcbind, (target_ulong t0)) | |
53 | +DEF_HELPER(target_ulong, do_mftc0_tcbind, (target_ulong t0)) | |
54 | +DEF_HELPER(target_ulong, do_mfc0_tcrestart, (target_ulong t0)) | |
55 | +DEF_HELPER(target_ulong, do_mftc0_tcrestart, (target_ulong t0)) | |
56 | +DEF_HELPER(target_ulong, do_mfc0_tchalt, (target_ulong t0)) | |
57 | +DEF_HELPER(target_ulong, do_mftc0_tchalt, (target_ulong t0)) | |
58 | +DEF_HELPER(target_ulong, do_mfc0_tccontext, (target_ulong t0)) | |
59 | +DEF_HELPER(target_ulong, do_mftc0_tccontext, (target_ulong t0)) | |
60 | +DEF_HELPER(target_ulong, do_mfc0_tcschedule, (target_ulong t0)) | |
61 | +DEF_HELPER(target_ulong, do_mftc0_tcschedule, (target_ulong t0)) | |
62 | +DEF_HELPER(target_ulong, do_mfc0_tcschefback, (target_ulong t0)) | |
63 | +DEF_HELPER(target_ulong, do_mftc0_tcschefback, (target_ulong t0)) | |
64 | +DEF_HELPER(target_ulong, do_mfc0_count, (target_ulong t0)) | |
65 | +DEF_HELPER(target_ulong, do_mftc0_entryhi, (target_ulong t0)) | |
66 | +DEF_HELPER(target_ulong, do_mftc0_status, (target_ulong t0)) | |
67 | +DEF_HELPER(target_ulong, do_mfc0_lladdr, (target_ulong t0)) | |
68 | +DEF_HELPER(target_ulong, do_mfc0_watchlo, (target_ulong t0, uint32_t sel)) | |
69 | +DEF_HELPER(target_ulong, do_mfc0_watchhi, (target_ulong t0, uint32_t sel)) | |
70 | +DEF_HELPER(target_ulong, do_mfc0_debug, (target_ulong t0)) | |
71 | +DEF_HELPER(target_ulong, do_mftc0_debug, (target_ulong t0)) | |
72 | 72 | #ifdef TARGET_MIPS64 |
73 | -DEF_HELPER(void, do_dmfc0_tcrestart, (void)) | |
74 | -DEF_HELPER(void, do_dmfc0_tchalt, (void)) | |
75 | -DEF_HELPER(void, do_dmfc0_tccontext, (void)) | |
76 | -DEF_HELPER(void, do_dmfc0_tcschedule, (void)) | |
77 | -DEF_HELPER(void, do_dmfc0_tcschefback, (void)) | |
78 | -DEF_HELPER(void, do_dmfc0_lladdr, (void)) | |
79 | -DEF_HELPER(void, do_dmfc0_watchlo, (uint32_t sel)) | |
73 | +DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (target_ulong t0)) | |
74 | +DEF_HELPER(target_ulong, do_dmfc0_tchalt, (target_ulong t0)) | |
75 | +DEF_HELPER(target_ulong, do_dmfc0_tccontext, (target_ulong t0)) | |
76 | +DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (target_ulong t0)) | |
77 | +DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (target_ulong t0)) | |
78 | +DEF_HELPER(target_ulong, do_dmfc0_lladdr, (target_ulong t0)) | |
79 | +DEF_HELPER(target_ulong, do_dmfc0_watchlo, (target_ulong t0, uint32_t sel)) | |
80 | 80 | #endif /* TARGET_MIPS64 */ |
81 | 81 | |
82 | -DEF_HELPER(void, do_mtc0_index, (void)) | |
83 | -DEF_HELPER(void, do_mtc0_mvpcontrol, (void)) | |
84 | -DEF_HELPER(void, do_mtc0_vpecontrol, (void)) | |
85 | -DEF_HELPER(void, do_mtc0_vpeconf0, (void)) | |
86 | -DEF_HELPER(void, do_mtc0_vpeconf1, (void)) | |
87 | -DEF_HELPER(void, do_mtc0_yqmask, (void)) | |
88 | -DEF_HELPER(void, do_mtc0_vpeopt, (void)) | |
89 | -DEF_HELPER(void, do_mtc0_entrylo0, (void)) | |
90 | -DEF_HELPER(void, do_mtc0_tcstatus, (void)) | |
91 | -DEF_HELPER(void, do_mttc0_tcstatus, (void)) | |
92 | -DEF_HELPER(void, do_mtc0_tcbind, (void)) | |
93 | -DEF_HELPER(void, do_mttc0_tcbind, (void)) | |
94 | -DEF_HELPER(void, do_mtc0_tcrestart, (void)) | |
95 | -DEF_HELPER(void, do_mttc0_tcrestart, (void)) | |
96 | -DEF_HELPER(void, do_mtc0_tchalt, (void)) | |
97 | -DEF_HELPER(void, do_mttc0_tchalt, (void)) | |
98 | -DEF_HELPER(void, do_mtc0_tccontext, (void)) | |
99 | -DEF_HELPER(void, do_mttc0_tccontext, (void)) | |
100 | -DEF_HELPER(void, do_mtc0_tcschedule, (void)) | |
101 | -DEF_HELPER(void, do_mttc0_tcschedule, (void)) | |
102 | -DEF_HELPER(void, do_mtc0_tcschefback, (void)) | |
103 | -DEF_HELPER(void, do_mttc0_tcschefback, (void)) | |
104 | -DEF_HELPER(void, do_mtc0_entrylo1, (void)) | |
105 | -DEF_HELPER(void, do_mtc0_context, (void)) | |
106 | -DEF_HELPER(void, do_mtc0_pagemask, (void)) | |
107 | -DEF_HELPER(void, do_mtc0_pagegrain, (void)) | |
108 | -DEF_HELPER(void, do_mtc0_wired, (void)) | |
109 | -DEF_HELPER(void, do_mtc0_srsconf0, (void)) | |
110 | -DEF_HELPER(void, do_mtc0_srsconf1, (void)) | |
111 | -DEF_HELPER(void, do_mtc0_srsconf2, (void)) | |
112 | -DEF_HELPER(void, do_mtc0_srsconf3, (void)) | |
113 | -DEF_HELPER(void, do_mtc0_srsconf4, (void)) | |
114 | -DEF_HELPER(void, do_mtc0_hwrena, (void)) | |
115 | -DEF_HELPER(void, do_mtc0_count, (void)) | |
116 | -DEF_HELPER(void, do_mtc0_entryhi, (void)) | |
117 | -DEF_HELPER(void, do_mttc0_entryhi, (void)) | |
118 | -DEF_HELPER(void, do_mtc0_compare, (void)) | |
119 | -DEF_HELPER(void, do_mtc0_status, (void)) | |
120 | -DEF_HELPER(void, do_mttc0_status, (void)) | |
121 | -DEF_HELPER(void, do_mtc0_intctl, (void)) | |
122 | -DEF_HELPER(void, do_mtc0_srsctl, (void)) | |
123 | -DEF_HELPER(void, do_mtc0_cause, (void)) | |
124 | -DEF_HELPER(void, do_mtc0_ebase, (void)) | |
125 | -DEF_HELPER(void, do_mtc0_config0, (void)) | |
126 | -DEF_HELPER(void, do_mtc0_config2, (void)) | |
127 | -DEF_HELPER(void, do_mtc0_watchlo, (uint32_t sel)) | |
128 | -DEF_HELPER(void, do_mtc0_watchhi, (uint32_t sel)) | |
129 | -DEF_HELPER(void, do_mtc0_xcontext, (void)) | |
130 | -DEF_HELPER(void, do_mtc0_framemask, (void)) | |
131 | -DEF_HELPER(void, do_mtc0_debug, (void)) | |
132 | -DEF_HELPER(void, do_mttc0_debug, (void)) | |
133 | -DEF_HELPER(void, do_mtc0_performance0, (void)) | |
134 | -DEF_HELPER(void, do_mtc0_taglo, (void)) | |
135 | -DEF_HELPER(void, do_mtc0_datalo, (void)) | |
136 | -DEF_HELPER(void, do_mtc0_taghi, (void)) | |
137 | -DEF_HELPER(void, do_mtc0_datahi, (void)) | |
82 | +DEF_HELPER(void, do_mtc0_index, (target_ulong t0)) | |
83 | +DEF_HELPER(void, do_mtc0_mvpcontrol, (target_ulong t0)) | |
84 | +DEF_HELPER(void, do_mtc0_vpecontrol, (target_ulong t0)) | |
85 | +DEF_HELPER(void, do_mtc0_vpeconf0, (target_ulong t0)) | |
86 | +DEF_HELPER(void, do_mtc0_vpeconf1, (target_ulong t0)) | |
87 | +DEF_HELPER(void, do_mtc0_yqmask, (target_ulong t0)) | |
88 | +DEF_HELPER(void, do_mtc0_vpeopt, (target_ulong t0)) | |
89 | +DEF_HELPER(void, do_mtc0_entrylo0, (target_ulong t0)) | |
90 | +DEF_HELPER(void, do_mtc0_tcstatus, (target_ulong t0)) | |
91 | +DEF_HELPER(void, do_mttc0_tcstatus, (target_ulong t0)) | |
92 | +DEF_HELPER(void, do_mtc0_tcbind, (target_ulong t0)) | |
93 | +DEF_HELPER(void, do_mttc0_tcbind, (target_ulong t0)) | |
94 | +DEF_HELPER(void, do_mtc0_tcrestart, (target_ulong t0)) | |
95 | +DEF_HELPER(void, do_mttc0_tcrestart, (target_ulong t0)) | |
96 | +DEF_HELPER(void, do_mtc0_tchalt, (target_ulong t0)) | |
97 | +DEF_HELPER(void, do_mttc0_tchalt, (target_ulong t0)) | |
98 | +DEF_HELPER(void, do_mtc0_tccontext, (target_ulong t0)) | |
99 | +DEF_HELPER(void, do_mttc0_tccontext, (target_ulong t0)) | |
100 | +DEF_HELPER(void, do_mtc0_tcschedule, (target_ulong t0)) | |
101 | +DEF_HELPER(void, do_mttc0_tcschedule, (target_ulong t0)) | |
102 | +DEF_HELPER(void, do_mtc0_tcschefback, (target_ulong t0)) | |
103 | +DEF_HELPER(void, do_mttc0_tcschefback, (target_ulong t0)) | |
104 | +DEF_HELPER(void, do_mtc0_entrylo1, (target_ulong t0)) | |
105 | +DEF_HELPER(void, do_mtc0_context, (target_ulong t0)) | |
106 | +DEF_HELPER(void, do_mtc0_pagemask, (target_ulong t0)) | |
107 | +DEF_HELPER(void, do_mtc0_pagegrain, (target_ulong t0)) | |
108 | +DEF_HELPER(void, do_mtc0_wired, (target_ulong t0)) | |
109 | +DEF_HELPER(void, do_mtc0_srsconf0, (target_ulong t0)) | |
110 | +DEF_HELPER(void, do_mtc0_srsconf1, (target_ulong t0)) | |
111 | +DEF_HELPER(void, do_mtc0_srsconf2, (target_ulong t0)) | |
112 | +DEF_HELPER(void, do_mtc0_srsconf3, (target_ulong t0)) | |
113 | +DEF_HELPER(void, do_mtc0_srsconf4, (target_ulong t0)) | |
114 | +DEF_HELPER(void, do_mtc0_hwrena, (target_ulong t0)) | |
115 | +DEF_HELPER(void, do_mtc0_count, (target_ulong t0)) | |
116 | +DEF_HELPER(void, do_mtc0_entryhi, (target_ulong t0)) | |
117 | +DEF_HELPER(void, do_mttc0_entryhi, (target_ulong t0)) | |
118 | +DEF_HELPER(void, do_mtc0_compare, (target_ulong t0)) | |
119 | +DEF_HELPER(void, do_mtc0_status, (target_ulong t0)) | |
120 | +DEF_HELPER(void, do_mttc0_status, (target_ulong t0)) | |
121 | +DEF_HELPER(void, do_mtc0_intctl, (target_ulong t0)) | |
122 | +DEF_HELPER(void, do_mtc0_srsctl, (target_ulong t0)) | |
123 | +DEF_HELPER(void, do_mtc0_cause, (target_ulong t0)) | |
124 | +DEF_HELPER(void, do_mtc0_ebase, (target_ulong t0)) | |
125 | +DEF_HELPER(void, do_mtc0_config0, (target_ulong t0)) | |
126 | +DEF_HELPER(void, do_mtc0_config2, (target_ulong t0)) | |
127 | +DEF_HELPER(void, do_mtc0_watchlo, (target_ulong t0, uint32_t sel)) | |
128 | +DEF_HELPER(void, do_mtc0_watchhi, (target_ulong t0, uint32_t sel)) | |
129 | +DEF_HELPER(void, do_mtc0_xcontext, (target_ulong t0)) | |
130 | +DEF_HELPER(void, do_mtc0_framemask, (target_ulong t0)) | |
131 | +DEF_HELPER(void, do_mtc0_debug, (target_ulong t0)) | |
132 | +DEF_HELPER(void, do_mttc0_debug, (target_ulong t0)) | |
133 | +DEF_HELPER(void, do_mtc0_performance0, (target_ulong t0)) | |
134 | +DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0)) | |
135 | +DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0)) | |
136 | +DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0)) | |
137 | +DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0)) | |
138 | 138 | #endif /* !CONFIG_USER_ONLY */ |
139 | 139 | |
140 | 140 | /* MIPS MT functions */ |
141 | -DEF_HELPER(void, do_mftgpr, (uint32_t sel)) | |
142 | -DEF_HELPER(void, do_mftlo, (uint32_t sel)) | |
143 | -DEF_HELPER(void, do_mfthi, (uint32_t sel)) | |
144 | -DEF_HELPER(void, do_mftacx, (uint32_t sel)) | |
145 | -DEF_HELPER(void, do_mftdsp, (void)) | |
146 | -DEF_HELPER(void, do_mttgpr, (uint32_t sel)) | |
147 | -DEF_HELPER(void, do_mttlo, (uint32_t sel)) | |
148 | -DEF_HELPER(void, do_mtthi, (uint32_t sel)) | |
149 | -DEF_HELPER(void, do_mttacx, (uint32_t sel)) | |
150 | -DEF_HELPER(void, do_mttdsp, (void)) | |
151 | -DEF_HELPER(void, do_dmt, (void)) | |
152 | -DEF_HELPER(void, do_emt, (void)) | |
153 | -DEF_HELPER(void, do_dvpe, (void)) | |
154 | -DEF_HELPER(void, do_evpe, (void)) | |
155 | -DEF_HELPER(void, do_fork, (void)) | |
156 | -DEF_HELPER(void, do_yield, (void)) | |
141 | +DEF_HELPER(target_ulong, do_mftgpr, (target_ulong t0, uint32_t sel)) | |
142 | +DEF_HELPER(target_ulong, do_mftlo, (target_ulong t0, uint32_t sel)) | |
143 | +DEF_HELPER(target_ulong, do_mfthi, (target_ulong t0, uint32_t sel)) | |
144 | +DEF_HELPER(target_ulong, do_mftacx, (target_ulong t0, uint32_t sel)) | |
145 | +DEF_HELPER(target_ulong, do_mftdsp, (target_ulong t0)) | |
146 | +DEF_HELPER(void, do_mttgpr, (target_ulong t0, uint32_t sel)) | |
147 | +DEF_HELPER(void, do_mttlo, (target_ulong t0, uint32_t sel)) | |
148 | +DEF_HELPER(void, do_mtthi, (target_ulong t0, uint32_t sel)) | |
149 | +DEF_HELPER(void, do_mttacx, (target_ulong t0, uint32_t sel)) | |
150 | +DEF_HELPER(void, do_mttdsp, (target_ulong t0)) | |
151 | +DEF_HELPER(target_ulong, do_dmt, (target_ulong t0)) | |
152 | +DEF_HELPER(target_ulong, do_emt, (target_ulong t0)) | |
153 | +DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0)) | |
154 | +DEF_HELPER(target_ulong, do_evpe, (target_ulong t0)) | |
155 | +DEF_HELPER(target_ulong, do_fork, (target_ulong t0, target_ulong t1)) | |
156 | +DEF_HELPER(target_ulong, do_yield, (target_ulong t0)) | |
157 | 157 | |
158 | 158 | /* CP1 functions */ |
159 | -DEF_HELPER(void, do_cfc1, (uint32_t reg)) | |
160 | -DEF_HELPER(void, do_ctc1, (uint32_t reg)) | |
159 | +DEF_HELPER(target_ulong, do_cfc1, (target_ulong t0, uint32_t reg)) | |
160 | +DEF_HELPER(void, do_ctc1, (target_ulong t0, uint32_t reg)) | |
161 | 161 | |
162 | 162 | DEF_HELPER(void, do_float_cvtd_s, (void)) |
163 | 163 | DEF_HELPER(void, do_float_cvtd_w, (void)) |
... | ... | @@ -239,24 +239,24 @@ FOP_PROTO(ngt) |
239 | 239 | #undef FOP_PROTO |
240 | 240 | |
241 | 241 | /* Special functions */ |
242 | -DEF_HELPER(void, do_di, (void)) | |
243 | -DEF_HELPER(void, do_ei, (void)) | |
244 | -DEF_HELPER(void, do_eret, (void)) | |
245 | -DEF_HELPER(void, do_deret, (void)) | |
246 | -DEF_HELPER(void, do_rdhwr_cpunum, (void)) | |
247 | -DEF_HELPER(void, do_rdhwr_synci_step, (void)) | |
248 | -DEF_HELPER(void, do_rdhwr_cc, (void)) | |
249 | -DEF_HELPER(void, do_rdhwr_ccres, (void)) | |
242 | +DEF_HELPER(target_ulong, do_di, (target_ulong t0)) | |
243 | +DEF_HELPER(target_ulong, do_ei, (target_ulong t0)) | |
244 | +DEF_HELPER(void, do_eret, (target_ulong t0)) | |
245 | +DEF_HELPER(void, do_deret, (target_ulong t0)) | |
246 | +DEF_HELPER(target_ulong, do_rdhwr_cpunum, (target_ulong t0)) | |
247 | +DEF_HELPER(target_ulong, do_rdhwr_synci_step, (target_ulong t0)) | |
248 | +DEF_HELPER(target_ulong, do_rdhwr_cc, (target_ulong t0)) | |
249 | +DEF_HELPER(target_ulong, do_rdhwr_ccres, (target_ulong t0)) | |
250 | 250 | DEF_HELPER(void, do_pmon, (int function)) |
251 | 251 | DEF_HELPER(void, do_wait, (void)) |
252 | 252 | |
253 | 253 | /* Bitfield operations. */ |
254 | -DEF_HELPER(void, do_ext, (uint32_t pos, uint32_t size)) | |
255 | -DEF_HELPER(void, do_ins, (uint32_t pos, uint32_t size)) | |
256 | -DEF_HELPER(void, do_wsbh, (void)) | |
254 | +DEF_HELPER(target_ulong, do_ext, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)) | |
255 | +DEF_HELPER(target_ulong, do_ins, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)) | |
256 | +DEF_HELPER(target_ulong, do_wsbh, (target_ulong t0, target_ulong t1)) | |
257 | 257 | #ifdef TARGET_MIPS64 |
258 | -DEF_HELPER(void, do_dext, (uint32_t pos, uint32_t size)) | |
259 | -DEF_HELPER(void, do_dins, (uint32_t pos, uint32_t size)) | |
260 | -DEF_HELPER(void, do_dsbh, (void)) | |
261 | -DEF_HELPER(void, do_dshd, (void)) | |
258 | +DEF_HELPER(target_ulong, do_dext, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)) | |
259 | +DEF_HELPER(target_ulong, do_dins, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)) | |
260 | +DEF_HELPER(target_ulong, do_dsbh, (target_ulong t0, target_ulong t1)) | |
261 | +DEF_HELPER(target_ulong, do_dshd, (target_ulong t0, target_ulong t1)) | |
262 | 262 | #endif | ... | ... |
target-mips/op_helper.c
... | ... | @@ -33,7 +33,6 @@ void do_raise_exception_err (uint32_t exception, int error_code) |
33 | 33 | #endif |
34 | 34 | env->exception_index = exception; |
35 | 35 | env->error_code = error_code; |
36 | - T0 = 0; | |
37 | 36 | cpu_loop_exit(); |
38 | 37 | } |
39 | 38 | |
... | ... | @@ -65,106 +64,26 @@ void do_restore_state (void *pc_ptr) |
65 | 64 | } |
66 | 65 | } |
67 | 66 | |
68 | -void do_clo (void) | |
67 | +target_ulong do_clo (target_ulong t0) | |
69 | 68 | { |
70 | - T0 = clo32(T0); | |
69 | + return clo32(t0); | |
71 | 70 | } |
72 | 71 | |
73 | -void do_clz (void) | |
72 | +target_ulong do_clz (target_ulong t0) | |
74 | 73 | { |
75 | - T0 = clz32(T0); | |
74 | + return clz32(t0); | |
76 | 75 | } |
77 | 76 | |
78 | 77 | #if defined(TARGET_MIPS64) |
79 | -#if TARGET_LONG_BITS > HOST_LONG_BITS | |
80 | -/* Those might call libgcc functions. */ | |
81 | -void do_dsll (void) | |
82 | -{ | |
83 | - T0 = T0 << T1; | |
84 | -} | |
85 | - | |
86 | -void do_dsll32 (void) | |
87 | -{ | |
88 | - T0 = T0 << (T1 + 32); | |
89 | -} | |
90 | - | |
91 | -void do_dsra (void) | |
92 | -{ | |
93 | - T0 = (int64_t)T0 >> T1; | |
94 | -} | |
95 | - | |
96 | -void do_dsra32 (void) | |
97 | -{ | |
98 | - T0 = (int64_t)T0 >> (T1 + 32); | |
99 | -} | |
100 | - | |
101 | -void do_dsrl (void) | |
102 | -{ | |
103 | - T0 = T0 >> T1; | |
104 | -} | |
105 | - | |
106 | -void do_dsrl32 (void) | |
107 | -{ | |
108 | - T0 = T0 >> (T1 + 32); | |
109 | -} | |
110 | - | |
111 | -void do_drotr (void) | |
112 | -{ | |
113 | - target_ulong tmp; | |
114 | - | |
115 | - if (T1) { | |
116 | - tmp = T0 << (0x40 - T1); | |
117 | - T0 = (T0 >> T1) | tmp; | |
118 | - } | |
119 | -} | |
120 | - | |
121 | -void do_drotr32 (void) | |
122 | -{ | |
123 | - target_ulong tmp; | |
124 | - | |
125 | - tmp = T0 << (0x40 - (32 + T1)); | |
126 | - T0 = (T0 >> (32 + T1)) | tmp; | |
127 | -} | |
128 | - | |
129 | -void do_dsllv (void) | |
130 | -{ | |
131 | - T0 = T1 << (T0 & 0x3F); | |
132 | -} | |
133 | - | |
134 | -void do_dsrav (void) | |
135 | -{ | |
136 | - T0 = (int64_t)T1 >> (T0 & 0x3F); | |
137 | -} | |
138 | - | |
139 | -void do_dsrlv (void) | |
140 | -{ | |
141 | - T0 = T1 >> (T0 & 0x3F); | |
142 | -} | |
143 | - | |
144 | -void do_drotrv (void) | |
145 | -{ | |
146 | - target_ulong tmp; | |
147 | - | |
148 | - T0 &= 0x3F; | |
149 | - if (T0) { | |
150 | - tmp = T1 << (0x40 - T0); | |
151 | - T0 = (T1 >> T0) | tmp; | |
152 | - } else | |
153 | - T0 = T1; | |
154 | -} | |
155 | - | |
156 | -#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
157 | - | |
158 | -void do_dclo (void) | |
78 | +target_ulong do_dclo (target_ulong t0) | |
159 | 79 | { |
160 | - T0 = clo64(T0); | |
80 | + return clo64(t0); | |
161 | 81 | } |
162 | 82 | |
163 | -void do_dclz (void) | |
83 | +target_ulong do_dclz (target_ulong t0) | |
164 | 84 | { |
165 | - T0 = clz64(T0); | |
85 | + return clz64(t0); | |
166 | 86 | } |
167 | - | |
168 | 87 | #endif /* TARGET_MIPS64 */ |
169 | 88 | |
170 | 89 | /* 64 bits arithmetic for 32 bits hosts */ |
... | ... | @@ -179,132 +98,160 @@ static always_inline void set_HILO (uint64_t HILO) |
179 | 98 | env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
180 | 99 | } |
181 | 100 | |
182 | -static always_inline void set_HIT0_LO (uint64_t HILO) | |
101 | +static always_inline void set_HIT0_LO (target_ulong t0, uint64_t HILO) | |
183 | 102 | { |
184 | 103 | env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
185 | - T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); | |
104 | + t0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); | |
186 | 105 | } |
187 | 106 | |
188 | -static always_inline void set_HI_LOT0 (uint64_t HILO) | |
107 | +static always_inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO) | |
189 | 108 | { |
190 | - T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); | |
109 | + t0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); | |
191 | 110 | env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
192 | 111 | } |
193 | 112 | |
194 | 113 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
195 | -void do_madd (void) | |
114 | +void do_madd (target_ulong t0, target_ulong t1) | |
196 | 115 | { |
197 | 116 | int64_t tmp; |
198 | 117 | |
199 | - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
118 | + tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1); | |
200 | 119 | set_HILO((int64_t)get_HILO() + tmp); |
201 | 120 | } |
202 | 121 | |
203 | -void do_maddu (void) | |
122 | +void do_maddu (target_ulong t0, target_ulong t1) | |
204 | 123 | { |
205 | 124 | uint64_t tmp; |
206 | 125 | |
207 | - tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
126 | + tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1); | |
208 | 127 | set_HILO(get_HILO() + tmp); |
209 | 128 | } |
210 | 129 | |
211 | -void do_msub (void) | |
130 | +void do_msub (target_ulong t0, target_ulong t1) | |
212 | 131 | { |
213 | 132 | int64_t tmp; |
214 | 133 | |
215 | - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
134 | + tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1); | |
216 | 135 | set_HILO((int64_t)get_HILO() - tmp); |
217 | 136 | } |
218 | 137 | |
219 | -void do_msubu (void) | |
138 | +void do_msubu (target_ulong t0, target_ulong t1) | |
220 | 139 | { |
221 | 140 | uint64_t tmp; |
222 | 141 | |
223 | - tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
142 | + tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1); | |
224 | 143 | set_HILO(get_HILO() - tmp); |
225 | 144 | } |
226 | 145 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
227 | 146 | |
228 | 147 | /* Multiplication variants of the vr54xx. */ |
229 | -void do_muls (void) | |
148 | +target_ulong do_muls (target_ulong t0, target_ulong t1) | |
230 | 149 | { |
231 | - set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); | |
150 | + set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); | |
151 | + | |
152 | + return t0; | |
232 | 153 | } |
233 | 154 | |
234 | -void do_mulsu (void) | |
155 | +target_ulong do_mulsu (target_ulong t0, target_ulong t1) | |
235 | 156 | { |
236 | - set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); | |
157 | + set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); | |
158 | + | |
159 | + return t0; | |
237 | 160 | } |
238 | 161 | |
239 | -void do_macc (void) | |
162 | +target_ulong do_macc (target_ulong t0, target_ulong t1) | |
240 | 163 | { |
241 | - set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); | |
164 | + set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); | |
165 | + | |
166 | + return t0; | |
242 | 167 | } |
243 | 168 | |
244 | -void do_macchi (void) | |
169 | +target_ulong do_macchi (target_ulong t0, target_ulong t1) | |
245 | 170 | { |
246 | - set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); | |
171 | + set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); | |
172 | + | |
173 | + return t0; | |
247 | 174 | } |
248 | 175 | |
249 | -void do_maccu (void) | |
176 | +target_ulong do_maccu (target_ulong t0, target_ulong t1) | |
250 | 177 | { |
251 | - set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); | |
178 | + set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); | |
179 | + | |
180 | + return t0; | |
252 | 181 | } |
253 | 182 | |
254 | -void do_macchiu (void) | |
183 | +target_ulong do_macchiu (target_ulong t0, target_ulong t1) | |
255 | 184 | { |
256 | - set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); | |
185 | + set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); | |
186 | + | |
187 | + return t0; | |
257 | 188 | } |
258 | 189 | |
259 | -void do_msac (void) | |
190 | +target_ulong do_msac (target_ulong t0, target_ulong t1) | |
260 | 191 | { |
261 | - set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); | |
192 | + set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); | |
193 | + | |
194 | + return t0; | |
262 | 195 | } |
263 | 196 | |
264 | -void do_msachi (void) | |
197 | +target_ulong do_msachi (target_ulong t0, target_ulong t1) | |
265 | 198 | { |
266 | - set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); | |
199 | + set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); | |
200 | + | |
201 | + return t0; | |
267 | 202 | } |
268 | 203 | |
269 | -void do_msacu (void) | |
204 | +target_ulong do_msacu (target_ulong t0, target_ulong t1) | |
270 | 205 | { |
271 | - set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); | |
206 | + set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); | |
207 | + | |
208 | + return t0; | |
272 | 209 | } |
273 | 210 | |
274 | -void do_msachiu (void) | |
211 | +target_ulong do_msachiu (target_ulong t0, target_ulong t1) | |
275 | 212 | { |
276 | - set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); | |
213 | + set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); | |
214 | + | |
215 | + return t0; | |
277 | 216 | } |
278 | 217 | |
279 | -void do_mulhi (void) | |
218 | +target_ulong do_mulhi (target_ulong t0, target_ulong t1) | |
280 | 219 | { |
281 | - set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
220 | + set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1); | |
221 | + | |
222 | + return t0; | |
282 | 223 | } |
283 | 224 | |
284 | -void do_mulhiu (void) | |
225 | +target_ulong do_mulhiu (target_ulong t0, target_ulong t1) | |
285 | 226 | { |
286 | - set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
227 | + set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1); | |
228 | + | |
229 | + return t0; | |
287 | 230 | } |
288 | 231 | |
289 | -void do_mulshi (void) | |
232 | +target_ulong do_mulshi (target_ulong t0, target_ulong t1) | |
290 | 233 | { |
291 | - set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); | |
234 | + set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); | |
235 | + | |
236 | + return t0; | |
292 | 237 | } |
293 | 238 | |
294 | -void do_mulshiu (void) | |
239 | +target_ulong do_mulshiu (target_ulong t0, target_ulong t1) | |
295 | 240 | { |
296 | - set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); | |
241 | + set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); | |
242 | + | |
243 | + return t0; | |
297 | 244 | } |
298 | 245 | |
299 | 246 | #ifdef TARGET_MIPS64 |
300 | -void do_dmult (void) | |
247 | +void do_dmult (target_ulong t0, target_ulong t1) | |
301 | 248 | { |
302 | - muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1); | |
249 | + muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1); | |
303 | 250 | } |
304 | 251 | |
305 | -void do_dmultu (void) | |
252 | +void do_dmultu (target_ulong t0, target_ulong t1) | |
306 | 253 | { |
307 | - mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1); | |
254 | + mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1); | |
308 | 255 | } |
309 | 256 | #endif |
310 | 257 | |
... | ... | @@ -316,7 +263,7 @@ void do_dmultu (void) |
316 | 263 | #define GET_OFFSET(addr, offset) (addr - (offset)) |
317 | 264 | #endif |
318 | 265 | |
319 | -void do_lwl(int mem_idx) | |
266 | +target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx) | |
320 | 267 | { |
321 | 268 | target_ulong tmp; |
322 | 269 | |
... | ... | @@ -333,27 +280,27 @@ void do_lwl(int mem_idx) |
333 | 280 | case 2: ldfun = ldub_user; break; |
334 | 281 | } |
335 | 282 | #endif |
336 | - tmp = ldfun(T0); | |
337 | - T1 = (T1 & 0x00FFFFFF) | (tmp << 24); | |
283 | + tmp = ldfun(t0); | |
284 | + t1 = (t1 & 0x00FFFFFF) | (tmp << 24); | |
338 | 285 | |
339 | - if (GET_LMASK(T0) <= 2) { | |
340 | - tmp = ldfun(GET_OFFSET(T0, 1)); | |
341 | - T1 = (T1 & 0xFF00FFFF) | (tmp << 16); | |
286 | + if (GET_LMASK(t0) <= 2) { | |
287 | + tmp = ldfun(GET_OFFSET(t0, 1)); | |
288 | + t1 = (t1 & 0xFF00FFFF) | (tmp << 16); | |
342 | 289 | } |
343 | 290 | |
344 | - if (GET_LMASK(T0) <= 1) { | |
345 | - tmp = ldfun(GET_OFFSET(T0, 2)); | |
346 | - T1 = (T1 & 0xFFFF00FF) | (tmp << 8); | |
291 | + if (GET_LMASK(t0) <= 1) { | |
292 | + tmp = ldfun(GET_OFFSET(t0, 2)); | |
293 | + t1 = (t1 & 0xFFFF00FF) | (tmp << 8); | |
347 | 294 | } |
348 | 295 | |
349 | - if (GET_LMASK(T0) == 0) { | |
350 | - tmp = ldfun(GET_OFFSET(T0, 3)); | |
351 | - T1 = (T1 & 0xFFFFFF00) | tmp; | |
296 | + if (GET_LMASK(t0) == 0) { | |
297 | + tmp = ldfun(GET_OFFSET(t0, 3)); | |
298 | + t1 = (t1 & 0xFFFFFF00) | tmp; | |
352 | 299 | } |
353 | - T1 = (int32_t)T1; | |
300 | + return (int32_t)t1; | |
354 | 301 | } |
355 | 302 | |
356 | -void do_lwr(int mem_idx) | |
303 | +target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx) | |
357 | 304 | { |
358 | 305 | target_ulong tmp; |
359 | 306 | |
... | ... | @@ -370,27 +317,27 @@ void do_lwr(int mem_idx) |
370 | 317 | case 2: ldfun = ldub_user; break; |
371 | 318 | } |
372 | 319 | #endif |
373 | - tmp = ldfun(T0); | |
374 | - T1 = (T1 & 0xFFFFFF00) | tmp; | |
320 | + tmp = ldfun(t0); | |
321 | + t1 = (t1 & 0xFFFFFF00) | tmp; | |
375 | 322 | |
376 | - if (GET_LMASK(T0) >= 1) { | |
377 | - tmp = ldfun(GET_OFFSET(T0, -1)); | |
378 | - T1 = (T1 & 0xFFFF00FF) | (tmp << 8); | |
323 | + if (GET_LMASK(t0) >= 1) { | |
324 | + tmp = ldfun(GET_OFFSET(t0, -1)); | |
325 | + t1 = (t1 & 0xFFFF00FF) | (tmp << 8); | |
379 | 326 | } |
380 | 327 | |
381 | - if (GET_LMASK(T0) >= 2) { | |
382 | - tmp = ldfun(GET_OFFSET(T0, -2)); | |
383 | - T1 = (T1 & 0xFF00FFFF) | (tmp << 16); | |
328 | + if (GET_LMASK(t0) >= 2) { | |
329 | + tmp = ldfun(GET_OFFSET(t0, -2)); | |
330 | + t1 = (t1 & 0xFF00FFFF) | (tmp << 16); | |
384 | 331 | } |
385 | 332 | |
386 | - if (GET_LMASK(T0) == 3) { | |
387 | - tmp = ldfun(GET_OFFSET(T0, -3)); | |
388 | - T1 = (T1 & 0x00FFFFFF) | (tmp << 24); | |
333 | + if (GET_LMASK(t0) == 3) { | |
334 | + tmp = ldfun(GET_OFFSET(t0, -3)); | |
335 | + t1 = (t1 & 0x00FFFFFF) | (tmp << 24); | |
389 | 336 | } |
390 | - T1 = (int32_t)T1; | |
337 | + return (int32_t)t1; | |
391 | 338 | } |
392 | 339 | |
393 | -void do_swl(int mem_idx) | |
340 | +void do_swl(target_ulong t0, target_ulong t1, int mem_idx) | |
394 | 341 | { |
395 | 342 | #ifdef CONFIG_USER_ONLY |
396 | 343 | #define stfun stb_raw |
... | ... | @@ -405,19 +352,19 @@ void do_swl(int mem_idx) |
405 | 352 | case 2: stfun = stb_user; break; |
406 | 353 | } |
407 | 354 | #endif |
408 | - stfun(T0, (uint8_t)(T1 >> 24)); | |
355 | + stfun(t0, (uint8_t)(t1 >> 24)); | |
409 | 356 | |
410 | - if (GET_LMASK(T0) <= 2) | |
411 | - stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 16)); | |
357 | + if (GET_LMASK(t0) <= 2) | |
358 | + stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16)); | |
412 | 359 | |
413 | - if (GET_LMASK(T0) <= 1) | |
414 | - stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 8)); | |
360 | + if (GET_LMASK(t0) <= 1) | |
361 | + stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8)); | |
415 | 362 | |
416 | - if (GET_LMASK(T0) == 0) | |
417 | - stfun(GET_OFFSET(T0, 3), (uint8_t)T1); | |
363 | + if (GET_LMASK(t0) == 0) | |
364 | + stfun(GET_OFFSET(t0, 3), (uint8_t)t1); | |
418 | 365 | } |
419 | 366 | |
420 | -void do_swr(int mem_idx) | |
367 | +void do_swr(target_ulong t0, target_ulong t1, int mem_idx) | |
421 | 368 | { |
422 | 369 | #ifdef CONFIG_USER_ONLY |
423 | 370 | #define stfun stb_raw |
... | ... | @@ -432,16 +379,16 @@ void do_swr(int mem_idx) |
432 | 379 | case 2: stfun = stb_user; break; |
433 | 380 | } |
434 | 381 | #endif |
435 | - stfun(T0, (uint8_t)T1); | |
382 | + stfun(t0, (uint8_t)t1); | |
436 | 383 | |
437 | - if (GET_LMASK(T0) >= 1) | |
438 | - stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8)); | |
384 | + if (GET_LMASK(t0) >= 1) | |
385 | + stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8)); | |
439 | 386 | |
440 | - if (GET_LMASK(T0) >= 2) | |
441 | - stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16)); | |
387 | + if (GET_LMASK(t0) >= 2) | |
388 | + stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16)); | |
442 | 389 | |
443 | - if (GET_LMASK(T0) == 3) | |
444 | - stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24)); | |
390 | + if (GET_LMASK(t0) == 3) | |
391 | + stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24)); | |
445 | 392 | } |
446 | 393 | |
447 | 394 | #if defined(TARGET_MIPS64) |
... | ... | @@ -454,14 +401,14 @@ void do_swr(int mem_idx) |
454 | 401 | #define GET_LMASK64(v) (((v) & 7) ^ 7) |
455 | 402 | #endif |
456 | 403 | |
457 | -void do_ldl(int mem_idx) | |
404 | +target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx) | |
458 | 405 | { |
459 | 406 | uint64_t tmp; |
460 | 407 | |
461 | 408 | #ifdef CONFIG_USER_ONLY |
462 | 409 | #define ldfun ldub_raw |
463 | 410 | #else |
464 | - target_ulong (*ldfun)(target_ulong); | |
411 | + int (*ldfun)(target_ulong); | |
465 | 412 | |
466 | 413 | switch (mem_idx) |
467 | 414 | { |
... | ... | @@ -471,53 +418,55 @@ void do_ldl(int mem_idx) |
471 | 418 | case 2: ldfun = ldub_user; break; |
472 | 419 | } |
473 | 420 | #endif |
474 | - tmp = ldfun(T0); | |
475 | - T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); | |
421 | + tmp = ldfun(t0); | |
422 | + t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); | |
476 | 423 | |
477 | - if (GET_LMASK64(T0) <= 6) { | |
478 | - tmp = ldfun(GET_OFFSET(T0, 1)); | |
479 | - T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); | |
424 | + if (GET_LMASK64(t0) <= 6) { | |
425 | + tmp = ldfun(GET_OFFSET(t0, 1)); | |
426 | + t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); | |
480 | 427 | } |
481 | 428 | |
482 | - if (GET_LMASK64(T0) <= 5) { | |
483 | - tmp = ldfun(GET_OFFSET(T0, 2)); | |
484 | - T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); | |
429 | + if (GET_LMASK64(t0) <= 5) { | |
430 | + tmp = ldfun(GET_OFFSET(t0, 2)); | |
431 | + t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); | |
485 | 432 | } |
486 | 433 | |
487 | - if (GET_LMASK64(T0) <= 4) { | |
488 | - tmp = ldfun(GET_OFFSET(T0, 3)); | |
489 | - T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); | |
434 | + if (GET_LMASK64(t0) <= 4) { | |
435 | + tmp = ldfun(GET_OFFSET(t0, 3)); | |
436 | + t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); | |
490 | 437 | } |
491 | 438 | |
492 | - if (GET_LMASK64(T0) <= 3) { | |
493 | - tmp = ldfun(GET_OFFSET(T0, 4)); | |
494 | - T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); | |
439 | + if (GET_LMASK64(t0) <= 3) { | |
440 | + tmp = ldfun(GET_OFFSET(t0, 4)); | |
441 | + t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); | |
495 | 442 | } |
496 | 443 | |
497 | - if (GET_LMASK64(T0) <= 2) { | |
498 | - tmp = ldfun(GET_OFFSET(T0, 5)); | |
499 | - T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); | |
444 | + if (GET_LMASK64(t0) <= 2) { | |
445 | + tmp = ldfun(GET_OFFSET(t0, 5)); | |
446 | + t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); | |
500 | 447 | } |
501 | 448 | |
502 | - if (GET_LMASK64(T0) <= 1) { | |
503 | - tmp = ldfun(GET_OFFSET(T0, 6)); | |
504 | - T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); | |
449 | + if (GET_LMASK64(t0) <= 1) { | |
450 | + tmp = ldfun(GET_OFFSET(t0, 6)); | |
451 | + t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); | |
505 | 452 | } |
506 | 453 | |
507 | - if (GET_LMASK64(T0) == 0) { | |
508 | - tmp = ldfun(GET_OFFSET(T0, 7)); | |
509 | - T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; | |
454 | + if (GET_LMASK64(t0) == 0) { | |
455 | + tmp = ldfun(GET_OFFSET(t0, 7)); | |
456 | + t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; | |
510 | 457 | } |
458 | + | |
459 | + return t1; | |
511 | 460 | } |
512 | 461 | |
513 | -void do_ldr(int mem_idx) | |
462 | +target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx) | |
514 | 463 | { |
515 | 464 | uint64_t tmp; |
516 | 465 | |
517 | 466 | #ifdef CONFIG_USER_ONLY |
518 | 467 | #define ldfun ldub_raw |
519 | 468 | #else |
520 | - target_ulong (*ldfun)(target_ulong); | |
469 | + int (*ldfun)(target_ulong); | |
521 | 470 | |
522 | 471 | switch (mem_idx) |
523 | 472 | { |
... | ... | @@ -527,46 +476,48 @@ void do_ldr(int mem_idx) |
527 | 476 | case 2: ldfun = ldub_user; break; |
528 | 477 | } |
529 | 478 | #endif |
530 | - tmp = ldfun(T0); | |
531 | - T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; | |
479 | + tmp = ldfun(t0); | |
480 | + t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; | |
532 | 481 | |
533 | - if (GET_LMASK64(T0) >= 1) { | |
534 | - tmp = ldfun(GET_OFFSET(T0, -1)); | |
535 | - T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); | |
482 | + if (GET_LMASK64(t0) >= 1) { | |
483 | + tmp = ldfun(GET_OFFSET(t0, -1)); | |
484 | + t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); | |
536 | 485 | } |
537 | 486 | |
538 | - if (GET_LMASK64(T0) >= 2) { | |
539 | - tmp = ldfun(GET_OFFSET(T0, -2)); | |
540 | - T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); | |
487 | + if (GET_LMASK64(t0) >= 2) { | |
488 | + tmp = ldfun(GET_OFFSET(t0, -2)); | |
489 | + t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); | |
541 | 490 | } |
542 | 491 | |
543 | - if (GET_LMASK64(T0) >= 3) { | |
544 | - tmp = ldfun(GET_OFFSET(T0, -3)); | |
545 | - T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); | |
492 | + if (GET_LMASK64(t0) >= 3) { | |
493 | + tmp = ldfun(GET_OFFSET(t0, -3)); | |
494 | + t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); | |
546 | 495 | } |
547 | 496 | |
548 | - if (GET_LMASK64(T0) >= 4) { | |
549 | - tmp = ldfun(GET_OFFSET(T0, -4)); | |
550 | - T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); | |
497 | + if (GET_LMASK64(t0) >= 4) { | |
498 | + tmp = ldfun(GET_OFFSET(t0, -4)); | |
499 | + t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); | |
551 | 500 | } |
552 | 501 | |
553 | - if (GET_LMASK64(T0) >= 5) { | |
554 | - tmp = ldfun(GET_OFFSET(T0, -5)); | |
555 | - T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); | |
502 | + if (GET_LMASK64(t0) >= 5) { | |
503 | + tmp = ldfun(GET_OFFSET(t0, -5)); | |
504 | + t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); | |
556 | 505 | } |
557 | 506 | |
558 | - if (GET_LMASK64(T0) >= 6) { | |
559 | - tmp = ldfun(GET_OFFSET(T0, -6)); | |
560 | - T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); | |
507 | + if (GET_LMASK64(t0) >= 6) { | |
508 | + tmp = ldfun(GET_OFFSET(t0, -6)); | |
509 | + t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); | |
561 | 510 | } |
562 | 511 | |
563 | - if (GET_LMASK64(T0) == 7) { | |
564 | - tmp = ldfun(GET_OFFSET(T0, -7)); | |
565 | - T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); | |
512 | + if (GET_LMASK64(t0) == 7) { | |
513 | + tmp = ldfun(GET_OFFSET(t0, -7)); | |
514 | + t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); | |
566 | 515 | } |
516 | + | |
517 | + return t1; | |
567 | 518 | } |
568 | 519 | |
569 | -void do_sdl(int mem_idx) | |
520 | +void do_sdl(target_ulong t0, target_ulong t1, int mem_idx) | |
570 | 521 | { |
571 | 522 | #ifdef CONFIG_USER_ONLY |
572 | 523 | #define stfun stb_raw |
... | ... | @@ -581,31 +532,31 @@ void do_sdl(int mem_idx) |
581 | 532 | case 2: stfun = stb_user; break; |
582 | 533 | } |
583 | 534 | #endif |
584 | - stfun(T0, (uint8_t)(T1 >> 56)); | |
535 | + stfun(t0, (uint8_t)(t1 >> 56)); | |
585 | 536 | |
586 | - if (GET_LMASK64(T0) <= 6) | |
587 | - stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 48)); | |
537 | + if (GET_LMASK64(t0) <= 6) | |
538 | + stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48)); | |
588 | 539 | |
589 | - if (GET_LMASK64(T0) <= 5) | |
590 | - stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 40)); | |
540 | + if (GET_LMASK64(t0) <= 5) | |
541 | + stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40)); | |
591 | 542 | |
592 | - if (GET_LMASK64(T0) <= 4) | |
593 | - stfun(GET_OFFSET(T0, 3), (uint8_t)(T1 >> 32)); | |
543 | + if (GET_LMASK64(t0) <= 4) | |
544 | + stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32)); | |
594 | 545 | |
595 | - if (GET_LMASK64(T0) <= 3) | |
596 | - stfun(GET_OFFSET(T0, 4), (uint8_t)(T1 >> 24)); | |
546 | + if (GET_LMASK64(t0) <= 3) | |
547 | + stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24)); | |
597 | 548 | |
598 | - if (GET_LMASK64(T0) <= 2) | |
599 | - stfun(GET_OFFSET(T0, 5), (uint8_t)(T1 >> 16)); | |
549 | + if (GET_LMASK64(t0) <= 2) | |
550 | + stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16)); | |
600 | 551 | |
601 | - if (GET_LMASK64(T0) <= 1) | |
602 | - stfun(GET_OFFSET(T0, 6), (uint8_t)(T1 >> 8)); | |
552 | + if (GET_LMASK64(t0) <= 1) | |
553 | + stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8)); | |
603 | 554 | |
604 | - if (GET_LMASK64(T0) <= 0) | |
605 | - stfun(GET_OFFSET(T0, 7), (uint8_t)T1); | |
555 | + if (GET_LMASK64(t0) <= 0) | |
556 | + stfun(GET_OFFSET(t0, 7), (uint8_t)t1); | |
606 | 557 | } |
607 | 558 | |
608 | -void do_sdr(int mem_idx) | |
559 | +void do_sdr(target_ulong t0, target_ulong t1, int mem_idx) | |
609 | 560 | { |
610 | 561 | #ifdef CONFIG_USER_ONLY |
611 | 562 | #define stfun stb_raw |
... | ... | @@ -620,28 +571,28 @@ void do_sdr(int mem_idx) |
620 | 571 | case 2: stfun = stb_user; break; |
621 | 572 | } |
622 | 573 | #endif |
623 | - stfun(T0, (uint8_t)T1); | |
574 | + stfun(t0, (uint8_t)t1); | |
624 | 575 | |
625 | - if (GET_LMASK64(T0) >= 1) | |
626 | - stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8)); | |
576 | + if (GET_LMASK64(t0) >= 1) | |
577 | + stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8)); | |
627 | 578 | |
628 | - if (GET_LMASK64(T0) >= 2) | |
629 | - stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16)); | |
579 | + if (GET_LMASK64(t0) >= 2) | |
580 | + stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16)); | |
630 | 581 | |
631 | - if (GET_LMASK64(T0) >= 3) | |
632 | - stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24)); | |
582 | + if (GET_LMASK64(t0) >= 3) | |
583 | + stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24)); | |
633 | 584 | |
634 | - if (GET_LMASK64(T0) >= 4) | |
635 | - stfun(GET_OFFSET(T0, -4), (uint8_t)(T1 >> 32)); | |
585 | + if (GET_LMASK64(t0) >= 4) | |
586 | + stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32)); | |
636 | 587 | |
637 | - if (GET_LMASK64(T0) >= 5) | |
638 | - stfun(GET_OFFSET(T0, -5), (uint8_t)(T1 >> 40)); | |
588 | + if (GET_LMASK64(t0) >= 5) | |
589 | + stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40)); | |
639 | 590 | |
640 | - if (GET_LMASK64(T0) >= 6) | |
641 | - stfun(GET_OFFSET(T0, -6), (uint8_t)(T1 >> 48)); | |
591 | + if (GET_LMASK64(t0) >= 6) | |
592 | + stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48)); | |
642 | 593 | |
643 | - if (GET_LMASK64(T0) == 7) | |
644 | - stfun(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56)); | |
594 | + if (GET_LMASK64(t0) == 7) | |
595 | + stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56)); | |
645 | 596 | } |
646 | 597 | #endif /* TARGET_MIPS64 */ |
647 | 598 | |
... | ... | @@ -699,203 +650,207 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
699 | 650 | #else |
700 | 651 | |
701 | 652 | /* CP0 helpers */ |
702 | -void do_mfc0_mvpcontrol (void) | |
653 | +target_ulong do_mfc0_mvpcontrol (target_ulong t0) | |
703 | 654 | { |
704 | - T0 = env->mvp->CP0_MVPControl; | |
655 | + return env->mvp->CP0_MVPControl; | |
705 | 656 | } |
706 | 657 | |
707 | -void do_mfc0_mvpconf0 (void) | |
658 | +target_ulong do_mfc0_mvpconf0 (target_ulong t0) | |
708 | 659 | { |
709 | - T0 = env->mvp->CP0_MVPConf0; | |
660 | + return env->mvp->CP0_MVPConf0; | |
710 | 661 | } |
711 | 662 | |
712 | -void do_mfc0_mvpconf1 (void) | |
663 | +target_ulong do_mfc0_mvpconf1 (target_ulong t0) | |
713 | 664 | { |
714 | - T0 = env->mvp->CP0_MVPConf1; | |
665 | + return env->mvp->CP0_MVPConf1; | |
715 | 666 | } |
716 | 667 | |
717 | -void do_mfc0_random (void) | |
668 | +target_ulong do_mfc0_random (target_ulong t0) | |
718 | 669 | { |
719 | - T0 = (int32_t)cpu_mips_get_random(env); | |
670 | + return (int32_t)cpu_mips_get_random(env); | |
720 | 671 | } |
721 | 672 | |
722 | -void do_mfc0_tcstatus (void) | |
673 | +target_ulong do_mfc0_tcstatus (target_ulong t0) | |
723 | 674 | { |
724 | - T0 = env->CP0_TCStatus[env->current_tc]; | |
675 | + return env->CP0_TCStatus[env->current_tc]; | |
725 | 676 | } |
726 | 677 | |
727 | -void do_mftc0_tcstatus(void) | |
678 | +target_ulong do_mftc0_tcstatus(target_ulong t0) | |
728 | 679 | { |
729 | 680 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
730 | 681 | |
731 | - T0 = env->CP0_TCStatus[other_tc]; | |
682 | + return env->CP0_TCStatus[other_tc]; | |
732 | 683 | } |
733 | 684 | |
734 | -void do_mfc0_tcbind (void) | |
685 | +target_ulong do_mfc0_tcbind (target_ulong t0) | |
735 | 686 | { |
736 | - T0 = env->CP0_TCBind[env->current_tc]; | |
687 | + return env->CP0_TCBind[env->current_tc]; | |
737 | 688 | } |
738 | 689 | |
739 | -void do_mftc0_tcbind(void) | |
690 | +target_ulong do_mftc0_tcbind(target_ulong t0) | |
740 | 691 | { |
741 | 692 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
742 | 693 | |
743 | - T0 = env->CP0_TCBind[other_tc]; | |
694 | + return env->CP0_TCBind[other_tc]; | |
744 | 695 | } |
745 | 696 | |
746 | -void do_mfc0_tcrestart (void) | |
697 | +target_ulong do_mfc0_tcrestart (target_ulong t0) | |
747 | 698 | { |
748 | - T0 = env->PC[env->current_tc]; | |
699 | + return env->PC[env->current_tc]; | |
749 | 700 | } |
750 | 701 | |
751 | -void do_mftc0_tcrestart(void) | |
702 | +target_ulong do_mftc0_tcrestart(target_ulong t0) | |
752 | 703 | { |
753 | 704 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
754 | 705 | |
755 | - T0 = env->PC[other_tc]; | |
706 | + return env->PC[other_tc]; | |
756 | 707 | } |
757 | 708 | |
758 | -void do_mfc0_tchalt (void) | |
709 | +target_ulong do_mfc0_tchalt (target_ulong t0) | |
759 | 710 | { |
760 | - T0 = env->CP0_TCHalt[env->current_tc]; | |
711 | + return env->CP0_TCHalt[env->current_tc]; | |
761 | 712 | } |
762 | 713 | |
763 | -void do_mftc0_tchalt(void) | |
714 | +target_ulong do_mftc0_tchalt(target_ulong t0) | |
764 | 715 | { |
765 | 716 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
766 | 717 | |
767 | - T0 = env->CP0_TCHalt[other_tc]; | |
718 | + return env->CP0_TCHalt[other_tc]; | |
768 | 719 | } |
769 | 720 | |
770 | -void do_mfc0_tccontext (void) | |
721 | +target_ulong do_mfc0_tccontext (target_ulong t0) | |
771 | 722 | { |
772 | - T0 = env->CP0_TCContext[env->current_tc]; | |
723 | + return env->CP0_TCContext[env->current_tc]; | |
773 | 724 | } |
774 | 725 | |
775 | -void do_mftc0_tccontext(void) | |
726 | +target_ulong do_mftc0_tccontext(target_ulong t0) | |
776 | 727 | { |
777 | 728 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
778 | 729 | |
779 | - T0 = env->CP0_TCContext[other_tc]; | |
730 | + return env->CP0_TCContext[other_tc]; | |
780 | 731 | } |
781 | 732 | |
782 | -void do_mfc0_tcschedule (void) | |
733 | +target_ulong do_mfc0_tcschedule (target_ulong t0) | |
783 | 734 | { |
784 | - T0 = env->CP0_TCSchedule[env->current_tc]; | |
735 | + return env->CP0_TCSchedule[env->current_tc]; | |
785 | 736 | } |
786 | 737 | |
787 | -void do_mftc0_tcschedule(void) | |
738 | +target_ulong do_mftc0_tcschedule(target_ulong t0) | |
788 | 739 | { |
789 | 740 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
790 | 741 | |
791 | - T0 = env->CP0_TCSchedule[other_tc]; | |
742 | + return env->CP0_TCSchedule[other_tc]; | |
792 | 743 | } |
793 | 744 | |
794 | -void do_mfc0_tcschefback (void) | |
745 | +target_ulong do_mfc0_tcschefback (target_ulong t0) | |
795 | 746 | { |
796 | - T0 = env->CP0_TCScheFBack[env->current_tc]; | |
747 | + return env->CP0_TCScheFBack[env->current_tc]; | |
797 | 748 | } |
798 | 749 | |
799 | -void do_mftc0_tcschefback(void) | |
750 | +target_ulong do_mftc0_tcschefback(target_ulong t0) | |
800 | 751 | { |
801 | 752 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
802 | 753 | |
803 | - T0 = env->CP0_TCScheFBack[other_tc]; | |
754 | + return env->CP0_TCScheFBack[other_tc]; | |
804 | 755 | } |
805 | 756 | |
806 | -void do_mfc0_count (void) | |
757 | +target_ulong do_mfc0_count (target_ulong t0) | |
807 | 758 | { |
808 | - T0 = (int32_t)cpu_mips_get_count(env); | |
759 | + return (int32_t)cpu_mips_get_count(env); | |
809 | 760 | } |
810 | 761 | |
811 | -void do_mftc0_entryhi(void) | |
762 | +target_ulong do_mftc0_entryhi(target_ulong t0) | |
812 | 763 | { |
813 | 764 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
814 | 765 | |
815 | - T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); | |
766 | + return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); | |
816 | 767 | } |
817 | 768 | |
818 | -void do_mftc0_status(void) | |
769 | +target_ulong do_mftc0_status(target_ulong t0) | |
819 | 770 | { |
820 | 771 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
821 | 772 | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
822 | 773 | |
823 | - T0 = env->CP0_Status & ~0xf1000018; | |
824 | - T0 |= tcstatus & (0xf << CP0TCSt_TCU0); | |
825 | - T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); | |
826 | - T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); | |
774 | + t0 = env->CP0_Status & ~0xf1000018; | |
775 | + t0 |= tcstatus & (0xf << CP0TCSt_TCU0); | |
776 | + t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); | |
777 | + t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); | |
778 | + | |
779 | + return t0; | |
827 | 780 | } |
828 | 781 | |
829 | -void do_mfc0_lladdr (void) | |
782 | +target_ulong do_mfc0_lladdr (target_ulong t0) | |
830 | 783 | { |
831 | - T0 = (int32_t)env->CP0_LLAddr >> 4; | |
784 | + return (int32_t)env->CP0_LLAddr >> 4; | |
832 | 785 | } |
833 | 786 | |
834 | -void do_mfc0_watchlo (uint32_t sel) | |
787 | +target_ulong do_mfc0_watchlo (target_ulong t0, uint32_t sel) | |
835 | 788 | { |
836 | - T0 = (int32_t)env->CP0_WatchLo[sel]; | |
789 | + return (int32_t)env->CP0_WatchLo[sel]; | |
837 | 790 | } |
838 | 791 | |
839 | -void do_mfc0_watchhi (uint32_t sel) | |
792 | +target_ulong do_mfc0_watchhi (target_ulong t0, uint32_t sel) | |
840 | 793 | { |
841 | - T0 = env->CP0_WatchHi[sel]; | |
794 | + return env->CP0_WatchHi[sel]; | |
842 | 795 | } |
843 | 796 | |
844 | -void do_mfc0_debug (void) | |
797 | +target_ulong do_mfc0_debug (target_ulong t0) | |
845 | 798 | { |
846 | - T0 = env->CP0_Debug; | |
799 | + t0 = env->CP0_Debug; | |
847 | 800 | if (env->hflags & MIPS_HFLAG_DM) |
848 | - T0 |= 1 << CP0DB_DM; | |
801 | + t0 |= 1 << CP0DB_DM; | |
802 | + | |
803 | + return t0; | |
849 | 804 | } |
850 | 805 | |
851 | -void do_mftc0_debug(void) | |
806 | +target_ulong do_mftc0_debug(target_ulong t0) | |
852 | 807 | { |
853 | 808 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
854 | 809 | |
855 | 810 | /* XXX: Might be wrong, check with EJTAG spec. */ |
856 | - T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | | |
857 | - (env->CP0_Debug_tcstatus[other_tc] & | |
858 | - ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); | |
811 | + return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | | |
812 | + (env->CP0_Debug_tcstatus[other_tc] & | |
813 | + ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); | |
859 | 814 | } |
860 | 815 | |
861 | 816 | #if defined(TARGET_MIPS64) |
862 | -void do_dmfc0_tcrestart (void) | |
817 | +target_ulong do_dmfc0_tcrestart (target_ulong t0) | |
863 | 818 | { |
864 | - T0 = env->PC[env->current_tc]; | |
819 | + return env->PC[env->current_tc]; | |
865 | 820 | } |
866 | 821 | |
867 | -void do_dmfc0_tchalt (void) | |
822 | +target_ulong do_dmfc0_tchalt (target_ulong t0) | |
868 | 823 | { |
869 | - T0 = env->CP0_TCHalt[env->current_tc]; | |
824 | + return env->CP0_TCHalt[env->current_tc]; | |
870 | 825 | } |
871 | 826 | |
872 | -void do_dmfc0_tccontext (void) | |
827 | +target_ulong do_dmfc0_tccontext (target_ulong t0) | |
873 | 828 | { |
874 | - T0 = env->CP0_TCContext[env->current_tc]; | |
829 | + return env->CP0_TCContext[env->current_tc]; | |
875 | 830 | } |
876 | 831 | |
877 | -void do_dmfc0_tcschedule (void) | |
832 | +target_ulong do_dmfc0_tcschedule (target_ulong t0) | |
878 | 833 | { |
879 | - T0 = env->CP0_TCSchedule[env->current_tc]; | |
834 | + return env->CP0_TCSchedule[env->current_tc]; | |
880 | 835 | } |
881 | 836 | |
882 | -void do_dmfc0_tcschefback (void) | |
837 | +target_ulong do_dmfc0_tcschefback (target_ulong t0) | |
883 | 838 | { |
884 | - T0 = env->CP0_TCScheFBack[env->current_tc]; | |
839 | + return env->CP0_TCScheFBack[env->current_tc]; | |
885 | 840 | } |
886 | 841 | |
887 | -void do_dmfc0_lladdr (void) | |
842 | +target_ulong do_dmfc0_lladdr (target_ulong t0) | |
888 | 843 | { |
889 | - T0 = env->CP0_LLAddr >> 4; | |
844 | + return env->CP0_LLAddr >> 4; | |
890 | 845 | } |
891 | 846 | |
892 | -void do_dmfc0_watchlo (uint32_t sel) | |
847 | +target_ulong do_dmfc0_watchlo (target_ulong t0, uint32_t sel) | |
893 | 848 | { |
894 | - T0 = env->CP0_WatchLo[sel]; | |
849 | + return env->CP0_WatchLo[sel]; | |
895 | 850 | } |
896 | 851 | #endif /* TARGET_MIPS64 */ |
897 | 852 | |
898 | -void do_mtc0_index (void) | |
853 | +void do_mtc0_index (target_ulong t0) | |
899 | 854 | { |
900 | 855 | int num = 1; |
901 | 856 | unsigned int tmp = env->tlb->nb_tlb; |
... | ... | @@ -904,10 +859,10 @@ void do_mtc0_index (void) |
904 | 859 | tmp >>= 1; |
905 | 860 | num <<= 1; |
906 | 861 | } while (tmp); |
907 | - env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1)); | |
862 | + env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1)); | |
908 | 863 | } |
909 | 864 | |
910 | -void do_mtc0_mvpcontrol (void) | |
865 | +void do_mtc0_mvpcontrol (target_ulong t0) | |
911 | 866 | { |
912 | 867 | uint32_t mask = 0; |
913 | 868 | uint32_t newval; |
... | ... | @@ -917,21 +872,21 @@ void do_mtc0_mvpcontrol (void) |
917 | 872 | (1 << CP0MVPCo_EVP); |
918 | 873 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
919 | 874 | mask |= (1 << CP0MVPCo_STLB); |
920 | - newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); | |
875 | + newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask); | |
921 | 876 | |
922 | 877 | // TODO: Enable/disable shared TLB, enable/disable VPEs. |
923 | 878 | |
924 | 879 | env->mvp->CP0_MVPControl = newval; |
925 | 880 | } |
926 | 881 | |
927 | -void do_mtc0_vpecontrol (void) | |
882 | +void do_mtc0_vpecontrol (target_ulong t0) | |
928 | 883 | { |
929 | 884 | uint32_t mask; |
930 | 885 | uint32_t newval; |
931 | 886 | |
932 | 887 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
933 | 888 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
934 | - newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); | |
889 | + newval = (env->CP0_VPEControl & ~mask) | (t0 & mask); | |
935 | 890 | |
936 | 891 | /* Yield scheduler intercept not implemented. */ |
937 | 892 | /* Gating storage scheduler intercept not implemented. */ |
... | ... | @@ -941,7 +896,7 @@ void do_mtc0_vpecontrol (void) |
941 | 896 | env->CP0_VPEControl = newval; |
942 | 897 | } |
943 | 898 | |
944 | -void do_mtc0_vpeconf0 (void) | |
899 | +void do_mtc0_vpeconf0 (target_ulong t0) | |
945 | 900 | { |
946 | 901 | uint32_t mask = 0; |
947 | 902 | uint32_t newval; |
... | ... | @@ -951,14 +906,14 @@ void do_mtc0_vpeconf0 (void) |
951 | 906 | mask |= (0xff << CP0VPEC0_XTC); |
952 | 907 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
953 | 908 | } |
954 | - newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); | |
909 | + newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask); | |
955 | 910 | |
956 | 911 | // TODO: TC exclusive handling due to ERL/EXL. |
957 | 912 | |
958 | 913 | env->CP0_VPEConf0 = newval; |
959 | 914 | } |
960 | 915 | |
961 | -void do_mtc0_vpeconf1 (void) | |
916 | +void do_mtc0_vpeconf1 (target_ulong t0) | |
962 | 917 | { |
963 | 918 | uint32_t mask = 0; |
964 | 919 | uint32_t newval; |
... | ... | @@ -966,7 +921,7 @@ void do_mtc0_vpeconf1 (void) |
966 | 921 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
967 | 922 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
968 | 923 | (0xff << CP0VPEC1_NCP1); |
969 | - newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); | |
924 | + newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask); | |
970 | 925 | |
971 | 926 | /* UDI not implemented. */ |
972 | 927 | /* CP2 not implemented. */ |
... | ... | @@ -976,57 +931,57 @@ void do_mtc0_vpeconf1 (void) |
976 | 931 | env->CP0_VPEConf1 = newval; |
977 | 932 | } |
978 | 933 | |
979 | -void do_mtc0_yqmask (void) | |
934 | +void do_mtc0_yqmask (target_ulong t0) | |
980 | 935 | { |
981 | 936 | /* Yield qualifier inputs not implemented. */ |
982 | 937 | env->CP0_YQMask = 0x00000000; |
983 | 938 | } |
984 | 939 | |
985 | -void do_mtc0_vpeopt (void) | |
940 | +void do_mtc0_vpeopt (target_ulong t0) | |
986 | 941 | { |
987 | - env->CP0_VPEOpt = T0 & 0x0000ffff; | |
942 | + env->CP0_VPEOpt = t0 & 0x0000ffff; | |
988 | 943 | } |
989 | 944 | |
990 | -void do_mtc0_entrylo0 (void) | |
945 | +void do_mtc0_entrylo0 (target_ulong t0) | |
991 | 946 | { |
992 | 947 | /* Large physaddr (PABITS) not implemented */ |
993 | 948 | /* 1k pages not implemented */ |
994 | - env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; | |
949 | + env->CP0_EntryLo0 = t0 & 0x3FFFFFFF; | |
995 | 950 | } |
996 | 951 | |
997 | -void do_mtc0_tcstatus (void) | |
952 | +void do_mtc0_tcstatus (target_ulong t0) | |
998 | 953 | { |
999 | 954 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
1000 | 955 | uint32_t newval; |
1001 | 956 | |
1002 | - newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); | |
957 | + newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (t0 & mask); | |
1003 | 958 | |
1004 | 959 | // TODO: Sync with CP0_Status. |
1005 | 960 | |
1006 | 961 | env->CP0_TCStatus[env->current_tc] = newval; |
1007 | 962 | } |
1008 | 963 | |
1009 | -void do_mttc0_tcstatus (void) | |
964 | +void do_mttc0_tcstatus (target_ulong t0) | |
1010 | 965 | { |
1011 | 966 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1012 | 967 | |
1013 | 968 | // TODO: Sync with CP0_Status. |
1014 | 969 | |
1015 | - env->CP0_TCStatus[other_tc] = T0; | |
970 | + env->CP0_TCStatus[other_tc] = t0; | |
1016 | 971 | } |
1017 | 972 | |
1018 | -void do_mtc0_tcbind (void) | |
973 | +void do_mtc0_tcbind (target_ulong t0) | |
1019 | 974 | { |
1020 | 975 | uint32_t mask = (1 << CP0TCBd_TBE); |
1021 | 976 | uint32_t newval; |
1022 | 977 | |
1023 | 978 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1024 | 979 | mask |= (1 << CP0TCBd_CurVPE); |
1025 | - newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); | |
980 | + newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (t0 & mask); | |
1026 | 981 | env->CP0_TCBind[env->current_tc] = newval; |
1027 | 982 | } |
1028 | 983 | |
1029 | -void do_mttc0_tcbind (void) | |
984 | +void do_mttc0_tcbind (target_ulong t0) | |
1030 | 985 | { |
1031 | 986 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1032 | 987 | uint32_t mask = (1 << CP0TCBd_TBE); |
... | ... | @@ -1034,99 +989,99 @@ void do_mttc0_tcbind (void) |
1034 | 989 | |
1035 | 990 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1036 | 991 | mask |= (1 << CP0TCBd_CurVPE); |
1037 | - newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); | |
992 | + newval = (env->CP0_TCBind[other_tc] & ~mask) | (t0 & mask); | |
1038 | 993 | env->CP0_TCBind[other_tc] = newval; |
1039 | 994 | } |
1040 | 995 | |
1041 | -void do_mtc0_tcrestart (void) | |
996 | +void do_mtc0_tcrestart (target_ulong t0) | |
1042 | 997 | { |
1043 | - env->PC[env->current_tc] = T0; | |
998 | + env->PC[env->current_tc] = t0; | |
1044 | 999 | env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS); |
1045 | 1000 | env->CP0_LLAddr = 0ULL; |
1046 | 1001 | /* MIPS16 not implemented. */ |
1047 | 1002 | } |
1048 | 1003 | |
1049 | -void do_mttc0_tcrestart (void) | |
1004 | +void do_mttc0_tcrestart (target_ulong t0) | |
1050 | 1005 | { |
1051 | 1006 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1052 | 1007 | |
1053 | - env->PC[other_tc] = T0; | |
1008 | + env->PC[other_tc] = t0; | |
1054 | 1009 | env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS); |
1055 | 1010 | env->CP0_LLAddr = 0ULL; |
1056 | 1011 | /* MIPS16 not implemented. */ |
1057 | 1012 | } |
1058 | 1013 | |
1059 | -void do_mtc0_tchalt (void) | |
1014 | +void do_mtc0_tchalt (target_ulong t0) | |
1060 | 1015 | { |
1061 | - env->CP0_TCHalt[env->current_tc] = T0 & 0x1; | |
1016 | + env->CP0_TCHalt[env->current_tc] = t0 & 0x1; | |
1062 | 1017 | |
1063 | 1018 | // TODO: Halt TC / Restart (if allocated+active) TC. |
1064 | 1019 | } |
1065 | 1020 | |
1066 | -void do_mttc0_tchalt (void) | |
1021 | +void do_mttc0_tchalt (target_ulong t0) | |
1067 | 1022 | { |
1068 | 1023 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1069 | 1024 | |
1070 | 1025 | // TODO: Halt TC / Restart (if allocated+active) TC. |
1071 | 1026 | |
1072 | - env->CP0_TCHalt[other_tc] = T0; | |
1027 | + env->CP0_TCHalt[other_tc] = t0; | |
1073 | 1028 | } |
1074 | 1029 | |
1075 | -void do_mtc0_tccontext (void) | |
1030 | +void do_mtc0_tccontext (target_ulong t0) | |
1076 | 1031 | { |
1077 | - env->CP0_TCContext[env->current_tc] = T0; | |
1032 | + env->CP0_TCContext[env->current_tc] = t0; | |
1078 | 1033 | } |
1079 | 1034 | |
1080 | -void do_mttc0_tccontext (void) | |
1035 | +void do_mttc0_tccontext (target_ulong t0) | |
1081 | 1036 | { |
1082 | 1037 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1083 | 1038 | |
1084 | - env->CP0_TCContext[other_tc] = T0; | |
1039 | + env->CP0_TCContext[other_tc] = t0; | |
1085 | 1040 | } |
1086 | 1041 | |
1087 | -void do_mtc0_tcschedule (void) | |
1042 | +void do_mtc0_tcschedule (target_ulong t0) | |
1088 | 1043 | { |
1089 | - env->CP0_TCSchedule[env->current_tc] = T0; | |
1044 | + env->CP0_TCSchedule[env->current_tc] = t0; | |
1090 | 1045 | } |
1091 | 1046 | |
1092 | -void do_mttc0_tcschedule (void) | |
1047 | +void do_mttc0_tcschedule (target_ulong t0) | |
1093 | 1048 | { |
1094 | 1049 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1095 | 1050 | |
1096 | - env->CP0_TCSchedule[other_tc] = T0; | |
1051 | + env->CP0_TCSchedule[other_tc] = t0; | |
1097 | 1052 | } |
1098 | 1053 | |
1099 | -void do_mtc0_tcschefback (void) | |
1054 | +void do_mtc0_tcschefback (target_ulong t0) | |
1100 | 1055 | { |
1101 | - env->CP0_TCScheFBack[env->current_tc] = T0; | |
1056 | + env->CP0_TCScheFBack[env->current_tc] = t0; | |
1102 | 1057 | } |
1103 | 1058 | |
1104 | -void do_mttc0_tcschefback (void) | |
1059 | +void do_mttc0_tcschefback (target_ulong t0) | |
1105 | 1060 | { |
1106 | 1061 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1107 | 1062 | |
1108 | - env->CP0_TCScheFBack[other_tc] = T0; | |
1063 | + env->CP0_TCScheFBack[other_tc] = t0; | |
1109 | 1064 | } |
1110 | 1065 | |
1111 | -void do_mtc0_entrylo1 (void) | |
1066 | +void do_mtc0_entrylo1 (target_ulong t0) | |
1112 | 1067 | { |
1113 | 1068 | /* Large physaddr (PABITS) not implemented */ |
1114 | 1069 | /* 1k pages not implemented */ |
1115 | - env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; | |
1070 | + env->CP0_EntryLo1 = t0 & 0x3FFFFFFF; | |
1116 | 1071 | } |
1117 | 1072 | |
1118 | -void do_mtc0_context (void) | |
1073 | +void do_mtc0_context (target_ulong t0) | |
1119 | 1074 | { |
1120 | - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); | |
1075 | + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF); | |
1121 | 1076 | } |
1122 | 1077 | |
1123 | -void do_mtc0_pagemask (void) | |
1078 | +void do_mtc0_pagemask (target_ulong t0) | |
1124 | 1079 | { |
1125 | 1080 | /* 1k pages not implemented */ |
1126 | - env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); | |
1081 | + env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); | |
1127 | 1082 | } |
1128 | 1083 | |
1129 | -void do_mtc0_pagegrain (void) | |
1084 | +void do_mtc0_pagegrain (target_ulong t0) | |
1130 | 1085 | { |
1131 | 1086 | /* SmartMIPS not implemented */ |
1132 | 1087 | /* Large physaddr (PABITS) not implemented */ |
... | ... | @@ -1134,52 +1089,52 @@ void do_mtc0_pagegrain (void) |
1134 | 1089 | env->CP0_PageGrain = 0; |
1135 | 1090 | } |
1136 | 1091 | |
1137 | -void do_mtc0_wired (void) | |
1092 | +void do_mtc0_wired (target_ulong t0) | |
1138 | 1093 | { |
1139 | - env->CP0_Wired = T0 % env->tlb->nb_tlb; | |
1094 | + env->CP0_Wired = t0 % env->tlb->nb_tlb; | |
1140 | 1095 | } |
1141 | 1096 | |
1142 | -void do_mtc0_srsconf0 (void) | |
1097 | +void do_mtc0_srsconf0 (target_ulong t0) | |
1143 | 1098 | { |
1144 | - env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; | |
1099 | + env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask; | |
1145 | 1100 | } |
1146 | 1101 | |
1147 | -void do_mtc0_srsconf1 (void) | |
1102 | +void do_mtc0_srsconf1 (target_ulong t0) | |
1148 | 1103 | { |
1149 | - env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; | |
1104 | + env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask; | |
1150 | 1105 | } |
1151 | 1106 | |
1152 | -void do_mtc0_srsconf2 (void) | |
1107 | +void do_mtc0_srsconf2 (target_ulong t0) | |
1153 | 1108 | { |
1154 | - env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; | |
1109 | + env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask; | |
1155 | 1110 | } |
1156 | 1111 | |
1157 | -void do_mtc0_srsconf3 (void) | |
1112 | +void do_mtc0_srsconf3 (target_ulong t0) | |
1158 | 1113 | { |
1159 | - env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; | |
1114 | + env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask; | |
1160 | 1115 | } |
1161 | 1116 | |
1162 | -void do_mtc0_srsconf4 (void) | |
1117 | +void do_mtc0_srsconf4 (target_ulong t0) | |
1163 | 1118 | { |
1164 | - env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; | |
1119 | + env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask; | |
1165 | 1120 | } |
1166 | 1121 | |
1167 | -void do_mtc0_hwrena (void) | |
1122 | +void do_mtc0_hwrena (target_ulong t0) | |
1168 | 1123 | { |
1169 | - env->CP0_HWREna = T0 & 0x0000000F; | |
1124 | + env->CP0_HWREna = t0 & 0x0000000F; | |
1170 | 1125 | } |
1171 | 1126 | |
1172 | -void do_mtc0_count (void) | |
1127 | +void do_mtc0_count (target_ulong t0) | |
1173 | 1128 | { |
1174 | - cpu_mips_store_count(env, T0); | |
1129 | + cpu_mips_store_count(env, t0); | |
1175 | 1130 | } |
1176 | 1131 | |
1177 | -void do_mtc0_entryhi (void) | |
1132 | +void do_mtc0_entryhi (target_ulong t0) | |
1178 | 1133 | { |
1179 | 1134 | target_ulong old, val; |
1180 | 1135 | |
1181 | 1136 | /* 1k pages not implemented */ |
1182 | - val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); | |
1137 | + val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF); | |
1183 | 1138 | #if defined(TARGET_MIPS64) |
1184 | 1139 | val &= env->SEGMask; |
1185 | 1140 | #endif |
... | ... | @@ -1194,25 +1149,25 @@ void do_mtc0_entryhi (void) |
1194 | 1149 | cpu_mips_tlb_flush(env, 1); |
1195 | 1150 | } |
1196 | 1151 | |
1197 | -void do_mttc0_entryhi(void) | |
1152 | +void do_mttc0_entryhi(target_ulong t0) | |
1198 | 1153 | { |
1199 | 1154 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1200 | 1155 | |
1201 | - env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff); | |
1202 | - env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); | |
1156 | + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff); | |
1157 | + env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (t0 & 0xff); | |
1203 | 1158 | } |
1204 | 1159 | |
1205 | -void do_mtc0_compare (void) | |
1160 | +void do_mtc0_compare (target_ulong t0) | |
1206 | 1161 | { |
1207 | - cpu_mips_store_compare(env, T0); | |
1162 | + cpu_mips_store_compare(env, t0); | |
1208 | 1163 | } |
1209 | 1164 | |
1210 | -void do_mtc0_status (void) | |
1165 | +void do_mtc0_status (target_ulong t0) | |
1211 | 1166 | { |
1212 | 1167 | uint32_t val, old; |
1213 | 1168 | uint32_t mask = env->CP0_Status_rw_bitmask; |
1214 | 1169 | |
1215 | - val = T0 & mask; | |
1170 | + val = t0 & mask; | |
1216 | 1171 | old = env->CP0_Status; |
1217 | 1172 | env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1218 | 1173 | compute_hflags(env); |
... | ... | @@ -1221,31 +1176,31 @@ void do_mtc0_status (void) |
1221 | 1176 | cpu_mips_update_irq(env); |
1222 | 1177 | } |
1223 | 1178 | |
1224 | -void do_mttc0_status(void) | |
1179 | +void do_mttc0_status(target_ulong t0) | |
1225 | 1180 | { |
1226 | 1181 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1227 | 1182 | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
1228 | 1183 | |
1229 | - env->CP0_Status = T0 & ~0xf1000018; | |
1230 | - tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0)); | |
1231 | - tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); | |
1232 | - tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); | |
1184 | + env->CP0_Status = t0 & ~0xf1000018; | |
1185 | + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0)); | |
1186 | + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); | |
1187 | + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); | |
1233 | 1188 | env->CP0_TCStatus[other_tc] = tcstatus; |
1234 | 1189 | } |
1235 | 1190 | |
1236 | -void do_mtc0_intctl (void) | |
1191 | +void do_mtc0_intctl (target_ulong t0) | |
1237 | 1192 | { |
1238 | 1193 | /* vectored interrupts not implemented, no performance counters. */ |
1239 | - env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); | |
1194 | + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0); | |
1240 | 1195 | } |
1241 | 1196 | |
1242 | -void do_mtc0_srsctl (void) | |
1197 | +void do_mtc0_srsctl (target_ulong t0) | |
1243 | 1198 | { |
1244 | 1199 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
1245 | - env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); | |
1200 | + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask); | |
1246 | 1201 | } |
1247 | 1202 | |
1248 | -void do_mtc0_cause (void) | |
1203 | +void do_mtc0_cause (target_ulong t0) | |
1249 | 1204 | { |
1250 | 1205 | uint32_t mask = 0x00C00300; |
1251 | 1206 | uint32_t old = env->CP0_Cause; |
... | ... | @@ -1253,7 +1208,7 @@ void do_mtc0_cause (void) |
1253 | 1208 | if (env->insn_flags & ISA_MIPS32R2) |
1254 | 1209 | mask |= 1 << CP0Ca_DC; |
1255 | 1210 | |
1256 | - env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); | |
1211 | + env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask); | |
1257 | 1212 | |
1258 | 1213 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { |
1259 | 1214 | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
... | ... | @@ -1264,95 +1219,95 @@ void do_mtc0_cause (void) |
1264 | 1219 | |
1265 | 1220 | /* Handle the software interrupt as an hardware one, as they |
1266 | 1221 | are very similar */ |
1267 | - if (T0 & CP0Ca_IP_mask) { | |
1222 | + if (t0 & CP0Ca_IP_mask) { | |
1268 | 1223 | cpu_mips_update_irq(env); |
1269 | 1224 | } |
1270 | 1225 | } |
1271 | 1226 | |
1272 | -void do_mtc0_ebase (void) | |
1227 | +void do_mtc0_ebase (target_ulong t0) | |
1273 | 1228 | { |
1274 | 1229 | /* vectored interrupts not implemented */ |
1275 | 1230 | /* Multi-CPU not implemented */ |
1276 | - env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); | |
1231 | + env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000); | |
1277 | 1232 | } |
1278 | 1233 | |
1279 | -void do_mtc0_config0 (void) | |
1234 | +void do_mtc0_config0 (target_ulong t0) | |
1280 | 1235 | { |
1281 | - env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); | |
1236 | + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007); | |
1282 | 1237 | } |
1283 | 1238 | |
1284 | -void do_mtc0_config2 (void) | |
1239 | +void do_mtc0_config2 (target_ulong t0) | |
1285 | 1240 | { |
1286 | 1241 | /* tertiary/secondary caches not implemented */ |
1287 | 1242 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); |
1288 | 1243 | } |
1289 | 1244 | |
1290 | -void do_mtc0_watchlo (uint32_t sel) | |
1245 | +void do_mtc0_watchlo (target_ulong t0, uint32_t sel) | |
1291 | 1246 | { |
1292 | 1247 | /* Watch exceptions for instructions, data loads, data stores |
1293 | 1248 | not implemented. */ |
1294 | - env->CP0_WatchLo[sel] = (T0 & ~0x7); | |
1249 | + env->CP0_WatchLo[sel] = (t0 & ~0x7); | |
1295 | 1250 | } |
1296 | 1251 | |
1297 | -void do_mtc0_watchhi (uint32_t sel) | |
1252 | +void do_mtc0_watchhi (target_ulong t0, uint32_t sel) | |
1298 | 1253 | { |
1299 | - env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8); | |
1300 | - env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7); | |
1254 | + env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8); | |
1255 | + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7); | |
1301 | 1256 | } |
1302 | 1257 | |
1303 | -void do_mtc0_xcontext (void) | |
1258 | +void do_mtc0_xcontext (target_ulong t0) | |
1304 | 1259 | { |
1305 | 1260 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
1306 | - env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); | |
1261 | + env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask); | |
1307 | 1262 | } |
1308 | 1263 | |
1309 | -void do_mtc0_framemask (void) | |
1264 | +void do_mtc0_framemask (target_ulong t0) | |
1310 | 1265 | { |
1311 | - env->CP0_Framemask = T0; /* XXX */ | |
1266 | + env->CP0_Framemask = t0; /* XXX */ | |
1312 | 1267 | } |
1313 | 1268 | |
1314 | -void do_mtc0_debug (void) | |
1269 | +void do_mtc0_debug (target_ulong t0) | |
1315 | 1270 | { |
1316 | - env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); | |
1317 | - if (T0 & (1 << CP0DB_DM)) | |
1271 | + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120); | |
1272 | + if (t0 & (1 << CP0DB_DM)) | |
1318 | 1273 | env->hflags |= MIPS_HFLAG_DM; |
1319 | 1274 | else |
1320 | 1275 | env->hflags &= ~MIPS_HFLAG_DM; |
1321 | 1276 | } |
1322 | 1277 | |
1323 | -void do_mttc0_debug(void) | |
1278 | +void do_mttc0_debug(target_ulong t0) | |
1324 | 1279 | { |
1325 | 1280 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1326 | 1281 | |
1327 | 1282 | /* XXX: Might be wrong, check with EJTAG spec. */ |
1328 | - env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); | |
1283 | + env->CP0_Debug_tcstatus[other_tc] = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); | |
1329 | 1284 | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
1330 | - (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); | |
1285 | + (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); | |
1331 | 1286 | } |
1332 | 1287 | |
1333 | -void do_mtc0_performance0 (void) | |
1288 | +void do_mtc0_performance0 (target_ulong t0) | |
1334 | 1289 | { |
1335 | - env->CP0_Performance0 = T0 & 0x000007ff; | |
1290 | + env->CP0_Performance0 = t0 & 0x000007ff; | |
1336 | 1291 | } |
1337 | 1292 | |
1338 | -void do_mtc0_taglo (void) | |
1293 | +void do_mtc0_taglo (target_ulong t0) | |
1339 | 1294 | { |
1340 | - env->CP0_TagLo = T0 & 0xFFFFFCF6; | |
1295 | + env->CP0_TagLo = t0 & 0xFFFFFCF6; | |
1341 | 1296 | } |
1342 | 1297 | |
1343 | -void do_mtc0_datalo (void) | |
1298 | +void do_mtc0_datalo (target_ulong t0) | |
1344 | 1299 | { |
1345 | - env->CP0_DataLo = T0; /* XXX */ | |
1300 | + env->CP0_DataLo = t0; /* XXX */ | |
1346 | 1301 | } |
1347 | 1302 | |
1348 | -void do_mtc0_taghi (void) | |
1303 | +void do_mtc0_taghi (target_ulong t0) | |
1349 | 1304 | { |
1350 | - env->CP0_TagHi = T0; /* XXX */ | |
1305 | + env->CP0_TagHi = t0; /* XXX */ | |
1351 | 1306 | } |
1352 | 1307 | |
1353 | -void do_mtc0_datahi (void) | |
1308 | +void do_mtc0_datahi (target_ulong t0) | |
1354 | 1309 | { |
1355 | - env->CP0_DataHi = T0; /* XXX */ | |
1310 | + env->CP0_DataHi = t0; /* XXX */ | |
1356 | 1311 | } |
1357 | 1312 | |
1358 | 1313 | void do_mtc0_status_debug(uint32_t old, uint32_t val) |
... | ... | @@ -1376,117 +1331,127 @@ void do_mtc0_status_irqraise_debug(void) |
1376 | 1331 | #endif /* !CONFIG_USER_ONLY */ |
1377 | 1332 | |
1378 | 1333 | /* MIPS MT functions */ |
1379 | -void do_mftgpr(uint32_t sel) | |
1334 | +target_ulong do_mftgpr(target_ulong t0, uint32_t sel) | |
1380 | 1335 | { |
1381 | 1336 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1382 | 1337 | |
1383 | - T0 = env->gpr[other_tc][sel]; | |
1338 | + return env->gpr[other_tc][sel]; | |
1384 | 1339 | } |
1385 | 1340 | |
1386 | -void do_mftlo(uint32_t sel) | |
1341 | +target_ulong do_mftlo(target_ulong t0, uint32_t sel) | |
1387 | 1342 | { |
1388 | 1343 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1389 | 1344 | |
1390 | - T0 = env->LO[other_tc][sel]; | |
1345 | + return env->LO[other_tc][sel]; | |
1391 | 1346 | } |
1392 | 1347 | |
1393 | -void do_mfthi(uint32_t sel) | |
1348 | +target_ulong do_mfthi(target_ulong t0, uint32_t sel) | |
1394 | 1349 | { |
1395 | 1350 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1396 | 1351 | |
1397 | - T0 = env->HI[other_tc][sel]; | |
1352 | + return env->HI[other_tc][sel]; | |
1398 | 1353 | } |
1399 | 1354 | |
1400 | -void do_mftacx(uint32_t sel) | |
1355 | +target_ulong do_mftacx(target_ulong t0, uint32_t sel) | |
1401 | 1356 | { |
1402 | 1357 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1403 | 1358 | |
1404 | - T0 = env->ACX[other_tc][sel]; | |
1359 | + return env->ACX[other_tc][sel]; | |
1405 | 1360 | } |
1406 | 1361 | |
1407 | -void do_mftdsp(void) | |
1362 | +target_ulong do_mftdsp(target_ulong t0) | |
1408 | 1363 | { |
1409 | 1364 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1410 | 1365 | |
1411 | - T0 = env->DSPControl[other_tc]; | |
1366 | + return env->DSPControl[other_tc]; | |
1412 | 1367 | } |
1413 | 1368 | |
1414 | -void do_mttgpr(uint32_t sel) | |
1369 | +void do_mttgpr(target_ulong t0, uint32_t sel) | |
1415 | 1370 | { |
1416 | 1371 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1417 | 1372 | |
1418 | - T0 = env->gpr[other_tc][sel]; | |
1373 | + env->gpr[other_tc][sel] = t0; | |
1419 | 1374 | } |
1420 | 1375 | |
1421 | -void do_mttlo(uint32_t sel) | |
1376 | +void do_mttlo(target_ulong t0, uint32_t sel) | |
1422 | 1377 | { |
1423 | 1378 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1424 | 1379 | |
1425 | - T0 = env->LO[other_tc][sel]; | |
1380 | + env->LO[other_tc][sel] = t0; | |
1426 | 1381 | } |
1427 | 1382 | |
1428 | -void do_mtthi(uint32_t sel) | |
1383 | +void do_mtthi(target_ulong t0, uint32_t sel) | |
1429 | 1384 | { |
1430 | 1385 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1431 | 1386 | |
1432 | - T0 = env->HI[other_tc][sel]; | |
1387 | + env->HI[other_tc][sel] = t0; | |
1433 | 1388 | } |
1434 | 1389 | |
1435 | -void do_mttacx(uint32_t sel) | |
1390 | +void do_mttacx(target_ulong t0, uint32_t sel) | |
1436 | 1391 | { |
1437 | 1392 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1438 | 1393 | |
1439 | - T0 = env->ACX[other_tc][sel]; | |
1394 | + env->ACX[other_tc][sel] = t0; | |
1440 | 1395 | } |
1441 | 1396 | |
1442 | -void do_mttdsp(void) | |
1397 | +void do_mttdsp(target_ulong t0) | |
1443 | 1398 | { |
1444 | 1399 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1445 | 1400 | |
1446 | - T0 = env->DSPControl[other_tc]; | |
1401 | + env->DSPControl[other_tc] = t0; | |
1447 | 1402 | } |
1448 | 1403 | |
1449 | 1404 | /* MIPS MT functions */ |
1450 | -void do_dmt(void) | |
1405 | +target_ulong do_dmt(target_ulong t0) | |
1451 | 1406 | { |
1452 | 1407 | // TODO |
1453 | - T0 = 0; | |
1454 | - // rt = T0 | |
1408 | + t0 = 0; | |
1409 | + // rt = t0 | |
1410 | + | |
1411 | + return t0; | |
1455 | 1412 | } |
1456 | 1413 | |
1457 | -void do_emt(void) | |
1414 | +target_ulong do_emt(target_ulong t0) | |
1458 | 1415 | { |
1459 | 1416 | // TODO |
1460 | - T0 = 0; | |
1461 | - // rt = T0 | |
1417 | + t0 = 0; | |
1418 | + // rt = t0 | |
1419 | + | |
1420 | + return t0; | |
1462 | 1421 | } |
1463 | 1422 | |
1464 | -void do_dvpe(void) | |
1423 | +target_ulong do_dvpe(target_ulong t0) | |
1465 | 1424 | { |
1466 | 1425 | // TODO |
1467 | - T0 = 0; | |
1468 | - // rt = T0 | |
1426 | + t0 = 0; | |
1427 | + // rt = t0 | |
1428 | + | |
1429 | + return t0; | |
1469 | 1430 | } |
1470 | 1431 | |
1471 | -void do_evpe(void) | |
1432 | +target_ulong do_evpe(target_ulong t0) | |
1472 | 1433 | { |
1473 | 1434 | // TODO |
1474 | - T0 = 0; | |
1475 | - // rt = T0 | |
1435 | + t0 = 0; | |
1436 | + // rt = t0 | |
1437 | + | |
1438 | + return t0; | |
1476 | 1439 | } |
1477 | 1440 | |
1478 | -void do_fork(void) | |
1441 | +target_ulong do_fork(target_ulong t0, target_ulong t1) | |
1479 | 1442 | { |
1480 | - // T0 = rt, T1 = rs | |
1481 | - T0 = 0; | |
1443 | + // t0 = rt, t1 = rs | |
1444 | + t0 = 0; | |
1482 | 1445 | // TODO: store to TC register |
1446 | + | |
1447 | + return t0; | |
1483 | 1448 | } |
1484 | 1449 | |
1485 | -void do_yield(void) | |
1450 | +target_ulong do_yield(target_ulong t0) | |
1486 | 1451 | { |
1487 | - if (T0 < 0) { | |
1452 | + if (t0 < 0) { | |
1488 | 1453 | /* No scheduling policy implemented. */ |
1489 | - if (T0 != -2) { | |
1454 | + if (t0 != -2) { | |
1490 | 1455 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
1491 | 1456 | env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) { |
1492 | 1457 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
... | ... | @@ -1494,20 +1459,20 @@ void do_yield(void) |
1494 | 1459 | do_raise_exception(EXCP_THREAD); |
1495 | 1460 | } |
1496 | 1461 | } |
1497 | - } else if (T0 == 0) { | |
1462 | + } else if (t0 == 0) { | |
1498 | 1463 | if (0 /* TODO: TC underflow */) { |
1499 | 1464 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1500 | 1465 | do_raise_exception(EXCP_THREAD); |
1501 | 1466 | } else { |
1502 | 1467 | // TODO: Deallocate TC |
1503 | 1468 | } |
1504 | - } else if (T0 > 0) { | |
1469 | + } else if (t0 > 0) { | |
1505 | 1470 | /* Yield qualifier inputs not implemented. */ |
1506 | 1471 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1507 | 1472 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; |
1508 | 1473 | do_raise_exception(EXCP_THREAD); |
1509 | 1474 | } |
1510 | - T0 = env->CP0_YQMask; | |
1475 | + return env->CP0_YQMask; | |
1511 | 1476 | } |
1512 | 1477 | |
1513 | 1478 | /* CP1 functions */ |
... | ... | @@ -1673,33 +1638,23 @@ void r4k_do_tlbr (void) |
1673 | 1638 | |
1674 | 1639 | #endif /* !CONFIG_USER_ONLY */ |
1675 | 1640 | |
1676 | -void dump_ldst (const unsigned char *func) | |
1677 | -{ | |
1678 | - if (loglevel) | |
1679 | - fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); | |
1680 | -} | |
1681 | - | |
1682 | -void dump_sc (void) | |
1683 | -{ | |
1684 | - if (loglevel) { | |
1685 | - fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, | |
1686 | - T1, T0, env->CP0_LLAddr); | |
1687 | - } | |
1688 | -} | |
1689 | - | |
1690 | 1641 | /* Specials */ |
1691 | -void do_di (void) | |
1642 | +target_ulong do_di (target_ulong t0) | |
1692 | 1643 | { |
1693 | - T0 = env->CP0_Status; | |
1694 | - env->CP0_Status = T0 & ~(1 << CP0St_IE); | |
1644 | + t0 = env->CP0_Status; | |
1645 | + env->CP0_Status = t0 & ~(1 << CP0St_IE); | |
1695 | 1646 | cpu_mips_update_irq(env); |
1647 | + | |
1648 | + return t0; | |
1696 | 1649 | } |
1697 | 1650 | |
1698 | -void do_ei (void) | |
1651 | +target_ulong do_ei (target_ulong t0) | |
1699 | 1652 | { |
1700 | - T0 = env->CP0_Status; | |
1701 | - env->CP0_Status = T0 | (1 << CP0St_IE); | |
1653 | + t0 = env->CP0_Status; | |
1654 | + env->CP0_Status = t0 | (1 << CP0St_IE); | |
1702 | 1655 | cpu_mips_update_irq(env); |
1656 | + | |
1657 | + return t0; | |
1703 | 1658 | } |
1704 | 1659 | |
1705 | 1660 | void debug_pre_eret (void) |
... | ... | @@ -1729,7 +1684,7 @@ void debug_post_eret (void) |
1729 | 1684 | } |
1730 | 1685 | } |
1731 | 1686 | |
1732 | -void do_eret (void) | |
1687 | +void do_eret (target_ulong t0) | |
1733 | 1688 | { |
1734 | 1689 | if (loglevel & CPU_LOG_EXEC) |
1735 | 1690 | debug_pre_eret(); |
... | ... | @@ -1746,7 +1701,7 @@ void do_eret (void) |
1746 | 1701 | env->CP0_LLAddr = 1; |
1747 | 1702 | } |
1748 | 1703 | |
1749 | -void do_deret (void) | |
1704 | +void do_deret (target_ulong t0) | |
1750 | 1705 | { |
1751 | 1706 | if (loglevel & CPU_LOG_EXEC) |
1752 | 1707 | debug_pre_eret(); |
... | ... | @@ -1758,82 +1713,90 @@ void do_deret (void) |
1758 | 1713 | env->CP0_LLAddr = 1; |
1759 | 1714 | } |
1760 | 1715 | |
1761 | -void do_rdhwr_cpunum(void) | |
1716 | +target_ulong do_rdhwr_cpunum(target_ulong t0) | |
1762 | 1717 | { |
1763 | 1718 | if ((env->hflags & MIPS_HFLAG_CP0) || |
1764 | 1719 | (env->CP0_HWREna & (1 << 0))) |
1765 | - T0 = env->CP0_EBase & 0x3ff; | |
1720 | + t0 = env->CP0_EBase & 0x3ff; | |
1766 | 1721 | else |
1767 | 1722 | do_raise_exception(EXCP_RI); |
1723 | + | |
1724 | + return t0; | |
1768 | 1725 | } |
1769 | 1726 | |
1770 | -void do_rdhwr_synci_step(void) | |
1727 | +target_ulong do_rdhwr_synci_step(target_ulong t0) | |
1771 | 1728 | { |
1772 | 1729 | if ((env->hflags & MIPS_HFLAG_CP0) || |
1773 | 1730 | (env->CP0_HWREna & (1 << 1))) |
1774 | - T0 = env->SYNCI_Step; | |
1731 | + t0 = env->SYNCI_Step; | |
1775 | 1732 | else |
1776 | 1733 | do_raise_exception(EXCP_RI); |
1734 | + | |
1735 | + return t0; | |
1777 | 1736 | } |
1778 | 1737 | |
1779 | -void do_rdhwr_cc(void) | |
1738 | +target_ulong do_rdhwr_cc(target_ulong t0) | |
1780 | 1739 | { |
1781 | 1740 | if ((env->hflags & MIPS_HFLAG_CP0) || |
1782 | 1741 | (env->CP0_HWREna & (1 << 2))) |
1783 | - T0 = env->CP0_Count; | |
1742 | + t0 = env->CP0_Count; | |
1784 | 1743 | else |
1785 | 1744 | do_raise_exception(EXCP_RI); |
1745 | + | |
1746 | + return t0; | |
1786 | 1747 | } |
1787 | 1748 | |
1788 | -void do_rdhwr_ccres(void) | |
1749 | +target_ulong do_rdhwr_ccres(target_ulong t0) | |
1789 | 1750 | { |
1790 | 1751 | if ((env->hflags & MIPS_HFLAG_CP0) || |
1791 | 1752 | (env->CP0_HWREna & (1 << 3))) |
1792 | - T0 = env->CCRes; | |
1753 | + t0 = env->CCRes; | |
1793 | 1754 | else |
1794 | 1755 | do_raise_exception(EXCP_RI); |
1756 | + | |
1757 | + return t0; | |
1795 | 1758 | } |
1796 | 1759 | |
1797 | 1760 | /* Bitfield operations. */ |
1798 | -void do_ext(uint32_t pos, uint32_t size) | |
1761 | +target_ulong do_ext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size) | |
1799 | 1762 | { |
1800 | - T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0)); | |
1763 | + return (int32_t)((t1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0)); | |
1801 | 1764 | } |
1802 | 1765 | |
1803 | -void do_ins(uint32_t pos, uint32_t size) | |
1766 | +target_ulong do_ins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size) | |
1804 | 1767 | { |
1805 | 1768 | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
1806 | 1769 | |
1807 | - T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask)); | |
1770 | + return (int32_t)((t0 & ~mask) | ((t1 << pos) & mask)); | |
1808 | 1771 | } |
1809 | 1772 | |
1810 | -void do_wsbh(void) | |
1773 | +target_ulong do_wsbh(target_ulong t0, target_ulong t1) | |
1811 | 1774 | { |
1812 | - T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF)); | |
1775 | + return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF)); | |
1813 | 1776 | } |
1814 | 1777 | |
1815 | 1778 | #if defined(TARGET_MIPS64) |
1816 | -void do_dext(uint32_t pos, uint32_t size) | |
1779 | +target_ulong do_dext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size) | |
1817 | 1780 | { |
1818 | - T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL); | |
1781 | + return (t1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL); | |
1819 | 1782 | } |
1820 | 1783 | |
1821 | -void do_dins(uint32_t pos, uint32_t size) | |
1784 | +target_ulong do_dins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size) | |
1822 | 1785 | { |
1823 | 1786 | target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos; |
1824 | 1787 | |
1825 | - T0 = (T0 & ~mask) | ((T1 << pos) & mask); | |
1788 | + return (t0 & ~mask) | ((t1 << pos) & mask); | |
1826 | 1789 | } |
1827 | 1790 | |
1828 | -void do_dsbh(void) | |
1791 | +target_ulong do_dsbh(target_ulong t0, target_ulong t1) | |
1829 | 1792 | { |
1830 | - T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); | |
1793 | + return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL); | |
1831 | 1794 | } |
1832 | 1795 | |
1833 | -void do_dshd(void) | |
1796 | +target_ulong do_dshd(target_ulong t0, target_ulong t1) | |
1834 | 1797 | { |
1835 | - T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); | |
1836 | - T0 = (T1 << 32) | (T1 >> 32); | |
1798 | + t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL); | |
1799 | + return (t1 << 32) | (t1 >> 32); | |
1837 | 1800 | } |
1838 | 1801 | #endif |
1839 | 1802 | |
... | ... | @@ -1955,51 +1918,53 @@ unsigned int ieee_rm[] = { |
1955 | 1918 | #define RESTORE_ROUNDING_MODE \ |
1956 | 1919 | set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status) |
1957 | 1920 | |
1958 | -void do_cfc1 (uint32_t reg) | |
1921 | +target_ulong do_cfc1 (target_ulong t0, uint32_t reg) | |
1959 | 1922 | { |
1960 | 1923 | switch (reg) { |
1961 | 1924 | case 0: |
1962 | - T0 = (int32_t)env->fpu->fcr0; | |
1925 | + t0 = (int32_t)env->fpu->fcr0; | |
1963 | 1926 | break; |
1964 | 1927 | case 25: |
1965 | - T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); | |
1928 | + t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); | |
1966 | 1929 | break; |
1967 | 1930 | case 26: |
1968 | - T0 = env->fpu->fcr31 & 0x0003f07c; | |
1931 | + t0 = env->fpu->fcr31 & 0x0003f07c; | |
1969 | 1932 | break; |
1970 | 1933 | case 28: |
1971 | - T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); | |
1934 | + t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); | |
1972 | 1935 | break; |
1973 | 1936 | default: |
1974 | - T0 = (int32_t)env->fpu->fcr31; | |
1937 | + t0 = (int32_t)env->fpu->fcr31; | |
1975 | 1938 | break; |
1976 | 1939 | } |
1940 | + | |
1941 | + return t0; | |
1977 | 1942 | } |
1978 | 1943 | |
1979 | -void do_ctc1 (uint32_t reg) | |
1944 | +void do_ctc1 (target_ulong t0, uint32_t reg) | |
1980 | 1945 | { |
1981 | 1946 | switch(reg) { |
1982 | 1947 | case 25: |
1983 | - if (T0 & 0xffffff00) | |
1948 | + if (t0 & 0xffffff00) | |
1984 | 1949 | return; |
1985 | - env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | | |
1986 | - ((T0 & 0x1) << 23); | |
1950 | + env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) | | |
1951 | + ((t0 & 0x1) << 23); | |
1987 | 1952 | break; |
1988 | 1953 | case 26: |
1989 | - if (T0 & 0x007c0000) | |
1954 | + if (t0 & 0x007c0000) | |
1990 | 1955 | return; |
1991 | - env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); | |
1956 | + env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c); | |
1992 | 1957 | break; |
1993 | 1958 | case 28: |
1994 | - if (T0 & 0x007c0000) | |
1959 | + if (t0 & 0x007c0000) | |
1995 | 1960 | return; |
1996 | - env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | | |
1997 | - ((T0 & 0x4) << 22); | |
1961 | + env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) | | |
1962 | + ((t0 & 0x4) << 22); | |
1998 | 1963 | break; |
1999 | 1964 | case 31: |
2000 | - if (T0 & 0x007c0000) | |
1965 | + if (t0 & 0x007c0000) | |
2001 | 1966 | return; |
2002 | - env->fpu->fcr31 = T0; | |
1967 | + env->fpu->fcr31 = t0; | |
2003 | 1968 | break; |
2004 | 1969 | default: |
2005 | 1970 | return; | ... | ... |
target-mips/translate.c
... | ... | @@ -428,22 +428,74 @@ static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[2]; |
428 | 428 | /* FPU TNs, global for now. */ |
429 | 429 | static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3]; |
430 | 430 | |
431 | -static inline void tcg_gen_helper_0_1i(void *func, TCGv arg) | |
431 | +static inline void tcg_gen_helper_0_i(void *func, TCGv arg) | |
432 | 432 | { |
433 | - TCGv t = tcg_const_i32(arg); | |
433 | + TCGv tmp = tcg_const_i32(arg); | |
434 | 434 | |
435 | - tcg_gen_helper_0_1(func, t); | |
436 | - tcg_temp_free(t); | |
435 | + tcg_gen_helper_0_1(func, tmp); | |
436 | + tcg_temp_free(tmp); | |
437 | 437 | } |
438 | 438 | |
439 | -static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2) | |
439 | +static inline void tcg_gen_helper_0_ii(void *func, TCGv arg1, TCGv arg2) | |
440 | 440 | { |
441 | - TCGv t1 = tcg_const_i32(arg1); | |
442 | - TCGv t2 = tcg_const_i32(arg2); | |
441 | + TCGv tmp1 = tcg_const_i32(arg1); | |
442 | + TCGv tmp2 = tcg_const_i32(arg2); | |
443 | 443 | |
444 | - tcg_gen_helper_0_2(func, t1, t2); | |
445 | - tcg_temp_free(t1); | |
446 | - tcg_temp_free(t2); | |
444 | + tcg_gen_helper_0_2(func, tmp1, tmp2); | |
445 | + tcg_temp_free(tmp1); | |
446 | + tcg_temp_free(tmp2); | |
447 | +} | |
448 | + | |
449 | +static inline void tcg_gen_helper_0_1i(void *func, TCGv arg1, TCGv arg2) | |
450 | +{ | |
451 | + TCGv tmp = tcg_const_i32(arg2); | |
452 | + | |
453 | + tcg_gen_helper_0_2(func, arg1, tmp); | |
454 | + tcg_temp_free(tmp); | |
455 | +} | |
456 | + | |
457 | +static inline void tcg_gen_helper_0_2i(void *func, TCGv arg1, TCGv arg2, TCGv arg3) | |
458 | +{ | |
459 | + TCGv tmp = tcg_const_i32(arg3); | |
460 | + | |
461 | + tcg_gen_helper_0_3(func, arg1, arg2, tmp); | |
462 | + tcg_temp_free(tmp); | |
463 | +} | |
464 | + | |
465 | +static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4) | |
466 | +{ | |
467 | + TCGv tmp1 = tcg_const_i32(arg3); | |
468 | + TCGv tmp2 = tcg_const_i32(arg3); | |
469 | + | |
470 | + tcg_gen_helper_0_4(func, arg1, arg2, tmp1, tmp2); | |
471 | + tcg_temp_free(tmp1); | |
472 | + tcg_temp_free(tmp2); | |
473 | +} | |
474 | + | |
475 | +static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, TCGv arg2) | |
476 | +{ | |
477 | + TCGv tmp = tcg_const_i32(arg2); | |
478 | + | |
479 | + tcg_gen_helper_1_2(func, ret, arg1, tmp); | |
480 | + tcg_temp_free(tmp); | |
481 | +} | |
482 | + | |
483 | +static inline void tcg_gen_helper_1_2i(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3) | |
484 | +{ | |
485 | + TCGv tmp = tcg_const_i32(arg3); | |
486 | + | |
487 | + tcg_gen_helper_1_3(func, ret, arg1, arg2, tmp); | |
488 | + tcg_temp_free(tmp); | |
489 | +} | |
490 | + | |
491 | +static inline void tcg_gen_helper_1_2ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4) | |
492 | +{ | |
493 | + TCGv tmp1 = tcg_const_i32(arg3); | |
494 | + TCGv tmp2 = tcg_const_i32(arg3); | |
495 | + | |
496 | + tcg_gen_helper_1_4(func, ret, arg1, arg2, tmp1, tmp2); | |
497 | + tcg_temp_free(tmp1); | |
498 | + tcg_temp_free(tmp2); | |
447 | 499 | } |
448 | 500 | |
449 | 501 | typedef struct DisasContext { |
... | ... | @@ -540,37 +592,44 @@ static inline void gen_store_HI (TCGv t, int reg) |
540 | 592 | } |
541 | 593 | |
542 | 594 | /* Moves to/from shadow registers. */ |
543 | -static inline void gen_load_srsgpr (TCGv t, int reg) | |
595 | +static inline void gen_load_srsgpr (int from, int to) | |
544 | 596 | { |
545 | - if (reg == 0) | |
546 | - tcg_gen_movi_tl(t, 0); | |
597 | + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); | |
598 | + | |
599 | + if (from == 0) | |
600 | + tcg_gen_movi_tl(r_tmp1, 0); | |
547 | 601 | else { |
548 | - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); | |
602 | + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); | |
549 | 603 | |
550 | - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl)); | |
551 | - tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS); | |
552 | - tcg_gen_andi_i32(r_tmp, r_tmp, 0xf); | |
553 | - tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32); | |
554 | - tcg_gen_add_i32(r_tmp, cpu_env, r_tmp); | |
604 | + tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); | |
605 | + tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS); | |
606 | + tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf); | |
607 | + tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32); | |
608 | + tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2); | |
555 | 609 | |
556 | - tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg); | |
557 | - tcg_temp_free(r_tmp); | |
610 | + tcg_gen_ld_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * from); | |
611 | + tcg_temp_free(r_tmp2); | |
558 | 612 | } |
613 | + gen_store_gpr(r_tmp1, to); | |
614 | + tcg_temp_free(r_tmp1); | |
559 | 615 | } |
560 | 616 | |
561 | -static inline void gen_store_srsgpr (TCGv t, int reg) | |
617 | +static inline void gen_store_srsgpr (int from, int to) | |
562 | 618 | { |
563 | - if (reg != 0) { | |
564 | - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); | |
565 | - | |
566 | - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl)); | |
567 | - tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS); | |
568 | - tcg_gen_andi_i32(r_tmp, r_tmp, 0xf); | |
569 | - tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32); | |
570 | - tcg_gen_add_i32(r_tmp, cpu_env, r_tmp); | |
571 | - | |
572 | - tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg); | |
573 | - tcg_temp_free(r_tmp); | |
619 | + if (to != 0) { | |
620 | + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); | |
621 | + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); | |
622 | + | |
623 | + gen_load_gpr(r_tmp1, from); | |
624 | + tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); | |
625 | + tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS); | |
626 | + tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf); | |
627 | + tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32); | |
628 | + tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2); | |
629 | + | |
630 | + tcg_gen_st_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * to); | |
631 | + tcg_temp_free(r_tmp1); | |
632 | + tcg_temp_free(r_tmp2); | |
574 | 633 | } |
575 | 634 | } |
576 | 635 | |
... | ... | @@ -666,7 +725,7 @@ static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = { \ |
666 | 725 | }; \ |
667 | 726 | static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ |
668 | 727 | { \ |
669 | - tcg_gen_helper_0_1i(fcmp ## type ## _ ## fmt ## _table[n], cc); \ | |
728 | + tcg_gen_helper_0_i(fcmp ## type ## _ ## fmt ## _table[n], cc); \ | |
670 | 729 | } |
671 | 730 | |
672 | 731 | FOP_CONDS(, d) |
... | ... | @@ -679,16 +738,16 @@ FOP_CONDS(abs, ps) |
679 | 738 | |
680 | 739 | /* Tests */ |
681 | 740 | #define OP_COND(name, cond) \ |
682 | -void glue(gen_op_, name) (void) \ | |
741 | +void glue(gen_op_, name) (TCGv t0, TCGv t1) \ | |
683 | 742 | { \ |
684 | 743 | int l1 = gen_new_label(); \ |
685 | 744 | int l2 = gen_new_label(); \ |
686 | 745 | \ |
687 | - tcg_gen_brcond_tl(cond, cpu_T[0], cpu_T[1], l1); \ | |
688 | - tcg_gen_movi_tl(cpu_T[0], 0); \ | |
746 | + tcg_gen_brcond_tl(cond, t0, t1, l1); \ | |
747 | + tcg_gen_movi_tl(t0, 0); \ | |
689 | 748 | tcg_gen_br(l2); \ |
690 | 749 | gen_set_label(l1); \ |
691 | - tcg_gen_movi_tl(cpu_T[0], 1); \ | |
750 | + tcg_gen_movi_tl(t0, 1); \ | |
692 | 751 | gen_set_label(l2); \ |
693 | 752 | } |
694 | 753 | OP_COND(eq, TCG_COND_EQ); |
... | ... | @@ -700,16 +759,16 @@ OP_COND(ltu, TCG_COND_LTU); |
700 | 759 | #undef OP_COND |
701 | 760 | |
702 | 761 | #define OP_CONDI(name, cond) \ |
703 | -void glue(gen_op_, name) (target_ulong val) \ | |
762 | +void glue(gen_op_, name) (TCGv t, target_ulong val) \ | |
704 | 763 | { \ |
705 | 764 | int l1 = gen_new_label(); \ |
706 | 765 | int l2 = gen_new_label(); \ |
707 | 766 | \ |
708 | - tcg_gen_brcondi_tl(cond, cpu_T[0], val, l1); \ | |
709 | - tcg_gen_movi_tl(cpu_T[0], 0); \ | |
767 | + tcg_gen_brcondi_tl(cond, t, val, l1); \ | |
768 | + tcg_gen_movi_tl(t, 0); \ | |
710 | 769 | tcg_gen_br(l2); \ |
711 | 770 | gen_set_label(l1); \ |
712 | - tcg_gen_movi_tl(cpu_T[0], 1); \ | |
771 | + tcg_gen_movi_tl(t, 1); \ | |
713 | 772 | gen_set_label(l2); \ |
714 | 773 | } |
715 | 774 | OP_CONDI(lti, TCG_COND_LT); |
... | ... | @@ -717,16 +776,16 @@ OP_CONDI(ltiu, TCG_COND_LTU); |
717 | 776 | #undef OP_CONDI |
718 | 777 | |
719 | 778 | #define OP_CONDZ(name, cond) \ |
720 | -void glue(gen_op_, name) (void) \ | |
779 | +void glue(gen_op_, name) (TCGv t) \ | |
721 | 780 | { \ |
722 | 781 | int l1 = gen_new_label(); \ |
723 | 782 | int l2 = gen_new_label(); \ |
724 | 783 | \ |
725 | - tcg_gen_brcondi_tl(cond, cpu_T[0], 0, l1); \ | |
726 | - tcg_gen_movi_tl(cpu_T[0], 0); \ | |
784 | + tcg_gen_brcondi_tl(cond, t, 0, l1); \ | |
785 | + tcg_gen_movi_tl(t, 0); \ | |
727 | 786 | tcg_gen_br(l2); \ |
728 | 787 | gen_set_label(l1); \ |
729 | - tcg_gen_movi_tl(cpu_T[0], 1); \ | |
788 | + tcg_gen_movi_tl(t, 1); \ | |
730 | 789 | gen_set_label(l2); \ |
731 | 790 | } |
732 | 791 | OP_CONDZ(gez, TCG_COND_GE); |
... | ... | @@ -840,7 +899,7 @@ static always_inline void |
840 | 899 | generate_exception_err (DisasContext *ctx, int excp, int err) |
841 | 900 | { |
842 | 901 | save_cpu_state(ctx, 1); |
843 | - tcg_gen_helper_0_2ii(do_raise_exception_err, excp, err); | |
902 | + tcg_gen_helper_0_ii(do_raise_exception_err, excp, err); | |
844 | 903 | tcg_gen_helper_0_0(do_interrupt_restart); |
845 | 904 | tcg_gen_exit_tb(0); |
846 | 905 | } |
... | ... | @@ -849,15 +908,15 @@ static always_inline void |
849 | 908 | generate_exception (DisasContext *ctx, int excp) |
850 | 909 | { |
851 | 910 | save_cpu_state(ctx, 1); |
852 | - tcg_gen_helper_0_1i(do_raise_exception, excp); | |
911 | + tcg_gen_helper_0_i(do_raise_exception, excp); | |
853 | 912 | tcg_gen_helper_0_0(do_interrupt_restart); |
854 | 913 | tcg_gen_exit_tb(0); |
855 | 914 | } |
856 | 915 | |
857 | 916 | /* Addresses computation */ |
858 | -static inline void gen_op_addr_add (void) | |
917 | +static inline void gen_op_addr_add (TCGv t0, TCGv t1) | |
859 | 918 | { |
860 | - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
919 | + tcg_gen_add_tl(t0, t0, t1); | |
861 | 920 | |
862 | 921 | #if defined(TARGET_MIPS64) |
863 | 922 | /* For compatibility with 32-bit code, data reference in user mode |
... | ... | @@ -874,7 +933,7 @@ static inline void gen_op_addr_add (void) |
874 | 933 | tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX)); |
875 | 934 | tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1); |
876 | 935 | tcg_temp_free(r_tmp); |
877 | - tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]); | |
936 | + tcg_gen_ext32s_i64(t0, t0); | |
878 | 937 | gen_set_label(l1); |
879 | 938 | } |
880 | 939 | #endif |
... | ... | @@ -946,9 +1005,9 @@ static always_inline void check_mips_64(DisasContext *ctx) |
946 | 1005 | |
947 | 1006 | /* load/store instructions. */ |
948 | 1007 | #define OP_LD(insn,fname) \ |
949 | -void inline op_ldst_##insn(DisasContext *ctx) \ | |
1008 | +void inline op_ldst_##insn(TCGv t0, DisasContext *ctx) \ | |
950 | 1009 | { \ |
951 | - tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \ | |
1010 | + tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \ | |
952 | 1011 | } |
953 | 1012 | OP_LD(lb,ld8s); |
954 | 1013 | OP_LD(lbu,ld8u); |
... | ... | @@ -962,9 +1021,9 @@ OP_LD(ld,ld64); |
962 | 1021 | #undef OP_LD |
963 | 1022 | |
964 | 1023 | #define OP_ST(insn,fname) \ |
965 | -void inline op_ldst_##insn(DisasContext *ctx) \ | |
1024 | +void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \ | |
966 | 1025 | { \ |
967 | - tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \ | |
1026 | + tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \ | |
968 | 1027 | } |
969 | 1028 | OP_ST(sb,st8); |
970 | 1029 | OP_ST(sh,st16); |
... | ... | @@ -975,11 +1034,11 @@ OP_ST(sd,st64); |
975 | 1034 | #undef OP_ST |
976 | 1035 | |
977 | 1036 | #define OP_LD_ATOMIC(insn,fname) \ |
978 | -void inline op_ldst_##insn(DisasContext *ctx) \ | |
1037 | +void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \ | |
979 | 1038 | { \ |
980 | - tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); \ | |
981 | - tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \ | |
982 | - tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUState, CP0_LLAddr)); \ | |
1039 | + tcg_gen_mov_tl(t1, t0); \ | |
1040 | + tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \ | |
1041 | + tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ | |
983 | 1042 | } |
984 | 1043 | OP_LD_ATOMIC(ll,ld32s); |
985 | 1044 | #if defined(TARGET_MIPS64) |
... | ... | @@ -988,26 +1047,26 @@ OP_LD_ATOMIC(lld,ld64); |
988 | 1047 | #undef OP_LD_ATOMIC |
989 | 1048 | |
990 | 1049 | #define OP_ST_ATOMIC(insn,fname,almask) \ |
991 | -void inline op_ldst_##insn(DisasContext *ctx) \ | |
1050 | +void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \ | |
992 | 1051 | { \ |
993 | 1052 | TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \ |
994 | 1053 | int l1 = gen_new_label(); \ |
995 | 1054 | int l2 = gen_new_label(); \ |
996 | 1055 | int l3 = gen_new_label(); \ |
997 | 1056 | \ |
998 | - tcg_gen_andi_tl(r_tmp, cpu_T[0], almask); \ | |
1057 | + tcg_gen_andi_tl(r_tmp, t0, almask); \ | |
999 | 1058 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \ |
1000 | - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ | |
1059 | + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ | |
1001 | 1060 | generate_exception(ctx, EXCP_AdES); \ |
1002 | 1061 | gen_set_label(l1); \ |
1003 | 1062 | tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ |
1004 | - tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \ | |
1063 | + tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \ | |
1005 | 1064 | tcg_temp_free(r_tmp); \ |
1006 | - tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \ | |
1007 | - tcg_gen_movi_tl(cpu_T[0], 1); \ | |
1065 | + tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \ | |
1066 | + tcg_gen_movi_tl(t0, 1); \ | |
1008 | 1067 | tcg_gen_br(l3); \ |
1009 | 1068 | gen_set_label(l2); \ |
1010 | - tcg_gen_movi_tl(cpu_T[0], 0); \ | |
1069 | + tcg_gen_movi_tl(t0, 0); \ | |
1011 | 1070 | gen_set_label(l3); \ |
1012 | 1071 | } |
1013 | 1072 | OP_ST_ATOMIC(sc,st32,0x3); |
... | ... | @@ -1029,141 +1088,141 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, |
1029 | 1088 | } else { |
1030 | 1089 | gen_load_gpr(cpu_T[0], base); |
1031 | 1090 | tcg_gen_movi_tl(cpu_T[1], offset); |
1032 | - gen_op_addr_add(); | |
1091 | + gen_op_addr_add(cpu_T[0], cpu_T[1]); | |
1033 | 1092 | } |
1034 | 1093 | /* Don't do NOP if destination is zero: we must perform the actual |
1035 | 1094 | memory access. */ |
1036 | 1095 | switch (opc) { |
1037 | 1096 | #if defined(TARGET_MIPS64) |
1038 | 1097 | case OPC_LWU: |
1039 | - op_ldst_lwu(ctx); | |
1098 | + op_ldst_lwu(cpu_T[0], ctx); | |
1040 | 1099 | gen_store_gpr(cpu_T[0], rt); |
1041 | 1100 | opn = "lwu"; |
1042 | 1101 | break; |
1043 | 1102 | case OPC_LD: |
1044 | - op_ldst_ld(ctx); | |
1103 | + op_ldst_ld(cpu_T[0], ctx); | |
1045 | 1104 | gen_store_gpr(cpu_T[0], rt); |
1046 | 1105 | opn = "ld"; |
1047 | 1106 | break; |
1048 | 1107 | case OPC_LLD: |
1049 | - op_ldst_lld(ctx); | |
1108 | + op_ldst_lld(cpu_T[0], cpu_T[1], ctx); | |
1050 | 1109 | gen_store_gpr(cpu_T[0], rt); |
1051 | 1110 | opn = "lld"; |
1052 | 1111 | break; |
1053 | 1112 | case OPC_SD: |
1054 | 1113 | gen_load_gpr(cpu_T[1], rt); |
1055 | - op_ldst_sd(ctx); | |
1114 | + op_ldst_sd(cpu_T[0], cpu_T[1], ctx); | |
1056 | 1115 | opn = "sd"; |
1057 | 1116 | break; |
1058 | 1117 | case OPC_SCD: |
1059 | 1118 | save_cpu_state(ctx, 1); |
1060 | 1119 | gen_load_gpr(cpu_T[1], rt); |
1061 | - op_ldst_scd(ctx); | |
1120 | + op_ldst_scd(cpu_T[0], cpu_T[1], ctx); | |
1062 | 1121 | gen_store_gpr(cpu_T[0], rt); |
1063 | 1122 | opn = "scd"; |
1064 | 1123 | break; |
1065 | 1124 | case OPC_LDL: |
1066 | 1125 | save_cpu_state(ctx, 1); |
1067 | 1126 | gen_load_gpr(cpu_T[1], rt); |
1068 | - tcg_gen_helper_0_1i(do_ldl, ctx->mem_idx); | |
1127 | + tcg_gen_helper_1_2i(do_ldl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1069 | 1128 | gen_store_gpr(cpu_T[1], rt); |
1070 | 1129 | opn = "ldl"; |
1071 | 1130 | break; |
1072 | 1131 | case OPC_SDL: |
1073 | 1132 | save_cpu_state(ctx, 1); |
1074 | 1133 | gen_load_gpr(cpu_T[1], rt); |
1075 | - tcg_gen_helper_0_1i(do_sdl, ctx->mem_idx); | |
1134 | + tcg_gen_helper_0_2i(do_sdl, cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1076 | 1135 | opn = "sdl"; |
1077 | 1136 | break; |
1078 | 1137 | case OPC_LDR: |
1079 | 1138 | save_cpu_state(ctx, 1); |
1080 | 1139 | gen_load_gpr(cpu_T[1], rt); |
1081 | - tcg_gen_helper_0_1i(do_ldr, ctx->mem_idx); | |
1140 | + tcg_gen_helper_1_2i(do_ldr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1082 | 1141 | gen_store_gpr(cpu_T[1], rt); |
1083 | 1142 | opn = "ldr"; |
1084 | 1143 | break; |
1085 | 1144 | case OPC_SDR: |
1086 | 1145 | save_cpu_state(ctx, 1); |
1087 | 1146 | gen_load_gpr(cpu_T[1], rt); |
1088 | - tcg_gen_helper_0_1i(do_sdr, ctx->mem_idx); | |
1147 | + tcg_gen_helper_0_2i(do_sdr, cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1089 | 1148 | opn = "sdr"; |
1090 | 1149 | break; |
1091 | 1150 | #endif |
1092 | 1151 | case OPC_LW: |
1093 | - op_ldst_lw(ctx); | |
1152 | + op_ldst_lw(cpu_T[0], ctx); | |
1094 | 1153 | gen_store_gpr(cpu_T[0], rt); |
1095 | 1154 | opn = "lw"; |
1096 | 1155 | break; |
1097 | 1156 | case OPC_SW: |
1098 | 1157 | gen_load_gpr(cpu_T[1], rt); |
1099 | - op_ldst_sw(ctx); | |
1158 | + op_ldst_sw(cpu_T[0], cpu_T[1], ctx); | |
1100 | 1159 | opn = "sw"; |
1101 | 1160 | break; |
1102 | 1161 | case OPC_LH: |
1103 | - op_ldst_lh(ctx); | |
1162 | + op_ldst_lh(cpu_T[0], ctx); | |
1104 | 1163 | gen_store_gpr(cpu_T[0], rt); |
1105 | 1164 | opn = "lh"; |
1106 | 1165 | break; |
1107 | 1166 | case OPC_SH: |
1108 | 1167 | gen_load_gpr(cpu_T[1], rt); |
1109 | - op_ldst_sh(ctx); | |
1168 | + op_ldst_sh(cpu_T[0], cpu_T[1], ctx); | |
1110 | 1169 | opn = "sh"; |
1111 | 1170 | break; |
1112 | 1171 | case OPC_LHU: |
1113 | - op_ldst_lhu(ctx); | |
1172 | + op_ldst_lhu(cpu_T[0], ctx); | |
1114 | 1173 | gen_store_gpr(cpu_T[0], rt); |
1115 | 1174 | opn = "lhu"; |
1116 | 1175 | break; |
1117 | 1176 | case OPC_LB: |
1118 | - op_ldst_lb(ctx); | |
1177 | + op_ldst_lb(cpu_T[0], ctx); | |
1119 | 1178 | gen_store_gpr(cpu_T[0], rt); |
1120 | 1179 | opn = "lb"; |
1121 | 1180 | break; |
1122 | 1181 | case OPC_SB: |
1123 | 1182 | gen_load_gpr(cpu_T[1], rt); |
1124 | - op_ldst_sb(ctx); | |
1183 | + op_ldst_sb(cpu_T[0], cpu_T[1], ctx); | |
1125 | 1184 | opn = "sb"; |
1126 | 1185 | break; |
1127 | 1186 | case OPC_LBU: |
1128 | - op_ldst_lbu(ctx); | |
1187 | + op_ldst_lbu(cpu_T[0], ctx); | |
1129 | 1188 | gen_store_gpr(cpu_T[0], rt); |
1130 | 1189 | opn = "lbu"; |
1131 | 1190 | break; |
1132 | 1191 | case OPC_LWL: |
1133 | 1192 | save_cpu_state(ctx, 1); |
1134 | 1193 | gen_load_gpr(cpu_T[1], rt); |
1135 | - tcg_gen_helper_0_1i(do_lwl, ctx->mem_idx); | |
1194 | + tcg_gen_helper_1_2i(do_lwl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1136 | 1195 | gen_store_gpr(cpu_T[1], rt); |
1137 | 1196 | opn = "lwl"; |
1138 | 1197 | break; |
1139 | 1198 | case OPC_SWL: |
1140 | 1199 | save_cpu_state(ctx, 1); |
1141 | 1200 | gen_load_gpr(cpu_T[1], rt); |
1142 | - tcg_gen_helper_0_1i(do_swl, ctx->mem_idx); | |
1201 | + tcg_gen_helper_0_2i(do_swl, cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1143 | 1202 | opn = "swr"; |
1144 | 1203 | break; |
1145 | 1204 | case OPC_LWR: |
1146 | 1205 | save_cpu_state(ctx, 1); |
1147 | 1206 | gen_load_gpr(cpu_T[1], rt); |
1148 | - tcg_gen_helper_0_1i(do_lwr, ctx->mem_idx); | |
1207 | + tcg_gen_helper_1_2i(do_lwr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1149 | 1208 | gen_store_gpr(cpu_T[1], rt); |
1150 | 1209 | opn = "lwr"; |
1151 | 1210 | break; |
1152 | 1211 | case OPC_SWR: |
1153 | 1212 | save_cpu_state(ctx, 1); |
1154 | 1213 | gen_load_gpr(cpu_T[1], rt); |
1155 | - tcg_gen_helper_0_1i(do_swr, ctx->mem_idx); | |
1214 | + tcg_gen_helper_0_2i(do_swr, cpu_T[0], cpu_T[1], ctx->mem_idx); | |
1156 | 1215 | opn = "swr"; |
1157 | 1216 | break; |
1158 | 1217 | case OPC_LL: |
1159 | - op_ldst_ll(ctx); | |
1218 | + op_ldst_ll(cpu_T[0], cpu_T[1], ctx); | |
1160 | 1219 | gen_store_gpr(cpu_T[0], rt); |
1161 | 1220 | opn = "ll"; |
1162 | 1221 | break; |
1163 | 1222 | case OPC_SC: |
1164 | 1223 | save_cpu_state(ctx, 1); |
1165 | 1224 | gen_load_gpr(cpu_T[1], rt); |
1166 | - op_ldst_sc(ctx); | |
1225 | + op_ldst_sc(cpu_T[0], cpu_T[1], ctx); | |
1167 | 1226 | gen_store_gpr(cpu_T[0], rt); |
1168 | 1227 | opn = "sc"; |
1169 | 1228 | break; |
... | ... | @@ -1188,7 +1247,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, |
1188 | 1247 | } else { |
1189 | 1248 | gen_load_gpr(cpu_T[0], base); |
1190 | 1249 | tcg_gen_movi_tl(cpu_T[1], offset); |
1191 | - gen_op_addr_add(); | |
1250 | + gen_op_addr_add(cpu_T[0], cpu_T[1]); | |
1192 | 1251 | } |
1193 | 1252 | /* Don't do NOP if destination is zero: we must perform the actual |
1194 | 1253 | memory access. */ |
... | ... | @@ -1245,7 +1304,6 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, |
1245 | 1304 | case OPC_SLTI: |
1246 | 1305 | case OPC_SLTIU: |
1247 | 1306 | uimm = (target_long)imm; /* Sign extend to 32/64 bits */ |
1248 | - tcg_gen_movi_tl(cpu_T[1], uimm); | |
1249 | 1307 | /* Fall through. */ |
1250 | 1308 | case OPC_ANDI: |
1251 | 1309 | case OPC_ORI: |
... | ... | @@ -1334,11 +1392,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, |
1334 | 1392 | break; |
1335 | 1393 | #endif |
1336 | 1394 | case OPC_SLTI: |
1337 | - gen_op_lti(uimm); | |
1395 | + gen_op_lti(cpu_T[0], uimm); | |
1338 | 1396 | opn = "slti"; |
1339 | 1397 | break; |
1340 | 1398 | case OPC_SLTIU: |
1341 | - gen_op_ltiu(uimm); | |
1399 | + gen_op_ltiu(cpu_T[0], uimm); | |
1342 | 1400 | opn = "sltiu"; |
1343 | 1401 | break; |
1344 | 1402 | case OPC_ANDI: |
... | ... | @@ -1645,11 +1703,11 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, |
1645 | 1703 | break; |
1646 | 1704 | #endif |
1647 | 1705 | case OPC_SLT: |
1648 | - gen_op_lt(); | |
1706 | + gen_op_lt(cpu_T[0], cpu_T[1]); | |
1649 | 1707 | opn = "slt"; |
1650 | 1708 | break; |
1651 | 1709 | case OPC_SLTU: |
1652 | - gen_op_ltu(); | |
1710 | + gen_op_ltu(cpu_T[0], cpu_T[1]); | |
1653 | 1711 | opn = "sltu"; |
1654 | 1712 | break; |
1655 | 1713 | case OPC_AND: |
... | ... | @@ -2031,11 +2089,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, |
2031 | 2089 | opn = "ddivu"; |
2032 | 2090 | break; |
2033 | 2091 | case OPC_DMULT: |
2034 | - tcg_gen_helper_0_0(do_dmult); | |
2092 | + tcg_gen_helper_0_2(do_dmult, cpu_T[0], cpu_T[1]); | |
2035 | 2093 | opn = "dmult"; |
2036 | 2094 | break; |
2037 | 2095 | case OPC_DMULTU: |
2038 | - tcg_gen_helper_0_0(do_dmultu); | |
2096 | + tcg_gen_helper_0_2(do_dmultu, cpu_T[0], cpu_T[1]); | |
2039 | 2097 | opn = "dmultu"; |
2040 | 2098 | break; |
2041 | 2099 | #endif |
... | ... | @@ -2181,59 +2239,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, |
2181 | 2239 | |
2182 | 2240 | switch (opc) { |
2183 | 2241 | case OPC_VR54XX_MULS: |
2184 | - tcg_gen_helper_0_0(do_muls); | |
2242 | + tcg_gen_helper_1_2(do_muls, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2185 | 2243 | opn = "muls"; |
2186 | 2244 | break; |
2187 | 2245 | case OPC_VR54XX_MULSU: |
2188 | - tcg_gen_helper_0_0(do_mulsu); | |
2246 | + tcg_gen_helper_1_2(do_mulsu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2189 | 2247 | opn = "mulsu"; |
2190 | 2248 | break; |
2191 | 2249 | case OPC_VR54XX_MACC: |
2192 | - tcg_gen_helper_0_0(do_macc); | |
2250 | + tcg_gen_helper_1_2(do_macc, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2193 | 2251 | opn = "macc"; |
2194 | 2252 | break; |
2195 | 2253 | case OPC_VR54XX_MACCU: |
2196 | - tcg_gen_helper_0_0(do_maccu); | |
2254 | + tcg_gen_helper_1_2(do_maccu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2197 | 2255 | opn = "maccu"; |
2198 | 2256 | break; |
2199 | 2257 | case OPC_VR54XX_MSAC: |
2200 | - tcg_gen_helper_0_0(do_msac); | |
2258 | + tcg_gen_helper_1_2(do_msac, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2201 | 2259 | opn = "msac"; |
2202 | 2260 | break; |
2203 | 2261 | case OPC_VR54XX_MSACU: |
2204 | - tcg_gen_helper_0_0(do_msacu); | |
2262 | + tcg_gen_helper_1_2(do_msacu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2205 | 2263 | opn = "msacu"; |
2206 | 2264 | break; |
2207 | 2265 | case OPC_VR54XX_MULHI: |
2208 | - tcg_gen_helper_0_0(do_mulhi); | |
2266 | + tcg_gen_helper_1_2(do_mulhi, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2209 | 2267 | opn = "mulhi"; |
2210 | 2268 | break; |
2211 | 2269 | case OPC_VR54XX_MULHIU: |
2212 | - tcg_gen_helper_0_0(do_mulhiu); | |
2270 | + tcg_gen_helper_1_2(do_mulhiu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2213 | 2271 | opn = "mulhiu"; |
2214 | 2272 | break; |
2215 | 2273 | case OPC_VR54XX_MULSHI: |
2216 | - tcg_gen_helper_0_0(do_mulshi); | |
2274 | + tcg_gen_helper_1_2(do_mulshi, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2217 | 2275 | opn = "mulshi"; |
2218 | 2276 | break; |
2219 | 2277 | case OPC_VR54XX_MULSHIU: |
2220 | - tcg_gen_helper_0_0(do_mulshiu); | |
2278 | + tcg_gen_helper_1_2(do_mulshiu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2221 | 2279 | opn = "mulshiu"; |
2222 | 2280 | break; |
2223 | 2281 | case OPC_VR54XX_MACCHI: |
2224 | - tcg_gen_helper_0_0(do_macchi); | |
2282 | + tcg_gen_helper_1_2(do_macchi, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2225 | 2283 | opn = "macchi"; |
2226 | 2284 | break; |
2227 | 2285 | case OPC_VR54XX_MACCHIU: |
2228 | - tcg_gen_helper_0_0(do_macchiu); | |
2286 | + tcg_gen_helper_1_2(do_macchiu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2229 | 2287 | opn = "macchiu"; |
2230 | 2288 | break; |
2231 | 2289 | case OPC_VR54XX_MSACHI: |
2232 | - tcg_gen_helper_0_0(do_msachi); | |
2290 | + tcg_gen_helper_1_2(do_msachi, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2233 | 2291 | opn = "msachi"; |
2234 | 2292 | break; |
2235 | 2293 | case OPC_VR54XX_MSACHIU: |
2236 | - tcg_gen_helper_0_0(do_msachiu); | |
2294 | + tcg_gen_helper_1_2(do_msachiu, cpu_T[0], cpu_T[0], cpu_T[1]); | |
2237 | 2295 | opn = "msachiu"; |
2238 | 2296 | break; |
2239 | 2297 | default: |
... | ... | @@ -2257,20 +2315,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, |
2257 | 2315 | gen_load_gpr(cpu_T[0], rs); |
2258 | 2316 | switch (opc) { |
2259 | 2317 | case OPC_CLO: |
2260 | - tcg_gen_helper_0_0(do_clo); | |
2318 | + tcg_gen_helper_1_1(do_clo, cpu_T[0], cpu_T[0]); | |
2261 | 2319 | opn = "clo"; |
2262 | 2320 | break; |
2263 | 2321 | case OPC_CLZ: |
2264 | - tcg_gen_helper_0_0(do_clz); | |
2322 | + tcg_gen_helper_1_1(do_clz, cpu_T[0], cpu_T[0]); | |
2265 | 2323 | opn = "clz"; |
2266 | 2324 | break; |
2267 | 2325 | #if defined(TARGET_MIPS64) |
2268 | 2326 | case OPC_DCLO: |
2269 | - tcg_gen_helper_0_0(do_dclo); | |
2327 | + tcg_gen_helper_1_1(do_dclo, cpu_T[0], cpu_T[0]); | |
2270 | 2328 | opn = "dclo"; |
2271 | 2329 | break; |
2272 | 2330 | case OPC_DCLZ: |
2273 | - tcg_gen_helper_0_0(do_dclz); | |
2331 | + tcg_gen_helper_1_1(do_dclz, cpu_T[0], cpu_T[0]); | |
2274 | 2332 | opn = "dclz"; |
2275 | 2333 | break; |
2276 | 2334 | #endif |
... | ... | @@ -2288,6 +2346,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, |
2288 | 2346 | int rs, int rt, int16_t imm) |
2289 | 2347 | { |
2290 | 2348 | int cond; |
2349 | + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); | |
2350 | + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); | |
2291 | 2351 | |
2292 | 2352 | cond = 0; |
2293 | 2353 | /* Load needed operands */ |
... | ... | @@ -2300,8 +2360,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, |
2300 | 2360 | case OPC_TNE: |
2301 | 2361 | /* Compare two registers */ |
2302 | 2362 | if (rs != rt) { |
2303 | - gen_load_gpr(cpu_T[0], rs); | |
2304 | - gen_load_gpr(cpu_T[1], rt); | |
2363 | + gen_load_gpr(t0, rs); | |
2364 | + gen_load_gpr(t1, rt); | |
2305 | 2365 | cond = 1; |
2306 | 2366 | } |
2307 | 2367 | break; |
... | ... | @@ -2313,8 +2373,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, |
2313 | 2373 | case OPC_TNEI: |
2314 | 2374 | /* Compare register to immediate */ |
2315 | 2375 | if (rs != 0 || imm != 0) { |
2316 | - gen_load_gpr(cpu_T[0], rs); | |
2317 | - tcg_gen_movi_tl(cpu_T[1], (int32_t)imm); | |
2376 | + gen_load_gpr(t0, rs); | |
2377 | + tcg_gen_movi_tl(t1, (int32_t)imm); | |
2318 | 2378 | cond = 1; |
2319 | 2379 | } |
2320 | 2380 | break; |
... | ... | @@ -2328,7 +2388,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, |
2328 | 2388 | case OPC_TGEU: /* rs >= rs unsigned */ |
2329 | 2389 | case OPC_TGEIU: /* r0 >= 0 unsigned */ |
2330 | 2390 | /* Always trap */ |
2331 | - tcg_gen_movi_tl(cpu_T[0], 1); | |
2391 | + tcg_gen_movi_tl(t0, 1); | |
2332 | 2392 | break; |
2333 | 2393 | case OPC_TLT: /* rs < rs */ |
2334 | 2394 | case OPC_TLTI: /* r0 < 0 */ |
... | ... | @@ -2337,53 +2397,56 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, |
2337 | 2397 | case OPC_TNE: /* rs != rs */ |
2338 | 2398 | case OPC_TNEI: /* r0 != 0 */ |
2339 | 2399 | /* Never trap: treat as NOP. */ |
2340 | - return; | |
2400 | + goto out; | |
2341 | 2401 | default: |
2342 | 2402 | MIPS_INVAL("trap"); |
2343 | 2403 | generate_exception(ctx, EXCP_RI); |
2344 | - return; | |
2404 | + goto out; | |
2345 | 2405 | } |
2346 | 2406 | } else { |
2347 | 2407 | switch (opc) { |
2348 | 2408 | case OPC_TEQ: |
2349 | 2409 | case OPC_TEQI: |
2350 | - gen_op_eq(); | |
2410 | + gen_op_eq(t0, t1); | |
2351 | 2411 | break; |
2352 | 2412 | case OPC_TGE: |
2353 | 2413 | case OPC_TGEI: |
2354 | - gen_op_ge(); | |
2414 | + gen_op_ge(t0, t1); | |
2355 | 2415 | break; |
2356 | 2416 | case OPC_TGEU: |
2357 | 2417 | case OPC_TGEIU: |
2358 | - gen_op_geu(); | |
2418 | + gen_op_geu(t0, t1); | |
2359 | 2419 | break; |
2360 | 2420 | case OPC_TLT: |
2361 | 2421 | case OPC_TLTI: |
2362 | - gen_op_lt(); | |
2422 | + gen_op_lt(t0, t1); | |
2363 | 2423 | break; |
2364 | 2424 | case OPC_TLTU: |
2365 | 2425 | case OPC_TLTIU: |
2366 | - gen_op_ltu(); | |
2426 | + gen_op_ltu(t0, t1); | |
2367 | 2427 | break; |
2368 | 2428 | case OPC_TNE: |
2369 | 2429 | case OPC_TNEI: |
2370 | - gen_op_ne(); | |
2430 | + gen_op_ne(t0, t1); | |
2371 | 2431 | break; |
2372 | 2432 | default: |
2373 | 2433 | MIPS_INVAL("trap"); |
2374 | 2434 | generate_exception(ctx, EXCP_RI); |
2375 | - return; | |
2435 | + goto out; | |
2376 | 2436 | } |
2377 | 2437 | } |
2378 | 2438 | save_cpu_state(ctx, 1); |
2379 | 2439 | { |
2380 | 2440 | int l1 = gen_new_label(); |
2381 | 2441 | |
2382 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1); | |
2383 | - tcg_gen_helper_0_1i(do_raise_exception, EXCP_TRAP); | |
2442 | + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2443 | + tcg_gen_helper_0_i(do_raise_exception, EXCP_TRAP); | |
2384 | 2444 | gen_set_label(l1); |
2385 | 2445 | } |
2386 | 2446 | ctx->bstate = BS_STOP; |
2447 | + out: | |
2448 | + tcg_temp_free(t0); | |
2449 | + tcg_temp_free(t1); | |
2387 | 2450 | } |
2388 | 2451 | |
2389 | 2452 | static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
... | ... | @@ -2546,69 +2609,69 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, |
2546 | 2609 | } else { |
2547 | 2610 | switch (opc) { |
2548 | 2611 | case OPC_BEQ: |
2549 | - gen_op_eq(); | |
2612 | + gen_op_eq(cpu_T[0], cpu_T[1]); | |
2550 | 2613 | MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx, |
2551 | 2614 | regnames[rs], regnames[rt], btarget); |
2552 | 2615 | goto not_likely; |
2553 | 2616 | case OPC_BEQL: |
2554 | - gen_op_eq(); | |
2617 | + gen_op_eq(cpu_T[0], cpu_T[1]); | |
2555 | 2618 | MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx, |
2556 | 2619 | regnames[rs], regnames[rt], btarget); |
2557 | 2620 | goto likely; |
2558 | 2621 | case OPC_BNE: |
2559 | - gen_op_ne(); | |
2622 | + gen_op_ne(cpu_T[0], cpu_T[1]); | |
2560 | 2623 | MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx, |
2561 | 2624 | regnames[rs], regnames[rt], btarget); |
2562 | 2625 | goto not_likely; |
2563 | 2626 | case OPC_BNEL: |
2564 | - gen_op_ne(); | |
2627 | + gen_op_ne(cpu_T[0], cpu_T[1]); | |
2565 | 2628 | MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx, |
2566 | 2629 | regnames[rs], regnames[rt], btarget); |
2567 | 2630 | goto likely; |
2568 | 2631 | case OPC_BGEZ: |
2569 | - gen_op_gez(); | |
2632 | + gen_op_gez(cpu_T[0]); | |
2570 | 2633 | MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2571 | 2634 | goto not_likely; |
2572 | 2635 | case OPC_BGEZL: |
2573 | - gen_op_gez(); | |
2636 | + gen_op_gez(cpu_T[0]); | |
2574 | 2637 | MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2575 | 2638 | goto likely; |
2576 | 2639 | case OPC_BGEZAL: |
2577 | - gen_op_gez(); | |
2640 | + gen_op_gez(cpu_T[0]); | |
2578 | 2641 | MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2579 | 2642 | blink = 31; |
2580 | 2643 | goto not_likely; |
2581 | 2644 | case OPC_BGEZALL: |
2582 | - gen_op_gez(); | |
2645 | + gen_op_gez(cpu_T[0]); | |
2583 | 2646 | blink = 31; |
2584 | 2647 | MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2585 | 2648 | goto likely; |
2586 | 2649 | case OPC_BGTZ: |
2587 | - gen_op_gtz(); | |
2650 | + gen_op_gtz(cpu_T[0]); | |
2588 | 2651 | MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2589 | 2652 | goto not_likely; |
2590 | 2653 | case OPC_BGTZL: |
2591 | - gen_op_gtz(); | |
2654 | + gen_op_gtz(cpu_T[0]); | |
2592 | 2655 | MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2593 | 2656 | goto likely; |
2594 | 2657 | case OPC_BLEZ: |
2595 | - gen_op_lez(); | |
2658 | + gen_op_lez(cpu_T[0]); | |
2596 | 2659 | MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2597 | 2660 | goto not_likely; |
2598 | 2661 | case OPC_BLEZL: |
2599 | - gen_op_lez(); | |
2662 | + gen_op_lez(cpu_T[0]); | |
2600 | 2663 | MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2601 | 2664 | goto likely; |
2602 | 2665 | case OPC_BLTZ: |
2603 | - gen_op_ltz(); | |
2666 | + gen_op_ltz(cpu_T[0]); | |
2604 | 2667 | MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2605 | 2668 | goto not_likely; |
2606 | 2669 | case OPC_BLTZL: |
2607 | - gen_op_ltz(); | |
2670 | + gen_op_ltz(cpu_T[0]); | |
2608 | 2671 | MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2609 | 2672 | goto likely; |
2610 | 2673 | case OPC_BLTZAL: |
2611 | - gen_op_ltz(); | |
2674 | + gen_op_ltz(cpu_T[0]); | |
2612 | 2675 | blink = 31; |
2613 | 2676 | MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2614 | 2677 | not_likely: |
... | ... | @@ -2616,7 +2679,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, |
2616 | 2679 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond)); |
2617 | 2680 | break; |
2618 | 2681 | case OPC_BLTZALL: |
2619 | - gen_op_ltz(); | |
2682 | + gen_op_ltz(cpu_T[0]); | |
2620 | 2683 | blink = 31; |
2621 | 2684 | MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget); |
2622 | 2685 | likely: |
... | ... | @@ -2648,49 +2711,49 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, |
2648 | 2711 | case OPC_EXT: |
2649 | 2712 | if (lsb + msb > 31) |
2650 | 2713 | goto fail; |
2651 | - tcg_gen_helper_0_2ii(do_ext, lsb, msb + 1); | |
2714 | + tcg_gen_helper_1_2ii(do_ext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1); | |
2652 | 2715 | break; |
2653 | 2716 | #if defined(TARGET_MIPS64) |
2654 | 2717 | case OPC_DEXTM: |
2655 | 2718 | if (lsb + msb > 63) |
2656 | 2719 | goto fail; |
2657 | - tcg_gen_helper_0_2ii(do_dext, lsb, msb + 1 + 32); | |
2720 | + tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1 + 32); | |
2658 | 2721 | break; |
2659 | 2722 | case OPC_DEXTU: |
2660 | 2723 | if (lsb + msb > 63) |
2661 | 2724 | goto fail; |
2662 | - tcg_gen_helper_0_2ii(do_dext, lsb + 32, msb + 1); | |
2725 | + tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb + 1); | |
2663 | 2726 | break; |
2664 | 2727 | case OPC_DEXT: |
2665 | 2728 | if (lsb + msb > 63) |
2666 | 2729 | goto fail; |
2667 | - tcg_gen_helper_0_2ii(do_dext, lsb, msb + 1); | |
2730 | + tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1); | |
2668 | 2731 | break; |
2669 | 2732 | #endif |
2670 | 2733 | case OPC_INS: |
2671 | 2734 | if (lsb > msb) |
2672 | 2735 | goto fail; |
2673 | 2736 | gen_load_gpr(cpu_T[0], rt); |
2674 | - tcg_gen_helper_0_2ii(do_ins, lsb, msb - lsb + 1); | |
2737 | + tcg_gen_helper_1_2ii(do_ins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1); | |
2675 | 2738 | break; |
2676 | 2739 | #if defined(TARGET_MIPS64) |
2677 | 2740 | case OPC_DINSM: |
2678 | 2741 | if (lsb > msb) |
2679 | 2742 | goto fail; |
2680 | 2743 | gen_load_gpr(cpu_T[0], rt); |
2681 | - tcg_gen_helper_0_2ii(do_dins, lsb, msb - lsb + 1 + 32); | |
2744 | + tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1 + 32); | |
2682 | 2745 | break; |
2683 | 2746 | case OPC_DINSU: |
2684 | 2747 | if (lsb > msb) |
2685 | 2748 | goto fail; |
2686 | 2749 | gen_load_gpr(cpu_T[0], rt); |
2687 | - tcg_gen_helper_0_2ii(do_dins, lsb + 32, msb - lsb + 1); | |
2750 | + tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb - lsb + 1); | |
2688 | 2751 | break; |
2689 | 2752 | case OPC_DINS: |
2690 | 2753 | if (lsb > msb) |
2691 | 2754 | goto fail; |
2692 | 2755 | gen_load_gpr(cpu_T[0], rt); |
2693 | - tcg_gen_helper_0_2ii(do_dins, lsb, msb - lsb + 1); | |
2756 | + tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1); | |
2694 | 2757 | break; |
2695 | 2758 | #endif |
2696 | 2759 | default: |
... | ... | @@ -2750,17 +2813,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
2750 | 2813 | break; |
2751 | 2814 | case 1: |
2752 | 2815 | check_insn(env, ctx, ASE_MT); |
2753 | - tcg_gen_helper_0_0(do_mfc0_mvpcontrol); | |
2816 | + tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]); | |
2754 | 2817 | rn = "MVPControl"; |
2755 | 2818 | break; |
2756 | 2819 | case 2: |
2757 | 2820 | check_insn(env, ctx, ASE_MT); |
2758 | - tcg_gen_helper_0_0(do_mfc0_mvpconf0); | |
2821 | + tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]); | |
2759 | 2822 | rn = "MVPConf0"; |
2760 | 2823 | break; |
2761 | 2824 | case 3: |
2762 | 2825 | check_insn(env, ctx, ASE_MT); |
2763 | - tcg_gen_helper_0_0(do_mfc0_mvpconf1); | |
2826 | + tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]); | |
2764 | 2827 | rn = "MVPConf1"; |
2765 | 2828 | break; |
2766 | 2829 | default: |
... | ... | @@ -2770,7 +2833,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
2770 | 2833 | case 1: |
2771 | 2834 | switch (sel) { |
2772 | 2835 | case 0: |
2773 | - tcg_gen_helper_0_0(do_mfc0_random); | |
2836 | + tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]); | |
2774 | 2837 | rn = "Random"; |
2775 | 2838 | break; |
2776 | 2839 | case 1: |
... | ... | @@ -2821,37 +2884,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
2821 | 2884 | break; |
2822 | 2885 | case 1: |
2823 | 2886 | check_insn(env, ctx, ASE_MT); |
2824 | - tcg_gen_helper_0_0(do_mfc0_tcstatus); | |
2887 | + tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]); | |
2825 | 2888 | rn = "TCStatus"; |
2826 | 2889 | break; |
2827 | 2890 | case 2: |
2828 | 2891 | check_insn(env, ctx, ASE_MT); |
2829 | - tcg_gen_helper_0_0(do_mfc0_tcbind); | |
2892 | + tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]); | |
2830 | 2893 | rn = "TCBind"; |
2831 | 2894 | break; |
2832 | 2895 | case 3: |
2833 | 2896 | check_insn(env, ctx, ASE_MT); |
2834 | - tcg_gen_helper_0_0(do_mfc0_tcrestart); | |
2897 | + tcg_gen_helper_1_1(do_mfc0_tcrestart, cpu_T[0], cpu_T[0]); | |
2835 | 2898 | rn = "TCRestart"; |
2836 | 2899 | break; |
2837 | 2900 | case 4: |
2838 | 2901 | check_insn(env, ctx, ASE_MT); |
2839 | - tcg_gen_helper_0_0(do_mfc0_tchalt); | |
2902 | + tcg_gen_helper_1_1(do_mfc0_tchalt, cpu_T[0], cpu_T[0]); | |
2840 | 2903 | rn = "TCHalt"; |
2841 | 2904 | break; |
2842 | 2905 | case 5: |
2843 | 2906 | check_insn(env, ctx, ASE_MT); |
2844 | - tcg_gen_helper_0_0(do_mfc0_tccontext); | |
2907 | + tcg_gen_helper_1_1(do_mfc0_tccontext, cpu_T[0], cpu_T[0]); | |
2845 | 2908 | rn = "TCContext"; |
2846 | 2909 | break; |
2847 | 2910 | case 6: |
2848 | 2911 | check_insn(env, ctx, ASE_MT); |
2849 | - tcg_gen_helper_0_0(do_mfc0_tcschedule); | |
2912 | + tcg_gen_helper_1_1(do_mfc0_tcschedule, cpu_T[0], cpu_T[0]); | |
2850 | 2913 | rn = "TCSchedule"; |
2851 | 2914 | break; |
2852 | 2915 | case 7: |
2853 | 2916 | check_insn(env, ctx, ASE_MT); |
2854 | - tcg_gen_helper_0_0(do_mfc0_tcschefback); | |
2917 | + tcg_gen_helper_1_1(do_mfc0_tcschefback, cpu_T[0], cpu_T[0]); | |
2855 | 2918 | rn = "TCScheFBack"; |
2856 | 2919 | break; |
2857 | 2920 | default: |
... | ... | @@ -2877,7 +2940,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
2877 | 2940 | rn = "Context"; |
2878 | 2941 | break; |
2879 | 2942 | case 1: |
2880 | -// tcg_gen_helper_0_0(do_mfc0_contextconfig); /* SmartMIPS ASE */ | |
2943 | +// tcg_gen_helper_1_1(do_mfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */ | |
2881 | 2944 | rn = "ContextConfig"; |
2882 | 2945 | // break; |
2883 | 2946 | default: |
... | ... | @@ -2959,7 +3022,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
2959 | 3022 | case 9: |
2960 | 3023 | switch (sel) { |
2961 | 3024 | case 0: |
2962 | - tcg_gen_helper_0_0(do_mfc0_count); | |
3025 | + tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]); | |
2963 | 3026 | rn = "Count"; |
2964 | 3027 | break; |
2965 | 3028 | /* 6,7 are implementation dependent */ |
... | ... | @@ -3085,7 +3148,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3085 | 3148 | case 17: |
3086 | 3149 | switch (sel) { |
3087 | 3150 | case 0: |
3088 | - tcg_gen_helper_0_0(do_mfc0_lladdr); | |
3151 | + tcg_gen_helper_1_1(do_mfc0_lladdr, cpu_T[0], cpu_T[0]); | |
3089 | 3152 | rn = "LLAddr"; |
3090 | 3153 | break; |
3091 | 3154 | default: |
... | ... | @@ -3095,7 +3158,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3095 | 3158 | case 18: |
3096 | 3159 | switch (sel) { |
3097 | 3160 | case 0 ... 7: |
3098 | - tcg_gen_helper_0_1i(do_mfc0_watchlo, sel); | |
3161 | + tcg_gen_helper_1_1i(do_mfc0_watchlo, cpu_T[0], cpu_T[0], sel); | |
3099 | 3162 | rn = "WatchLo"; |
3100 | 3163 | break; |
3101 | 3164 | default: |
... | ... | @@ -3105,7 +3168,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3105 | 3168 | case 19: |
3106 | 3169 | switch (sel) { |
3107 | 3170 | case 0 ...7: |
3108 | - tcg_gen_helper_0_1i(do_mfc0_watchhi, sel); | |
3171 | + tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel); | |
3109 | 3172 | rn = "WatchHi"; |
3110 | 3173 | break; |
3111 | 3174 | default: |
... | ... | @@ -3144,23 +3207,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3144 | 3207 | case 23: |
3145 | 3208 | switch (sel) { |
3146 | 3209 | case 0: |
3147 | - tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */ | |
3210 | + tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */ | |
3148 | 3211 | rn = "Debug"; |
3149 | 3212 | break; |
3150 | 3213 | case 1: |
3151 | -// tcg_gen_helper_0_0(do_mfc0_tracecontrol); /* PDtrace support */ | |
3214 | +// tcg_gen_helper_1_1(do_mfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
3152 | 3215 | rn = "TraceControl"; |
3153 | 3216 | // break; |
3154 | 3217 | case 2: |
3155 | -// tcg_gen_helper_0_0(do_mfc0_tracecontrol2); /* PDtrace support */ | |
3218 | +// tcg_gen_helper_1_1(do_mfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
3156 | 3219 | rn = "TraceControl2"; |
3157 | 3220 | // break; |
3158 | 3221 | case 3: |
3159 | -// tcg_gen_helper_0_0(do_mfc0_usertracedata); /* PDtrace support */ | |
3222 | +// tcg_gen_helper_1_1(do_mfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
3160 | 3223 | rn = "UserTraceData"; |
3161 | 3224 | // break; |
3162 | 3225 | case 4: |
3163 | -// tcg_gen_helper_0_0(do_mfc0_debug); /* PDtrace support */ | |
3226 | +// tcg_gen_helper_1_1(do_mfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
3164 | 3227 | rn = "TraceBPC"; |
3165 | 3228 | // break; |
3166 | 3229 | default: |
... | ... | @@ -3186,31 +3249,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3186 | 3249 | rn = "Performance0"; |
3187 | 3250 | break; |
3188 | 3251 | case 1: |
3189 | -// tcg_gen_helper_0_0(do_mfc0_performance1); | |
3252 | +// tcg_gen_helper_1_1(do_mfc0_performance1, cpu_T[0], cpu_T[0]); | |
3190 | 3253 | rn = "Performance1"; |
3191 | 3254 | // break; |
3192 | 3255 | case 2: |
3193 | -// tcg_gen_helper_0_0(do_mfc0_performance2); | |
3256 | +// tcg_gen_helper_1_1(do_mfc0_performance2, cpu_T[0], cpu_T[0]); | |
3194 | 3257 | rn = "Performance2"; |
3195 | 3258 | // break; |
3196 | 3259 | case 3: |
3197 | -// tcg_gen_helper_0_0(do_mfc0_performance3); | |
3260 | +// tcg_gen_helper_1_1(do_mfc0_performance3, cpu_T[0], cpu_T[0]); | |
3198 | 3261 | rn = "Performance3"; |
3199 | 3262 | // break; |
3200 | 3263 | case 4: |
3201 | -// tcg_gen_helper_0_0(do_mfc0_performance4); | |
3264 | +// tcg_gen_helper_1_1(do_mfc0_performance4, cpu_T[0], cpu_T[0]); | |
3202 | 3265 | rn = "Performance4"; |
3203 | 3266 | // break; |
3204 | 3267 | case 5: |
3205 | -// tcg_gen_helper_0_0(do_mfc0_performance5); | |
3268 | +// tcg_gen_helper_1_1(do_mfc0_performance5, cpu_T[0], cpu_T[0]); | |
3206 | 3269 | rn = "Performance5"; |
3207 | 3270 | // break; |
3208 | 3271 | case 6: |
3209 | -// tcg_gen_helper_0_0(do_mfc0_performance6); | |
3272 | +// tcg_gen_helper_1_1(do_mfc0_performance6, cpu_T[0], cpu_T[0]); | |
3210 | 3273 | rn = "Performance6"; |
3211 | 3274 | // break; |
3212 | 3275 | case 7: |
3213 | -// tcg_gen_helper_0_0(do_mfc0_performance7); | |
3276 | +// tcg_gen_helper_1_1(do_mfc0_performance7, cpu_T[0], cpu_T[0]); | |
3214 | 3277 | rn = "Performance7"; |
3215 | 3278 | // break; |
3216 | 3279 | default: |
... | ... | @@ -3324,12 +3387,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3324 | 3387 | case 0: |
3325 | 3388 | switch (sel) { |
3326 | 3389 | case 0: |
3327 | - tcg_gen_helper_0_0(do_mtc0_index); | |
3390 | + tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]); | |
3328 | 3391 | rn = "Index"; |
3329 | 3392 | break; |
3330 | 3393 | case 1: |
3331 | 3394 | check_insn(env, ctx, ASE_MT); |
3332 | - tcg_gen_helper_0_0(do_mtc0_mvpcontrol); | |
3395 | + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]); | |
3333 | 3396 | rn = "MVPControl"; |
3334 | 3397 | break; |
3335 | 3398 | case 2: |
... | ... | @@ -3354,22 +3417,22 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3354 | 3417 | break; |
3355 | 3418 | case 1: |
3356 | 3419 | check_insn(env, ctx, ASE_MT); |
3357 | - tcg_gen_helper_0_0(do_mtc0_vpecontrol); | |
3420 | + tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]); | |
3358 | 3421 | rn = "VPEControl"; |
3359 | 3422 | break; |
3360 | 3423 | case 2: |
3361 | 3424 | check_insn(env, ctx, ASE_MT); |
3362 | - tcg_gen_helper_0_0(do_mtc0_vpeconf0); | |
3425 | + tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]); | |
3363 | 3426 | rn = "VPEConf0"; |
3364 | 3427 | break; |
3365 | 3428 | case 3: |
3366 | 3429 | check_insn(env, ctx, ASE_MT); |
3367 | - tcg_gen_helper_0_0(do_mtc0_vpeconf1); | |
3430 | + tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]); | |
3368 | 3431 | rn = "VPEConf1"; |
3369 | 3432 | break; |
3370 | 3433 | case 4: |
3371 | 3434 | check_insn(env, ctx, ASE_MT); |
3372 | - tcg_gen_helper_0_0(do_mtc0_yqmask); | |
3435 | + tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]); | |
3373 | 3436 | rn = "YQMask"; |
3374 | 3437 | break; |
3375 | 3438 | case 5: |
... | ... | @@ -3384,7 +3447,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3384 | 3447 | break; |
3385 | 3448 | case 7: |
3386 | 3449 | check_insn(env, ctx, ASE_MT); |
3387 | - tcg_gen_helper_0_0(do_mtc0_vpeopt); | |
3450 | + tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]); | |
3388 | 3451 | rn = "VPEOpt"; |
3389 | 3452 | break; |
3390 | 3453 | default: |
... | ... | @@ -3394,42 +3457,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3394 | 3457 | case 2: |
3395 | 3458 | switch (sel) { |
3396 | 3459 | case 0: |
3397 | - tcg_gen_helper_0_0(do_mtc0_entrylo0); | |
3460 | + tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]); | |
3398 | 3461 | rn = "EntryLo0"; |
3399 | 3462 | break; |
3400 | 3463 | case 1: |
3401 | 3464 | check_insn(env, ctx, ASE_MT); |
3402 | - tcg_gen_helper_0_0(do_mtc0_tcstatus); | |
3465 | + tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]); | |
3403 | 3466 | rn = "TCStatus"; |
3404 | 3467 | break; |
3405 | 3468 | case 2: |
3406 | 3469 | check_insn(env, ctx, ASE_MT); |
3407 | - tcg_gen_helper_0_0(do_mtc0_tcbind); | |
3470 | + tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]); | |
3408 | 3471 | rn = "TCBind"; |
3409 | 3472 | break; |
3410 | 3473 | case 3: |
3411 | 3474 | check_insn(env, ctx, ASE_MT); |
3412 | - tcg_gen_helper_0_0(do_mtc0_tcrestart); | |
3475 | + tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]); | |
3413 | 3476 | rn = "TCRestart"; |
3414 | 3477 | break; |
3415 | 3478 | case 4: |
3416 | 3479 | check_insn(env, ctx, ASE_MT); |
3417 | - tcg_gen_helper_0_0(do_mtc0_tchalt); | |
3480 | + tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]); | |
3418 | 3481 | rn = "TCHalt"; |
3419 | 3482 | break; |
3420 | 3483 | case 5: |
3421 | 3484 | check_insn(env, ctx, ASE_MT); |
3422 | - tcg_gen_helper_0_0(do_mtc0_tccontext); | |
3485 | + tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]); | |
3423 | 3486 | rn = "TCContext"; |
3424 | 3487 | break; |
3425 | 3488 | case 6: |
3426 | 3489 | check_insn(env, ctx, ASE_MT); |
3427 | - tcg_gen_helper_0_0(do_mtc0_tcschedule); | |
3490 | + tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]); | |
3428 | 3491 | rn = "TCSchedule"; |
3429 | 3492 | break; |
3430 | 3493 | case 7: |
3431 | 3494 | check_insn(env, ctx, ASE_MT); |
3432 | - tcg_gen_helper_0_0(do_mtc0_tcschefback); | |
3495 | + tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]); | |
3433 | 3496 | rn = "TCScheFBack"; |
3434 | 3497 | break; |
3435 | 3498 | default: |
... | ... | @@ -3439,7 +3502,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3439 | 3502 | case 3: |
3440 | 3503 | switch (sel) { |
3441 | 3504 | case 0: |
3442 | - tcg_gen_helper_0_0(do_mtc0_entrylo1); | |
3505 | + tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]); | |
3443 | 3506 | rn = "EntryLo1"; |
3444 | 3507 | break; |
3445 | 3508 | default: |
... | ... | @@ -3449,11 +3512,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3449 | 3512 | case 4: |
3450 | 3513 | switch (sel) { |
3451 | 3514 | case 0: |
3452 | - tcg_gen_helper_0_0(do_mtc0_context); | |
3515 | + tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]); | |
3453 | 3516 | rn = "Context"; |
3454 | 3517 | break; |
3455 | 3518 | case 1: |
3456 | -// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */ | |
3519 | +// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */ | |
3457 | 3520 | rn = "ContextConfig"; |
3458 | 3521 | // break; |
3459 | 3522 | default: |
... | ... | @@ -3463,12 +3526,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3463 | 3526 | case 5: |
3464 | 3527 | switch (sel) { |
3465 | 3528 | case 0: |
3466 | - tcg_gen_helper_0_0(do_mtc0_pagemask); | |
3529 | + tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]); | |
3467 | 3530 | rn = "PageMask"; |
3468 | 3531 | break; |
3469 | 3532 | case 1: |
3470 | 3533 | check_insn(env, ctx, ISA_MIPS32R2); |
3471 | - tcg_gen_helper_0_0(do_mtc0_pagegrain); | |
3534 | + tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]); | |
3472 | 3535 | rn = "PageGrain"; |
3473 | 3536 | break; |
3474 | 3537 | default: |
... | ... | @@ -3478,32 +3541,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3478 | 3541 | case 6: |
3479 | 3542 | switch (sel) { |
3480 | 3543 | case 0: |
3481 | - tcg_gen_helper_0_0(do_mtc0_wired); | |
3544 | + tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]); | |
3482 | 3545 | rn = "Wired"; |
3483 | 3546 | break; |
3484 | 3547 | case 1: |
3485 | 3548 | check_insn(env, ctx, ISA_MIPS32R2); |
3486 | - tcg_gen_helper_0_0(do_mtc0_srsconf0); | |
3549 | + tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]); | |
3487 | 3550 | rn = "SRSConf0"; |
3488 | 3551 | break; |
3489 | 3552 | case 2: |
3490 | 3553 | check_insn(env, ctx, ISA_MIPS32R2); |
3491 | - tcg_gen_helper_0_0(do_mtc0_srsconf1); | |
3554 | + tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]); | |
3492 | 3555 | rn = "SRSConf1"; |
3493 | 3556 | break; |
3494 | 3557 | case 3: |
3495 | 3558 | check_insn(env, ctx, ISA_MIPS32R2); |
3496 | - tcg_gen_helper_0_0(do_mtc0_srsconf2); | |
3559 | + tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]); | |
3497 | 3560 | rn = "SRSConf2"; |
3498 | 3561 | break; |
3499 | 3562 | case 4: |
3500 | 3563 | check_insn(env, ctx, ISA_MIPS32R2); |
3501 | - tcg_gen_helper_0_0(do_mtc0_srsconf3); | |
3564 | + tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]); | |
3502 | 3565 | rn = "SRSConf3"; |
3503 | 3566 | break; |
3504 | 3567 | case 5: |
3505 | 3568 | check_insn(env, ctx, ISA_MIPS32R2); |
3506 | - tcg_gen_helper_0_0(do_mtc0_srsconf4); | |
3569 | + tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]); | |
3507 | 3570 | rn = "SRSConf4"; |
3508 | 3571 | break; |
3509 | 3572 | default: |
... | ... | @@ -3514,7 +3577,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3514 | 3577 | switch (sel) { |
3515 | 3578 | case 0: |
3516 | 3579 | check_insn(env, ctx, ISA_MIPS32R2); |
3517 | - tcg_gen_helper_0_0(do_mtc0_hwrena); | |
3580 | + tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]); | |
3518 | 3581 | rn = "HWREna"; |
3519 | 3582 | break; |
3520 | 3583 | default: |
... | ... | @@ -3528,7 +3591,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3528 | 3591 | case 9: |
3529 | 3592 | switch (sel) { |
3530 | 3593 | case 0: |
3531 | - tcg_gen_helper_0_0(do_mtc0_count); | |
3594 | + tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]); | |
3532 | 3595 | rn = "Count"; |
3533 | 3596 | break; |
3534 | 3597 | /* 6,7 are implementation dependent */ |
... | ... | @@ -3541,7 +3604,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3541 | 3604 | case 10: |
3542 | 3605 | switch (sel) { |
3543 | 3606 | case 0: |
3544 | - tcg_gen_helper_0_0(do_mtc0_entryhi); | |
3607 | + tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]); | |
3545 | 3608 | rn = "EntryHi"; |
3546 | 3609 | break; |
3547 | 3610 | default: |
... | ... | @@ -3551,7 +3614,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3551 | 3614 | case 11: |
3552 | 3615 | switch (sel) { |
3553 | 3616 | case 0: |
3554 | - tcg_gen_helper_0_0(do_mtc0_compare); | |
3617 | + tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]); | |
3555 | 3618 | rn = "Compare"; |
3556 | 3619 | break; |
3557 | 3620 | /* 6,7 are implementation dependent */ |
... | ... | @@ -3564,7 +3627,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3564 | 3627 | case 12: |
3565 | 3628 | switch (sel) { |
3566 | 3629 | case 0: |
3567 | - tcg_gen_helper_0_0(do_mtc0_status); | |
3630 | + tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]); | |
3568 | 3631 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
3569 | 3632 | gen_save_pc(ctx->pc + 4); |
3570 | 3633 | ctx->bstate = BS_EXCP; |
... | ... | @@ -3572,14 +3635,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3572 | 3635 | break; |
3573 | 3636 | case 1: |
3574 | 3637 | check_insn(env, ctx, ISA_MIPS32R2); |
3575 | - tcg_gen_helper_0_0(do_mtc0_intctl); | |
3638 | + tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]); | |
3576 | 3639 | /* Stop translation as we may have switched the execution mode */ |
3577 | 3640 | ctx->bstate = BS_STOP; |
3578 | 3641 | rn = "IntCtl"; |
3579 | 3642 | break; |
3580 | 3643 | case 2: |
3581 | 3644 | check_insn(env, ctx, ISA_MIPS32R2); |
3582 | - tcg_gen_helper_0_0(do_mtc0_srsctl); | |
3645 | + tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]); | |
3583 | 3646 | /* Stop translation as we may have switched the execution mode */ |
3584 | 3647 | ctx->bstate = BS_STOP; |
3585 | 3648 | rn = "SRSCtl"; |
... | ... | @@ -3598,7 +3661,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3598 | 3661 | case 13: |
3599 | 3662 | switch (sel) { |
3600 | 3663 | case 0: |
3601 | - tcg_gen_helper_0_0(do_mtc0_cause); | |
3664 | + tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]); | |
3602 | 3665 | rn = "Cause"; |
3603 | 3666 | break; |
3604 | 3667 | default: |
... | ... | @@ -3625,7 +3688,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3625 | 3688 | break; |
3626 | 3689 | case 1: |
3627 | 3690 | check_insn(env, ctx, ISA_MIPS32R2); |
3628 | - tcg_gen_helper_0_0(do_mtc0_ebase); | |
3691 | + tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]); | |
3629 | 3692 | rn = "EBase"; |
3630 | 3693 | break; |
3631 | 3694 | default: |
... | ... | @@ -3635,7 +3698,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3635 | 3698 | case 16: |
3636 | 3699 | switch (sel) { |
3637 | 3700 | case 0: |
3638 | - tcg_gen_helper_0_0(do_mtc0_config0); | |
3701 | + tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]); | |
3639 | 3702 | rn = "Config"; |
3640 | 3703 | /* Stop translation as we may have switched the execution mode */ |
3641 | 3704 | ctx->bstate = BS_STOP; |
... | ... | @@ -3645,7 +3708,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3645 | 3708 | rn = "Config1"; |
3646 | 3709 | break; |
3647 | 3710 | case 2: |
3648 | - tcg_gen_helper_0_0(do_mtc0_config2); | |
3711 | + tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]); | |
3649 | 3712 | rn = "Config2"; |
3650 | 3713 | /* Stop translation as we may have switched the execution mode */ |
3651 | 3714 | ctx->bstate = BS_STOP; |
... | ... | @@ -3682,7 +3745,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3682 | 3745 | case 18: |
3683 | 3746 | switch (sel) { |
3684 | 3747 | case 0 ... 7: |
3685 | - tcg_gen_helper_0_1i(do_mtc0_watchlo, sel); | |
3748 | + tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel); | |
3686 | 3749 | rn = "WatchLo"; |
3687 | 3750 | break; |
3688 | 3751 | default: |
... | ... | @@ -3692,7 +3755,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3692 | 3755 | case 19: |
3693 | 3756 | switch (sel) { |
3694 | 3757 | case 0 ... 7: |
3695 | - tcg_gen_helper_0_1i(do_mtc0_watchhi, sel); | |
3758 | + tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel); | |
3696 | 3759 | rn = "WatchHi"; |
3697 | 3760 | break; |
3698 | 3761 | default: |
... | ... | @@ -3704,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3704 | 3767 | case 0: |
3705 | 3768 | #if defined(TARGET_MIPS64) |
3706 | 3769 | check_insn(env, ctx, ISA_MIPS3); |
3707 | - tcg_gen_helper_0_0(do_mtc0_xcontext); | |
3770 | + tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]); | |
3708 | 3771 | rn = "XContext"; |
3709 | 3772 | break; |
3710 | 3773 | #endif |
... | ... | @@ -3716,7 +3779,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3716 | 3779 | /* Officially reserved, but sel 0 is used for R1x000 framemask */ |
3717 | 3780 | switch (sel) { |
3718 | 3781 | case 0: |
3719 | - tcg_gen_helper_0_0(do_mtc0_framemask); | |
3782 | + tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]); | |
3720 | 3783 | rn = "Framemask"; |
3721 | 3784 | break; |
3722 | 3785 | default: |
... | ... | @@ -3730,20 +3793,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3730 | 3793 | case 23: |
3731 | 3794 | switch (sel) { |
3732 | 3795 | case 0: |
3733 | - tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */ | |
3796 | + tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */ | |
3734 | 3797 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
3735 | 3798 | gen_save_pc(ctx->pc + 4); |
3736 | 3799 | ctx->bstate = BS_EXCP; |
3737 | 3800 | rn = "Debug"; |
3738 | 3801 | break; |
3739 | 3802 | case 1: |
3740 | -// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */ | |
3803 | +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */ | |
3741 | 3804 | rn = "TraceControl"; |
3742 | 3805 | /* Stop translation as we may have switched the execution mode */ |
3743 | 3806 | ctx->bstate = BS_STOP; |
3744 | 3807 | // break; |
3745 | 3808 | case 2: |
3746 | -// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */ | |
3809 | +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */ | |
3747 | 3810 | rn = "TraceControl2"; |
3748 | 3811 | /* Stop translation as we may have switched the execution mode */ |
3749 | 3812 | ctx->bstate = BS_STOP; |
... | ... | @@ -3751,13 +3814,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3751 | 3814 | case 3: |
3752 | 3815 | /* Stop translation as we may have switched the execution mode */ |
3753 | 3816 | ctx->bstate = BS_STOP; |
3754 | -// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */ | |
3817 | +// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */ | |
3755 | 3818 | rn = "UserTraceData"; |
3756 | 3819 | /* Stop translation as we may have switched the execution mode */ |
3757 | 3820 | ctx->bstate = BS_STOP; |
3758 | 3821 | // break; |
3759 | 3822 | case 4: |
3760 | -// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */ | |
3823 | +// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */ | |
3761 | 3824 | /* Stop translation as we may have switched the execution mode */ |
3762 | 3825 | ctx->bstate = BS_STOP; |
3763 | 3826 | rn = "TraceBPC"; |
... | ... | @@ -3780,35 +3843,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3780 | 3843 | case 25: |
3781 | 3844 | switch (sel) { |
3782 | 3845 | case 0: |
3783 | - tcg_gen_helper_0_0(do_mtc0_performance0); | |
3846 | + tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]); | |
3784 | 3847 | rn = "Performance0"; |
3785 | 3848 | break; |
3786 | 3849 | case 1: |
3787 | -// tcg_gen_helper_0_0(do_mtc0_performance1); | |
3850 | +// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]); | |
3788 | 3851 | rn = "Performance1"; |
3789 | 3852 | // break; |
3790 | 3853 | case 2: |
3791 | -// tcg_gen_helper_0_0(do_mtc0_performance2); | |
3854 | +// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]); | |
3792 | 3855 | rn = "Performance2"; |
3793 | 3856 | // break; |
3794 | 3857 | case 3: |
3795 | -// tcg_gen_helper_0_0(do_mtc0_performance3); | |
3858 | +// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]); | |
3796 | 3859 | rn = "Performance3"; |
3797 | 3860 | // break; |
3798 | 3861 | case 4: |
3799 | -// tcg_gen_helper_0_0(do_mtc0_performance4); | |
3862 | +// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]); | |
3800 | 3863 | rn = "Performance4"; |
3801 | 3864 | // break; |
3802 | 3865 | case 5: |
3803 | -// tcg_gen_helper_0_0(do_mtc0_performance5); | |
3866 | +// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]); | |
3804 | 3867 | rn = "Performance5"; |
3805 | 3868 | // break; |
3806 | 3869 | case 6: |
3807 | -// tcg_gen_helper_0_0(do_mtc0_performance6); | |
3870 | +// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]); | |
3808 | 3871 | rn = "Performance6"; |
3809 | 3872 | // break; |
3810 | 3873 | case 7: |
3811 | -// tcg_gen_helper_0_0(do_mtc0_performance7); | |
3874 | +// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]); | |
3812 | 3875 | rn = "Performance7"; |
3813 | 3876 | // break; |
3814 | 3877 | default: |
... | ... | @@ -3835,14 +3898,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3835 | 3898 | case 2: |
3836 | 3899 | case 4: |
3837 | 3900 | case 6: |
3838 | - tcg_gen_helper_0_0(do_mtc0_taglo); | |
3901 | + tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]); | |
3839 | 3902 | rn = "TagLo"; |
3840 | 3903 | break; |
3841 | 3904 | case 1: |
3842 | 3905 | case 3: |
3843 | 3906 | case 5: |
3844 | 3907 | case 7: |
3845 | - tcg_gen_helper_0_0(do_mtc0_datalo); | |
3908 | + tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]); | |
3846 | 3909 | rn = "DataLo"; |
3847 | 3910 | break; |
3848 | 3911 | default: |
... | ... | @@ -3855,14 +3918,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3855 | 3918 | case 2: |
3856 | 3919 | case 4: |
3857 | 3920 | case 6: |
3858 | - tcg_gen_helper_0_0(do_mtc0_taghi); | |
3921 | + tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]); | |
3859 | 3922 | rn = "TagHi"; |
3860 | 3923 | break; |
3861 | 3924 | case 1: |
3862 | 3925 | case 3: |
3863 | 3926 | case 5: |
3864 | 3927 | case 7: |
3865 | - tcg_gen_helper_0_0(do_mtc0_datahi); | |
3928 | + tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]); | |
3866 | 3929 | rn = "DataHi"; |
3867 | 3930 | break; |
3868 | 3931 | default: |
... | ... | @@ -3931,17 +3994,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3931 | 3994 | break; |
3932 | 3995 | case 1: |
3933 | 3996 | check_insn(env, ctx, ASE_MT); |
3934 | - tcg_gen_helper_0_0(do_mfc0_mvpcontrol); | |
3997 | + tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]); | |
3935 | 3998 | rn = "MVPControl"; |
3936 | 3999 | break; |
3937 | 4000 | case 2: |
3938 | 4001 | check_insn(env, ctx, ASE_MT); |
3939 | - tcg_gen_helper_0_0(do_mfc0_mvpconf0); | |
4002 | + tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]); | |
3940 | 4003 | rn = "MVPConf0"; |
3941 | 4004 | break; |
3942 | 4005 | case 3: |
3943 | 4006 | check_insn(env, ctx, ASE_MT); |
3944 | - tcg_gen_helper_0_0(do_mfc0_mvpconf1); | |
4007 | + tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]); | |
3945 | 4008 | rn = "MVPConf1"; |
3946 | 4009 | break; |
3947 | 4010 | default: |
... | ... | @@ -3951,7 +4014,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3951 | 4014 | case 1: |
3952 | 4015 | switch (sel) { |
3953 | 4016 | case 0: |
3954 | - tcg_gen_helper_0_0(do_mfc0_random); | |
4017 | + tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]); | |
3955 | 4018 | rn = "Random"; |
3956 | 4019 | break; |
3957 | 4020 | case 1: |
... | ... | @@ -4001,37 +4064,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4001 | 4064 | break; |
4002 | 4065 | case 1: |
4003 | 4066 | check_insn(env, ctx, ASE_MT); |
4004 | - tcg_gen_helper_0_0(do_mfc0_tcstatus); | |
4067 | + tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]); | |
4005 | 4068 | rn = "TCStatus"; |
4006 | 4069 | break; |
4007 | 4070 | case 2: |
4008 | 4071 | check_insn(env, ctx, ASE_MT); |
4009 | - tcg_gen_helper_0_0(do_mfc0_tcbind); | |
4072 | + tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]); | |
4010 | 4073 | rn = "TCBind"; |
4011 | 4074 | break; |
4012 | 4075 | case 3: |
4013 | 4076 | check_insn(env, ctx, ASE_MT); |
4014 | - tcg_gen_helper_0_0(do_dmfc0_tcrestart); | |
4077 | + tcg_gen_helper_1_1(do_dmfc0_tcrestart, cpu_T[0], cpu_T[0]); | |
4015 | 4078 | rn = "TCRestart"; |
4016 | 4079 | break; |
4017 | 4080 | case 4: |
4018 | 4081 | check_insn(env, ctx, ASE_MT); |
4019 | - tcg_gen_helper_0_0(do_dmfc0_tchalt); | |
4082 | + tcg_gen_helper_1_1(do_dmfc0_tchalt, cpu_T[0], cpu_T[0]); | |
4020 | 4083 | rn = "TCHalt"; |
4021 | 4084 | break; |
4022 | 4085 | case 5: |
4023 | 4086 | check_insn(env, ctx, ASE_MT); |
4024 | - tcg_gen_helper_0_0(do_dmfc0_tccontext); | |
4087 | + tcg_gen_helper_1_1(do_dmfc0_tccontext, cpu_T[0], cpu_T[0]); | |
4025 | 4088 | rn = "TCContext"; |
4026 | 4089 | break; |
4027 | 4090 | case 6: |
4028 | 4091 | check_insn(env, ctx, ASE_MT); |
4029 | - tcg_gen_helper_0_0(do_dmfc0_tcschedule); | |
4092 | + tcg_gen_helper_1_1(do_dmfc0_tcschedule, cpu_T[0], cpu_T[0]); | |
4030 | 4093 | rn = "TCSchedule"; |
4031 | 4094 | break; |
4032 | 4095 | case 7: |
4033 | 4096 | check_insn(env, ctx, ASE_MT); |
4034 | - tcg_gen_helper_0_0(do_dmfc0_tcschefback); | |
4097 | + tcg_gen_helper_1_1(do_dmfc0_tcschefback, cpu_T[0], cpu_T[0]); | |
4035 | 4098 | rn = "TCScheFBack"; |
4036 | 4099 | break; |
4037 | 4100 | default: |
... | ... | @@ -4055,7 +4118,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4055 | 4118 | rn = "Context"; |
4056 | 4119 | break; |
4057 | 4120 | case 1: |
4058 | -// tcg_gen_helper_0_0(do_dmfc0_contextconfig); /* SmartMIPS ASE */ | |
4121 | +// tcg_gen_helper_1_1(do_dmfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */ | |
4059 | 4122 | rn = "ContextConfig"; |
4060 | 4123 | // break; |
4061 | 4124 | default: |
... | ... | @@ -4136,7 +4199,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4136 | 4199 | case 9: |
4137 | 4200 | switch (sel) { |
4138 | 4201 | case 0: |
4139 | - tcg_gen_helper_0_0(do_mfc0_count); | |
4202 | + tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]); | |
4140 | 4203 | rn = "Count"; |
4141 | 4204 | break; |
4142 | 4205 | /* 6,7 are implementation dependent */ |
... | ... | @@ -4259,7 +4322,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4259 | 4322 | case 17: |
4260 | 4323 | switch (sel) { |
4261 | 4324 | case 0: |
4262 | - tcg_gen_helper_0_0(do_dmfc0_lladdr); | |
4325 | + tcg_gen_helper_1_1(do_dmfc0_lladdr, cpu_T[0], cpu_T[0]); | |
4263 | 4326 | rn = "LLAddr"; |
4264 | 4327 | break; |
4265 | 4328 | default: |
... | ... | @@ -4269,7 +4332,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4269 | 4332 | case 18: |
4270 | 4333 | switch (sel) { |
4271 | 4334 | case 0 ... 7: |
4272 | - tcg_gen_helper_0_1i(do_dmfc0_watchlo, sel); | |
4335 | + tcg_gen_helper_1_1i(do_dmfc0_watchlo, cpu_T[0], cpu_T[0], sel); | |
4273 | 4336 | rn = "WatchLo"; |
4274 | 4337 | break; |
4275 | 4338 | default: |
... | ... | @@ -4279,7 +4342,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4279 | 4342 | case 19: |
4280 | 4343 | switch (sel) { |
4281 | 4344 | case 0 ... 7: |
4282 | - tcg_gen_helper_0_1i(do_mfc0_watchhi, sel); | |
4345 | + tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel); | |
4283 | 4346 | rn = "WatchHi"; |
4284 | 4347 | break; |
4285 | 4348 | default: |
... | ... | @@ -4315,23 +4378,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4315 | 4378 | case 23: |
4316 | 4379 | switch (sel) { |
4317 | 4380 | case 0: |
4318 | - tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */ | |
4381 | + tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */ | |
4319 | 4382 | rn = "Debug"; |
4320 | 4383 | break; |
4321 | 4384 | case 1: |
4322 | -// tcg_gen_helper_0_0(do_dmfc0_tracecontrol); /* PDtrace support */ | |
4385 | +// tcg_gen_helper_1_1(do_dmfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
4323 | 4386 | rn = "TraceControl"; |
4324 | 4387 | // break; |
4325 | 4388 | case 2: |
4326 | -// tcg_gen_helper_0_0(do_dmfc0_tracecontrol2); /* PDtrace support */ | |
4389 | +// tcg_gen_helper_1_1(do_dmfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
4327 | 4390 | rn = "TraceControl2"; |
4328 | 4391 | // break; |
4329 | 4392 | case 3: |
4330 | -// tcg_gen_helper_0_0(do_dmfc0_usertracedata); /* PDtrace support */ | |
4393 | +// tcg_gen_helper_1_1(do_dmfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
4331 | 4394 | rn = "UserTraceData"; |
4332 | 4395 | // break; |
4333 | 4396 | case 4: |
4334 | -// tcg_gen_helper_0_0(do_dmfc0_debug); /* PDtrace support */ | |
4397 | +// tcg_gen_helper_1_1(do_dmfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */ | |
4335 | 4398 | rn = "TraceBPC"; |
4336 | 4399 | // break; |
4337 | 4400 | default: |
... | ... | @@ -4356,31 +4419,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4356 | 4419 | rn = "Performance0"; |
4357 | 4420 | break; |
4358 | 4421 | case 1: |
4359 | -// tcg_gen_helper_0_0(do_dmfc0_performance1); | |
4422 | +// tcg_gen_helper_1_1(do_dmfc0_performance1, cpu_T[0], cpu_T[0]); | |
4360 | 4423 | rn = "Performance1"; |
4361 | 4424 | // break; |
4362 | 4425 | case 2: |
4363 | -// tcg_gen_helper_0_0(do_dmfc0_performance2); | |
4426 | +// tcg_gen_helper_1_1(do_dmfc0_performance2, cpu_T[0], cpu_T[0]); | |
4364 | 4427 | rn = "Performance2"; |
4365 | 4428 | // break; |
4366 | 4429 | case 3: |
4367 | -// tcg_gen_helper_0_0(do_dmfc0_performance3); | |
4430 | +// tcg_gen_helper_1_1(do_dmfc0_performance3, cpu_T[0], cpu_T[0]); | |
4368 | 4431 | rn = "Performance3"; |
4369 | 4432 | // break; |
4370 | 4433 | case 4: |
4371 | -// tcg_gen_helper_0_0(do_dmfc0_performance4); | |
4434 | +// tcg_gen_helper_1_1(do_dmfc0_performance4, cpu_T[0], cpu_T[0]); | |
4372 | 4435 | rn = "Performance4"; |
4373 | 4436 | // break; |
4374 | 4437 | case 5: |
4375 | -// tcg_gen_helper_0_0(do_dmfc0_performance5); | |
4438 | +// tcg_gen_helper_1_1(do_dmfc0_performance5, cpu_T[0], cpu_T[0]); | |
4376 | 4439 | rn = "Performance5"; |
4377 | 4440 | // break; |
4378 | 4441 | case 6: |
4379 | -// tcg_gen_helper_0_0(do_dmfc0_performance6); | |
4442 | +// tcg_gen_helper_1_1(do_dmfc0_performance6, cpu_T[0], cpu_T[0]); | |
4380 | 4443 | rn = "Performance6"; |
4381 | 4444 | // break; |
4382 | 4445 | case 7: |
4383 | -// tcg_gen_helper_0_0(do_dmfc0_performance7); | |
4446 | +// tcg_gen_helper_1_1(do_dmfc0_performance7, cpu_T[0], cpu_T[0]); | |
4384 | 4447 | rn = "Performance7"; |
4385 | 4448 | // break; |
4386 | 4449 | default: |
... | ... | @@ -4493,12 +4556,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4493 | 4556 | case 0: |
4494 | 4557 | switch (sel) { |
4495 | 4558 | case 0: |
4496 | - tcg_gen_helper_0_0(do_mtc0_index); | |
4559 | + tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]); | |
4497 | 4560 | rn = "Index"; |
4498 | 4561 | break; |
4499 | 4562 | case 1: |
4500 | 4563 | check_insn(env, ctx, ASE_MT); |
4501 | - tcg_gen_helper_0_0(do_mtc0_mvpcontrol); | |
4564 | + tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]); | |
4502 | 4565 | rn = "MVPControl"; |
4503 | 4566 | break; |
4504 | 4567 | case 2: |
... | ... | @@ -4523,22 +4586,22 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4523 | 4586 | break; |
4524 | 4587 | case 1: |
4525 | 4588 | check_insn(env, ctx, ASE_MT); |
4526 | - tcg_gen_helper_0_0(do_mtc0_vpecontrol); | |
4589 | + tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]); | |
4527 | 4590 | rn = "VPEControl"; |
4528 | 4591 | break; |
4529 | 4592 | case 2: |
4530 | 4593 | check_insn(env, ctx, ASE_MT); |
4531 | - tcg_gen_helper_0_0(do_mtc0_vpeconf0); | |
4594 | + tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]); | |
4532 | 4595 | rn = "VPEConf0"; |
4533 | 4596 | break; |
4534 | 4597 | case 3: |
4535 | 4598 | check_insn(env, ctx, ASE_MT); |
4536 | - tcg_gen_helper_0_0(do_mtc0_vpeconf1); | |
4599 | + tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]); | |
4537 | 4600 | rn = "VPEConf1"; |
4538 | 4601 | break; |
4539 | 4602 | case 4: |
4540 | 4603 | check_insn(env, ctx, ASE_MT); |
4541 | - tcg_gen_helper_0_0(do_mtc0_yqmask); | |
4604 | + tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]); | |
4542 | 4605 | rn = "YQMask"; |
4543 | 4606 | break; |
4544 | 4607 | case 5: |
... | ... | @@ -4553,7 +4616,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4553 | 4616 | break; |
4554 | 4617 | case 7: |
4555 | 4618 | check_insn(env, ctx, ASE_MT); |
4556 | - tcg_gen_helper_0_0(do_mtc0_vpeopt); | |
4619 | + tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]); | |
4557 | 4620 | rn = "VPEOpt"; |
4558 | 4621 | break; |
4559 | 4622 | default: |
... | ... | @@ -4563,42 +4626,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4563 | 4626 | case 2: |
4564 | 4627 | switch (sel) { |
4565 | 4628 | case 0: |
4566 | - tcg_gen_helper_0_0(do_mtc0_entrylo0); | |
4629 | + tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]); | |
4567 | 4630 | rn = "EntryLo0"; |
4568 | 4631 | break; |
4569 | 4632 | case 1: |
4570 | 4633 | check_insn(env, ctx, ASE_MT); |
4571 | - tcg_gen_helper_0_0(do_mtc0_tcstatus); | |
4634 | + tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]); | |
4572 | 4635 | rn = "TCStatus"; |
4573 | 4636 | break; |
4574 | 4637 | case 2: |
4575 | 4638 | check_insn(env, ctx, ASE_MT); |
4576 | - tcg_gen_helper_0_0(do_mtc0_tcbind); | |
4639 | + tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]); | |
4577 | 4640 | rn = "TCBind"; |
4578 | 4641 | break; |
4579 | 4642 | case 3: |
4580 | 4643 | check_insn(env, ctx, ASE_MT); |
4581 | - tcg_gen_helper_0_0(do_mtc0_tcrestart); | |
4644 | + tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]); | |
4582 | 4645 | rn = "TCRestart"; |
4583 | 4646 | break; |
4584 | 4647 | case 4: |
4585 | 4648 | check_insn(env, ctx, ASE_MT); |
4586 | - tcg_gen_helper_0_0(do_mtc0_tchalt); | |
4649 | + tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]); | |
4587 | 4650 | rn = "TCHalt"; |
4588 | 4651 | break; |
4589 | 4652 | case 5: |
4590 | 4653 | check_insn(env, ctx, ASE_MT); |
4591 | - tcg_gen_helper_0_0(do_mtc0_tccontext); | |
4654 | + tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]); | |
4592 | 4655 | rn = "TCContext"; |
4593 | 4656 | break; |
4594 | 4657 | case 6: |
4595 | 4658 | check_insn(env, ctx, ASE_MT); |
4596 | - tcg_gen_helper_0_0(do_mtc0_tcschedule); | |
4659 | + tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]); | |
4597 | 4660 | rn = "TCSchedule"; |
4598 | 4661 | break; |
4599 | 4662 | case 7: |
4600 | 4663 | check_insn(env, ctx, ASE_MT); |
4601 | - tcg_gen_helper_0_0(do_mtc0_tcschefback); | |
4664 | + tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]); | |
4602 | 4665 | rn = "TCScheFBack"; |
4603 | 4666 | break; |
4604 | 4667 | default: |
... | ... | @@ -4608,7 +4671,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4608 | 4671 | case 3: |
4609 | 4672 | switch (sel) { |
4610 | 4673 | case 0: |
4611 | - tcg_gen_helper_0_0(do_mtc0_entrylo1); | |
4674 | + tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]); | |
4612 | 4675 | rn = "EntryLo1"; |
4613 | 4676 | break; |
4614 | 4677 | default: |
... | ... | @@ -4618,11 +4681,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4618 | 4681 | case 4: |
4619 | 4682 | switch (sel) { |
4620 | 4683 | case 0: |
4621 | - tcg_gen_helper_0_0(do_mtc0_context); | |
4684 | + tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]); | |
4622 | 4685 | rn = "Context"; |
4623 | 4686 | break; |
4624 | 4687 | case 1: |
4625 | -// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */ | |
4688 | +// tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */ | |
4626 | 4689 | rn = "ContextConfig"; |
4627 | 4690 | // break; |
4628 | 4691 | default: |
... | ... | @@ -4632,12 +4695,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4632 | 4695 | case 5: |
4633 | 4696 | switch (sel) { |
4634 | 4697 | case 0: |
4635 | - tcg_gen_helper_0_0(do_mtc0_pagemask); | |
4698 | + tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]); | |
4636 | 4699 | rn = "PageMask"; |
4637 | 4700 | break; |
4638 | 4701 | case 1: |
4639 | 4702 | check_insn(env, ctx, ISA_MIPS32R2); |
4640 | - tcg_gen_helper_0_0(do_mtc0_pagegrain); | |
4703 | + tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]); | |
4641 | 4704 | rn = "PageGrain"; |
4642 | 4705 | break; |
4643 | 4706 | default: |
... | ... | @@ -4647,32 +4710,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4647 | 4710 | case 6: |
4648 | 4711 | switch (sel) { |
4649 | 4712 | case 0: |
4650 | - tcg_gen_helper_0_0(do_mtc0_wired); | |
4713 | + tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]); | |
4651 | 4714 | rn = "Wired"; |
4652 | 4715 | break; |
4653 | 4716 | case 1: |
4654 | 4717 | check_insn(env, ctx, ISA_MIPS32R2); |
4655 | - tcg_gen_helper_0_0(do_mtc0_srsconf0); | |
4718 | + tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]); | |
4656 | 4719 | rn = "SRSConf0"; |
4657 | 4720 | break; |
4658 | 4721 | case 2: |
4659 | 4722 | check_insn(env, ctx, ISA_MIPS32R2); |
4660 | - tcg_gen_helper_0_0(do_mtc0_srsconf1); | |
4723 | + tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]); | |
4661 | 4724 | rn = "SRSConf1"; |
4662 | 4725 | break; |
4663 | 4726 | case 3: |
4664 | 4727 | check_insn(env, ctx, ISA_MIPS32R2); |
4665 | - tcg_gen_helper_0_0(do_mtc0_srsconf2); | |
4728 | + tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]); | |
4666 | 4729 | rn = "SRSConf2"; |
4667 | 4730 | break; |
4668 | 4731 | case 4: |
4669 | 4732 | check_insn(env, ctx, ISA_MIPS32R2); |
4670 | - tcg_gen_helper_0_0(do_mtc0_srsconf3); | |
4733 | + tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]); | |
4671 | 4734 | rn = "SRSConf3"; |
4672 | 4735 | break; |
4673 | 4736 | case 5: |
4674 | 4737 | check_insn(env, ctx, ISA_MIPS32R2); |
4675 | - tcg_gen_helper_0_0(do_mtc0_srsconf4); | |
4738 | + tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]); | |
4676 | 4739 | rn = "SRSConf4"; |
4677 | 4740 | break; |
4678 | 4741 | default: |
... | ... | @@ -4683,7 +4746,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4683 | 4746 | switch (sel) { |
4684 | 4747 | case 0: |
4685 | 4748 | check_insn(env, ctx, ISA_MIPS32R2); |
4686 | - tcg_gen_helper_0_0(do_mtc0_hwrena); | |
4749 | + tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]); | |
4687 | 4750 | rn = "HWREna"; |
4688 | 4751 | break; |
4689 | 4752 | default: |
... | ... | @@ -4697,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4697 | 4760 | case 9: |
4698 | 4761 | switch (sel) { |
4699 | 4762 | case 0: |
4700 | - tcg_gen_helper_0_0(do_mtc0_count); | |
4763 | + tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]); | |
4701 | 4764 | rn = "Count"; |
4702 | 4765 | break; |
4703 | 4766 | /* 6,7 are implementation dependent */ |
... | ... | @@ -4710,7 +4773,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4710 | 4773 | case 10: |
4711 | 4774 | switch (sel) { |
4712 | 4775 | case 0: |
4713 | - tcg_gen_helper_0_0(do_mtc0_entryhi); | |
4776 | + tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]); | |
4714 | 4777 | rn = "EntryHi"; |
4715 | 4778 | break; |
4716 | 4779 | default: |
... | ... | @@ -4720,7 +4783,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4720 | 4783 | case 11: |
4721 | 4784 | switch (sel) { |
4722 | 4785 | case 0: |
4723 | - tcg_gen_helper_0_0(do_mtc0_compare); | |
4786 | + tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]); | |
4724 | 4787 | rn = "Compare"; |
4725 | 4788 | break; |
4726 | 4789 | /* 6,7 are implementation dependent */ |
... | ... | @@ -4733,7 +4796,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4733 | 4796 | case 12: |
4734 | 4797 | switch (sel) { |
4735 | 4798 | case 0: |
4736 | - tcg_gen_helper_0_0(do_mtc0_status); | |
4799 | + tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]); | |
4737 | 4800 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
4738 | 4801 | gen_save_pc(ctx->pc + 4); |
4739 | 4802 | ctx->bstate = BS_EXCP; |
... | ... | @@ -4741,14 +4804,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4741 | 4804 | break; |
4742 | 4805 | case 1: |
4743 | 4806 | check_insn(env, ctx, ISA_MIPS32R2); |
4744 | - tcg_gen_helper_0_0(do_mtc0_intctl); | |
4807 | + tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]); | |
4745 | 4808 | /* Stop translation as we may have switched the execution mode */ |
4746 | 4809 | ctx->bstate = BS_STOP; |
4747 | 4810 | rn = "IntCtl"; |
4748 | 4811 | break; |
4749 | 4812 | case 2: |
4750 | 4813 | check_insn(env, ctx, ISA_MIPS32R2); |
4751 | - tcg_gen_helper_0_0(do_mtc0_srsctl); | |
4814 | + tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]); | |
4752 | 4815 | /* Stop translation as we may have switched the execution mode */ |
4753 | 4816 | ctx->bstate = BS_STOP; |
4754 | 4817 | rn = "SRSCtl"; |
... | ... | @@ -4767,7 +4830,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4767 | 4830 | case 13: |
4768 | 4831 | switch (sel) { |
4769 | 4832 | case 0: |
4770 | - tcg_gen_helper_0_0(do_mtc0_cause); | |
4833 | + tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]); | |
4771 | 4834 | rn = "Cause"; |
4772 | 4835 | break; |
4773 | 4836 | default: |
... | ... | @@ -4794,7 +4857,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4794 | 4857 | break; |
4795 | 4858 | case 1: |
4796 | 4859 | check_insn(env, ctx, ISA_MIPS32R2); |
4797 | - tcg_gen_helper_0_0(do_mtc0_ebase); | |
4860 | + tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]); | |
4798 | 4861 | rn = "EBase"; |
4799 | 4862 | break; |
4800 | 4863 | default: |
... | ... | @@ -4804,7 +4867,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4804 | 4867 | case 16: |
4805 | 4868 | switch (sel) { |
4806 | 4869 | case 0: |
4807 | - tcg_gen_helper_0_0(do_mtc0_config0); | |
4870 | + tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]); | |
4808 | 4871 | rn = "Config"; |
4809 | 4872 | /* Stop translation as we may have switched the execution mode */ |
4810 | 4873 | ctx->bstate = BS_STOP; |
... | ... | @@ -4814,7 +4877,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4814 | 4877 | rn = "Config1"; |
4815 | 4878 | break; |
4816 | 4879 | case 2: |
4817 | - tcg_gen_helper_0_0(do_mtc0_config2); | |
4880 | + tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]); | |
4818 | 4881 | rn = "Config2"; |
4819 | 4882 | /* Stop translation as we may have switched the execution mode */ |
4820 | 4883 | ctx->bstate = BS_STOP; |
... | ... | @@ -4842,7 +4905,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4842 | 4905 | case 18: |
4843 | 4906 | switch (sel) { |
4844 | 4907 | case 0 ... 7: |
4845 | - tcg_gen_helper_0_1i(do_mtc0_watchlo, sel); | |
4908 | + tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel); | |
4846 | 4909 | rn = "WatchLo"; |
4847 | 4910 | break; |
4848 | 4911 | default: |
... | ... | @@ -4852,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4852 | 4915 | case 19: |
4853 | 4916 | switch (sel) { |
4854 | 4917 | case 0 ... 7: |
4855 | - tcg_gen_helper_0_1i(do_mtc0_watchhi, sel); | |
4918 | + tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel); | |
4856 | 4919 | rn = "WatchHi"; |
4857 | 4920 | break; |
4858 | 4921 | default: |
... | ... | @@ -4863,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4863 | 4926 | switch (sel) { |
4864 | 4927 | case 0: |
4865 | 4928 | check_insn(env, ctx, ISA_MIPS3); |
4866 | - tcg_gen_helper_0_0(do_mtc0_xcontext); | |
4929 | + tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]); | |
4867 | 4930 | rn = "XContext"; |
4868 | 4931 | break; |
4869 | 4932 | default: |
... | ... | @@ -4874,7 +4937,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4874 | 4937 | /* Officially reserved, but sel 0 is used for R1x000 framemask */ |
4875 | 4938 | switch (sel) { |
4876 | 4939 | case 0: |
4877 | - tcg_gen_helper_0_0(do_mtc0_framemask); | |
4940 | + tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]); | |
4878 | 4941 | rn = "Framemask"; |
4879 | 4942 | break; |
4880 | 4943 | default: |
... | ... | @@ -4888,32 +4951,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4888 | 4951 | case 23: |
4889 | 4952 | switch (sel) { |
4890 | 4953 | case 0: |
4891 | - tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */ | |
4954 | + tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */ | |
4892 | 4955 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
4893 | 4956 | gen_save_pc(ctx->pc + 4); |
4894 | 4957 | ctx->bstate = BS_EXCP; |
4895 | 4958 | rn = "Debug"; |
4896 | 4959 | break; |
4897 | 4960 | case 1: |
4898 | -// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */ | |
4961 | +// tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */ | |
4899 | 4962 | /* Stop translation as we may have switched the execution mode */ |
4900 | 4963 | ctx->bstate = BS_STOP; |
4901 | 4964 | rn = "TraceControl"; |
4902 | 4965 | // break; |
4903 | 4966 | case 2: |
4904 | -// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */ | |
4967 | +// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */ | |
4905 | 4968 | /* Stop translation as we may have switched the execution mode */ |
4906 | 4969 | ctx->bstate = BS_STOP; |
4907 | 4970 | rn = "TraceControl2"; |
4908 | 4971 | // break; |
4909 | 4972 | case 3: |
4910 | -// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */ | |
4973 | +// tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */ | |
4911 | 4974 | /* Stop translation as we may have switched the execution mode */ |
4912 | 4975 | ctx->bstate = BS_STOP; |
4913 | 4976 | rn = "UserTraceData"; |
4914 | 4977 | // break; |
4915 | 4978 | case 4: |
4916 | -// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */ | |
4979 | +// tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */ | |
4917 | 4980 | /* Stop translation as we may have switched the execution mode */ |
4918 | 4981 | ctx->bstate = BS_STOP; |
4919 | 4982 | rn = "TraceBPC"; |
... | ... | @@ -4936,35 +4999,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4936 | 4999 | case 25: |
4937 | 5000 | switch (sel) { |
4938 | 5001 | case 0: |
4939 | - tcg_gen_helper_0_0(do_mtc0_performance0); | |
5002 | + tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]); | |
4940 | 5003 | rn = "Performance0"; |
4941 | 5004 | break; |
4942 | 5005 | case 1: |
4943 | -// tcg_gen_helper_0_0(do_mtc0_performance1); | |
5006 | +// tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]); | |
4944 | 5007 | rn = "Performance1"; |
4945 | 5008 | // break; |
4946 | 5009 | case 2: |
4947 | -// tcg_gen_helper_0_0(do_mtc0_performance2); | |
5010 | +// tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]); | |
4948 | 5011 | rn = "Performance2"; |
4949 | 5012 | // break; |
4950 | 5013 | case 3: |
4951 | -// tcg_gen_helper_0_0(do_mtc0_performance3); | |
5014 | +// tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]); | |
4952 | 5015 | rn = "Performance3"; |
4953 | 5016 | // break; |
4954 | 5017 | case 4: |
4955 | -// tcg_gen_helper_0_0(do_mtc0_performance4); | |
5018 | +// tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]); | |
4956 | 5019 | rn = "Performance4"; |
4957 | 5020 | // break; |
4958 | 5021 | case 5: |
4959 | -// tcg_gen_helper_0_0(do_mtc0_performance5); | |
5022 | +// tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]); | |
4960 | 5023 | rn = "Performance5"; |
4961 | 5024 | // break; |
4962 | 5025 | case 6: |
4963 | -// tcg_gen_helper_0_0(do_mtc0_performance6); | |
5026 | +// tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]); | |
4964 | 5027 | rn = "Performance6"; |
4965 | 5028 | // break; |
4966 | 5029 | case 7: |
4967 | -// tcg_gen_helper_0_0(do_mtc0_performance7); | |
5030 | +// tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]); | |
4968 | 5031 | rn = "Performance7"; |
4969 | 5032 | // break; |
4970 | 5033 | default: |
... | ... | @@ -4991,14 +5054,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
4991 | 5054 | case 2: |
4992 | 5055 | case 4: |
4993 | 5056 | case 6: |
4994 | - tcg_gen_helper_0_0(do_mtc0_taglo); | |
5057 | + tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]); | |
4995 | 5058 | rn = "TagLo"; |
4996 | 5059 | break; |
4997 | 5060 | case 1: |
4998 | 5061 | case 3: |
4999 | 5062 | case 5: |
5000 | 5063 | case 7: |
5001 | - tcg_gen_helper_0_0(do_mtc0_datalo); | |
5064 | + tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]); | |
5002 | 5065 | rn = "DataLo"; |
5003 | 5066 | break; |
5004 | 5067 | default: |
... | ... | @@ -5011,14 +5074,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
5011 | 5074 | case 2: |
5012 | 5075 | case 4: |
5013 | 5076 | case 6: |
5014 | - tcg_gen_helper_0_0(do_mtc0_taghi); | |
5077 | + tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]); | |
5015 | 5078 | rn = "TagHi"; |
5016 | 5079 | break; |
5017 | 5080 | case 1: |
5018 | 5081 | case 3: |
5019 | 5082 | case 5: |
5020 | 5083 | case 7: |
5021 | - tcg_gen_helper_0_0(do_mtc0_datahi); | |
5084 | + tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]); | |
5022 | 5085 | rn = "DataHi"; |
5023 | 5086 | break; |
5024 | 5087 | default: |
... | ... | @@ -5088,25 +5151,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
5088 | 5151 | case 2: |
5089 | 5152 | switch (sel) { |
5090 | 5153 | case 1: |
5091 | - tcg_gen_helper_0_0(do_mftc0_tcstatus); | |
5154 | + tcg_gen_helper_1_1(do_mftc0_tcstatus, cpu_T[0], cpu_T[0]); | |
5092 | 5155 | break; |
5093 | 5156 | case 2: |
5094 | - tcg_gen_helper_0_0(do_mftc0_tcbind); | |
5157 | + tcg_gen_helper_1_1(do_mftc0_tcbind, cpu_T[0], cpu_T[0]); | |
5095 | 5158 | break; |
5096 | 5159 | case 3: |
5097 | - tcg_gen_helper_0_0(do_mftc0_tcrestart); | |
5160 | + tcg_gen_helper_1_1(do_mftc0_tcrestart, cpu_T[0], cpu_T[0]); | |
5098 | 5161 | break; |
5099 | 5162 | case 4: |
5100 | - tcg_gen_helper_0_0(do_mftc0_tchalt); | |
5163 | + tcg_gen_helper_1_1(do_mftc0_tchalt, cpu_T[0], cpu_T[0]); | |
5101 | 5164 | break; |
5102 | 5165 | case 5: |
5103 | - tcg_gen_helper_0_0(do_mftc0_tccontext); | |
5166 | + tcg_gen_helper_1_1(do_mftc0_tccontext, cpu_T[0], cpu_T[0]); | |
5104 | 5167 | break; |
5105 | 5168 | case 6: |
5106 | - tcg_gen_helper_0_0(do_mftc0_tcschedule); | |
5169 | + tcg_gen_helper_1_1(do_mftc0_tcschedule, cpu_T[0], cpu_T[0]); | |
5107 | 5170 | break; |
5108 | 5171 | case 7: |
5109 | - tcg_gen_helper_0_0(do_mftc0_tcschefback); | |
5172 | + tcg_gen_helper_1_1(do_mftc0_tcschefback, cpu_T[0], cpu_T[0]); | |
5110 | 5173 | break; |
5111 | 5174 | default: |
5112 | 5175 | gen_mfc0(env, ctx, rt, sel); |
... | ... | @@ -5116,7 +5179,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
5116 | 5179 | case 10: |
5117 | 5180 | switch (sel) { |
5118 | 5181 | case 0: |
5119 | - tcg_gen_helper_0_0(do_mftc0_entryhi); | |
5182 | + tcg_gen_helper_1_1(do_mftc0_entryhi, cpu_T[0], cpu_T[0]); | |
5120 | 5183 | break; |
5121 | 5184 | default: |
5122 | 5185 | gen_mfc0(env, ctx, rt, sel); |
... | ... | @@ -5125,7 +5188,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
5125 | 5188 | case 12: |
5126 | 5189 | switch (sel) { |
5127 | 5190 | case 0: |
5128 | - tcg_gen_helper_0_0(do_mftc0_status); | |
5191 | + tcg_gen_helper_1_1(do_mftc0_status, cpu_T[0], cpu_T[0]); | |
5129 | 5192 | break; |
5130 | 5193 | default: |
5131 | 5194 | gen_mfc0(env, ctx, rt, sel); |
... | ... | @@ -5134,7 +5197,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
5134 | 5197 | case 23: |
5135 | 5198 | switch (sel) { |
5136 | 5199 | case 0: |
5137 | - tcg_gen_helper_0_0(do_mftc0_debug); | |
5200 | + tcg_gen_helper_1_1(do_mftc0_debug, cpu_T[0], cpu_T[0]); | |
5138 | 5201 | break; |
5139 | 5202 | default: |
5140 | 5203 | gen_mfc0(env, ctx, rt, sel); |
... | ... | @@ -5147,49 +5210,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
5147 | 5210 | } else switch (sel) { |
5148 | 5211 | /* GPR registers. */ |
5149 | 5212 | case 0: |
5150 | - tcg_gen_helper_0_1i(do_mftgpr, rt); | |
5213 | + tcg_gen_helper_1_1i(do_mftgpr, cpu_T[0], cpu_T[0], rt); | |
5151 | 5214 | break; |
5152 | 5215 | /* Auxiliary CPU registers */ |
5153 | 5216 | case 1: |
5154 | 5217 | switch (rt) { |
5155 | 5218 | case 0: |
5156 | - tcg_gen_helper_0_1i(do_mftlo, 0); | |
5219 | + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 0); | |
5157 | 5220 | break; |
5158 | 5221 | case 1: |
5159 | - tcg_gen_helper_0_1i(do_mfthi, 0); | |
5222 | + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 0); | |
5160 | 5223 | break; |
5161 | 5224 | case 2: |
5162 | - tcg_gen_helper_0_1i(do_mftacx, 0); | |
5225 | + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 0); | |
5163 | 5226 | break; |
5164 | 5227 | case 4: |
5165 | - tcg_gen_helper_0_1i(do_mftlo, 1); | |
5228 | + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 1); | |
5166 | 5229 | break; |
5167 | 5230 | case 5: |
5168 | - tcg_gen_helper_0_1i(do_mfthi, 1); | |
5231 | + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 1); | |
5169 | 5232 | break; |
5170 | 5233 | case 6: |
5171 | - tcg_gen_helper_0_1i(do_mftacx, 1); | |
5234 | + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 1); | |
5172 | 5235 | break; |
5173 | 5236 | case 8: |
5174 | - tcg_gen_helper_0_1i(do_mftlo, 2); | |
5237 | + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 2); | |
5175 | 5238 | break; |
5176 | 5239 | case 9: |
5177 | - tcg_gen_helper_0_1i(do_mfthi, 2); | |
5240 | + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 2); | |
5178 | 5241 | break; |
5179 | 5242 | case 10: |
5180 | - tcg_gen_helper_0_1i(do_mftacx, 2); | |
5243 | + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 2); | |
5181 | 5244 | break; |
5182 | 5245 | case 12: |
5183 | - tcg_gen_helper_0_1i(do_mftlo, 3); | |
5246 | + tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 3); | |
5184 | 5247 | break; |
5185 | 5248 | case 13: |
5186 | - tcg_gen_helper_0_1i(do_mfthi, 3); | |
5249 | + tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 3); | |
5187 | 5250 | break; |
5188 | 5251 | case 14: |
5189 | - tcg_gen_helper_0_1i(do_mftacx, 3); | |
5252 | + tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 3); | |
5190 | 5253 | break; |
5191 | 5254 | case 16: |
5192 | - tcg_gen_helper_0_0(do_mftdsp); | |
5255 | + tcg_gen_helper_1_1(do_mftdsp, cpu_T[0], cpu_T[0]); | |
5193 | 5256 | break; |
5194 | 5257 | default: |
5195 | 5258 | goto die; |
... | ... | @@ -5208,7 +5271,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
5208 | 5271 | break; |
5209 | 5272 | case 3: |
5210 | 5273 | /* XXX: For now we support only a single FPU context. */ |
5211 | - tcg_gen_helper_0_1i(do_cfc1, rt); | |
5274 | + tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], rt); | |
5212 | 5275 | break; |
5213 | 5276 | /* COP2: Not implemented. */ |
5214 | 5277 | case 4: |
... | ... | @@ -5252,25 +5315,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, |
5252 | 5315 | case 2: |
5253 | 5316 | switch (sel) { |
5254 | 5317 | case 1: |
5255 | - tcg_gen_helper_0_0(do_mttc0_tcstatus); | |
5318 | + tcg_gen_helper_0_1(do_mttc0_tcstatus, cpu_T[0]); | |
5256 | 5319 | break; |
5257 | 5320 | case 2: |
5258 | - tcg_gen_helper_0_0(do_mttc0_tcbind); | |
5321 | + tcg_gen_helper_0_1(do_mttc0_tcbind, cpu_T[0]); | |
5259 | 5322 | break; |
5260 | 5323 | case 3: |
5261 | - tcg_gen_helper_0_0(do_mttc0_tcrestart); | |
5324 | + tcg_gen_helper_0_1(do_mttc0_tcrestart, cpu_T[0]); | |
5262 | 5325 | break; |
5263 | 5326 | case 4: |
5264 | - tcg_gen_helper_0_0(do_mttc0_tchalt); | |
5327 | + tcg_gen_helper_0_1(do_mttc0_tchalt, cpu_T[0]); | |
5265 | 5328 | break; |
5266 | 5329 | case 5: |
5267 | - tcg_gen_helper_0_0(do_mttc0_tccontext); | |
5330 | + tcg_gen_helper_0_1(do_mttc0_tccontext, cpu_T[0]); | |
5268 | 5331 | break; |
5269 | 5332 | case 6: |
5270 | - tcg_gen_helper_0_0(do_mttc0_tcschedule); | |
5333 | + tcg_gen_helper_0_1(do_mttc0_tcschedule, cpu_T[0]); | |
5271 | 5334 | break; |
5272 | 5335 | case 7: |
5273 | - tcg_gen_helper_0_0(do_mttc0_tcschefback); | |
5336 | + tcg_gen_helper_0_1(do_mttc0_tcschefback, cpu_T[0]); | |
5274 | 5337 | break; |
5275 | 5338 | default: |
5276 | 5339 | gen_mtc0(env, ctx, rd, sel); |
... | ... | @@ -5280,7 +5343,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, |
5280 | 5343 | case 10: |
5281 | 5344 | switch (sel) { |
5282 | 5345 | case 0: |
5283 | - tcg_gen_helper_0_0(do_mttc0_entryhi); | |
5346 | + tcg_gen_helper_0_1(do_mttc0_entryhi, cpu_T[0]); | |
5284 | 5347 | break; |
5285 | 5348 | default: |
5286 | 5349 | gen_mtc0(env, ctx, rd, sel); |
... | ... | @@ -5289,7 +5352,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, |
5289 | 5352 | case 12: |
5290 | 5353 | switch (sel) { |
5291 | 5354 | case 0: |
5292 | - tcg_gen_helper_0_0(do_mttc0_status); | |
5355 | + tcg_gen_helper_0_1(do_mttc0_status, cpu_T[0]); | |
5293 | 5356 | break; |
5294 | 5357 | default: |
5295 | 5358 | gen_mtc0(env, ctx, rd, sel); |
... | ... | @@ -5298,7 +5361,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, |
5298 | 5361 | case 23: |
5299 | 5362 | switch (sel) { |
5300 | 5363 | case 0: |
5301 | - tcg_gen_helper_0_0(do_mttc0_debug); | |
5364 | + tcg_gen_helper_0_1(do_mttc0_debug, cpu_T[0]); | |
5302 | 5365 | break; |
5303 | 5366 | default: |
5304 | 5367 | gen_mtc0(env, ctx, rd, sel); |
... | ... | @@ -5311,49 +5374,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, |
5311 | 5374 | } else switch (sel) { |
5312 | 5375 | /* GPR registers. */ |
5313 | 5376 | case 0: |
5314 | - tcg_gen_helper_0_1i(do_mttgpr, rd); | |
5377 | + tcg_gen_helper_0_1i(do_mttgpr, cpu_T[0], rd); | |
5315 | 5378 | break; |
5316 | 5379 | /* Auxiliary CPU registers */ |
5317 | 5380 | case 1: |
5318 | 5381 | switch (rd) { |
5319 | 5382 | case 0: |
5320 | - tcg_gen_helper_0_1i(do_mttlo, 0); | |
5383 | + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 0); | |
5321 | 5384 | break; |
5322 | 5385 | case 1: |
5323 | - tcg_gen_helper_0_1i(do_mtthi, 0); | |
5386 | + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 0); | |
5324 | 5387 | break; |
5325 | 5388 | case 2: |
5326 | - tcg_gen_helper_0_1i(do_mttacx, 0); | |
5389 | + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 0); | |
5327 | 5390 | break; |
5328 | 5391 | case 4: |
5329 | - tcg_gen_helper_0_1i(do_mttlo, 1); | |
5392 | + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 1); | |
5330 | 5393 | break; |
5331 | 5394 | case 5: |
5332 | - tcg_gen_helper_0_1i(do_mtthi, 1); | |
5395 | + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 1); | |
5333 | 5396 | break; |
5334 | 5397 | case 6: |
5335 | - tcg_gen_helper_0_1i(do_mttacx, 1); | |
5398 | + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 1); | |
5336 | 5399 | break; |
5337 | 5400 | case 8: |
5338 | - tcg_gen_helper_0_1i(do_mttlo, 2); | |
5401 | + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 2); | |
5339 | 5402 | break; |
5340 | 5403 | case 9: |
5341 | - tcg_gen_helper_0_1i(do_mtthi, 2); | |
5404 | + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 2); | |
5342 | 5405 | break; |
5343 | 5406 | case 10: |
5344 | - tcg_gen_helper_0_1i(do_mttacx, 2); | |
5407 | + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 2); | |
5345 | 5408 | break; |
5346 | 5409 | case 12: |
5347 | - tcg_gen_helper_0_1i(do_mttlo, 3); | |
5410 | + tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 3); | |
5348 | 5411 | break; |
5349 | 5412 | case 13: |
5350 | - tcg_gen_helper_0_1i(do_mtthi, 3); | |
5413 | + tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 3); | |
5351 | 5414 | break; |
5352 | 5415 | case 14: |
5353 | - tcg_gen_helper_0_1i(do_mttacx, 3); | |
5416 | + tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 3); | |
5354 | 5417 | break; |
5355 | 5418 | case 16: |
5356 | - tcg_gen_helper_0_0(do_mttdsp); | |
5419 | + tcg_gen_helper_0_1(do_mttdsp, cpu_T[0]); | |
5357 | 5420 | break; |
5358 | 5421 | default: |
5359 | 5422 | goto die; |
... | ... | @@ -5372,7 +5435,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, |
5372 | 5435 | break; |
5373 | 5436 | case 3: |
5374 | 5437 | /* XXX: For now we support only a single FPU context. */ |
5375 | - tcg_gen_helper_0_1i(do_ctc1, rd); | |
5438 | + tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], rd); | |
5376 | 5439 | break; |
5377 | 5440 | /* COP2: Not implemented. */ |
5378 | 5441 | case 4: |
... | ... | @@ -5484,7 +5547,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int |
5484 | 5547 | opn = "eret"; |
5485 | 5548 | check_insn(env, ctx, ISA_MIPS2); |
5486 | 5549 | save_cpu_state(ctx, 1); |
5487 | - tcg_gen_helper_0_0(do_eret); | |
5550 | + tcg_gen_helper_0_1(do_eret, cpu_T[0]); | |
5488 | 5551 | ctx->bstate = BS_EXCP; |
5489 | 5552 | break; |
5490 | 5553 | case OPC_DERET: |
... | ... | @@ -5495,7 +5558,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int |
5495 | 5558 | generate_exception(ctx, EXCP_RI); |
5496 | 5559 | } else { |
5497 | 5560 | save_cpu_state(ctx, 1); |
5498 | - tcg_gen_helper_0_0(do_deret); | |
5561 | + tcg_gen_helper_0_1(do_deret, cpu_T[0]); | |
5499 | 5562 | ctx->bstate = BS_EXCP; |
5500 | 5563 | } |
5501 | 5564 | break; |
... | ... | @@ -5734,13 +5797,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) |
5734 | 5797 | opn = "mtc1"; |
5735 | 5798 | break; |
5736 | 5799 | case OPC_CFC1: |
5737 | - tcg_gen_helper_0_1i(do_cfc1, fs); | |
5800 | + tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], fs); | |
5738 | 5801 | gen_store_gpr(cpu_T[0], rt); |
5739 | 5802 | opn = "cfc1"; |
5740 | 5803 | break; |
5741 | 5804 | case OPC_CTC1: |
5742 | 5805 | gen_load_gpr(cpu_T[0], rt); |
5743 | - tcg_gen_helper_0_1i(do_ctc1, fs); | |
5806 | + tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], fs); | |
5744 | 5807 | opn = "ctc1"; |
5745 | 5808 | break; |
5746 | 5809 | case OPC_DMFC1: |
... | ... | @@ -6745,7 +6808,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, |
6745 | 6808 | } else { |
6746 | 6809 | gen_load_gpr(cpu_T[0], base); |
6747 | 6810 | gen_load_gpr(cpu_T[1], index); |
6748 | - gen_op_addr_add(); | |
6811 | + gen_op_addr_add(cpu_T[0], cpu_T[1]); | |
6749 | 6812 | } |
6750 | 6813 | /* Don't do NOP if destination is zero: we must perform the actual |
6751 | 6814 | memory access. */ |
... | ... | @@ -7069,7 +7132,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7069 | 7132 | MIPS_INVAL("PMON / selsl"); |
7070 | 7133 | generate_exception(ctx, EXCP_RI); |
7071 | 7134 | #else |
7072 | - tcg_gen_helper_0_1i(do_pmon, sa); | |
7135 | + tcg_gen_helper_0_i(do_pmon, sa); | |
7073 | 7136 | #endif |
7074 | 7137 | break; |
7075 | 7138 | case OPC_SYSCALL: |
... | ... | @@ -7187,7 +7250,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7187 | 7250 | switch (op2) { |
7188 | 7251 | case OPC_WSBH: |
7189 | 7252 | gen_load_gpr(cpu_T[1], rt); |
7190 | - tcg_gen_helper_0_0(do_wsbh); | |
7253 | + tcg_gen_helper_1_2(do_wsbh, cpu_T[0], cpu_T[0], cpu_T[1]); | |
7191 | 7254 | break; |
7192 | 7255 | case OPC_SEB: |
7193 | 7256 | gen_load_gpr(cpu_T[1], rt); |
... | ... | @@ -7209,19 +7272,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7209 | 7272 | switch (rd) { |
7210 | 7273 | case 0: |
7211 | 7274 | save_cpu_state(ctx, 1); |
7212 | - tcg_gen_helper_0_0(do_rdhwr_cpunum); | |
7275 | + tcg_gen_helper_1_1(do_rdhwr_cpunum, cpu_T[0], cpu_T[0]); | |
7213 | 7276 | break; |
7214 | 7277 | case 1: |
7215 | 7278 | save_cpu_state(ctx, 1); |
7216 | - tcg_gen_helper_0_0(do_rdhwr_synci_step); | |
7279 | + tcg_gen_helper_1_1(do_rdhwr_synci_step, cpu_T[0], cpu_T[0]); | |
7217 | 7280 | break; |
7218 | 7281 | case 2: |
7219 | 7282 | save_cpu_state(ctx, 1); |
7220 | - tcg_gen_helper_0_0(do_rdhwr_cc); | |
7283 | + tcg_gen_helper_1_1(do_rdhwr_cc, cpu_T[0], cpu_T[0]); | |
7221 | 7284 | break; |
7222 | 7285 | case 3: |
7223 | 7286 | save_cpu_state(ctx, 1); |
7224 | - tcg_gen_helper_0_0(do_rdhwr_ccres); | |
7287 | + tcg_gen_helper_1_1(do_rdhwr_ccres, cpu_T[0], cpu_T[0]); | |
7225 | 7288 | break; |
7226 | 7289 | case 29: |
7227 | 7290 | #if defined (CONFIG_USER_ONLY) |
... | ... | @@ -7241,12 +7304,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7241 | 7304 | check_insn(env, ctx, ASE_MT); |
7242 | 7305 | gen_load_gpr(cpu_T[0], rt); |
7243 | 7306 | gen_load_gpr(cpu_T[1], rs); |
7244 | - tcg_gen_helper_0_0(do_fork); | |
7307 | + tcg_gen_helper_1_2(do_fork, cpu_T[0], cpu_T[0], cpu_T[1]); | |
7245 | 7308 | break; |
7246 | 7309 | case OPC_YIELD: |
7247 | 7310 | check_insn(env, ctx, ASE_MT); |
7248 | 7311 | gen_load_gpr(cpu_T[0], rs); |
7249 | - tcg_gen_helper_0_0(do_yield); | |
7312 | + tcg_gen_helper_1_1(do_yield, cpu_T[0], cpu_T[0]); | |
7250 | 7313 | gen_store_gpr(cpu_T[0], rd); |
7251 | 7314 | break; |
7252 | 7315 | #if defined(TARGET_MIPS64) |
... | ... | @@ -7263,11 +7326,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7263 | 7326 | switch (op2) { |
7264 | 7327 | case OPC_DSBH: |
7265 | 7328 | gen_load_gpr(cpu_T[1], rt); |
7266 | - tcg_gen_helper_0_0(do_dsbh); | |
7329 | + tcg_gen_helper_1_2(do_dsbh, cpu_T[0], cpu_T[0], cpu_T[1]); | |
7267 | 7330 | break; |
7268 | 7331 | case OPC_DSHD: |
7269 | 7332 | gen_load_gpr(cpu_T[1], rt); |
7270 | - tcg_gen_helper_0_0(do_dshd); | |
7333 | + tcg_gen_helper_1_2(do_dshd, cpu_T[0], cpu_T[0], cpu_T[1]); | |
7271 | 7334 | break; |
7272 | 7335 | default: /* Invalid */ |
7273 | 7336 | MIPS_INVAL("dbshfl"); |
... | ... | @@ -7330,31 +7393,31 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7330 | 7393 | switch (op2) { |
7331 | 7394 | case OPC_DMT: |
7332 | 7395 | check_insn(env, ctx, ASE_MT); |
7333 | - tcg_gen_helper_0_0(do_dmt); | |
7396 | + tcg_gen_helper_1_1(do_dmt, cpu_T[0], cpu_T[0]); | |
7334 | 7397 | break; |
7335 | 7398 | case OPC_EMT: |
7336 | 7399 | check_insn(env, ctx, ASE_MT); |
7337 | - tcg_gen_helper_0_0(do_emt); | |
7400 | + tcg_gen_helper_1_1(do_emt, cpu_T[0], cpu_T[0]); | |
7338 | 7401 | break; |
7339 | 7402 | case OPC_DVPE: |
7340 | 7403 | check_insn(env, ctx, ASE_MT); |
7341 | - tcg_gen_helper_0_0(do_dvpe); | |
7404 | + tcg_gen_helper_1_1(do_dvpe, cpu_T[0], cpu_T[0]); | |
7342 | 7405 | break; |
7343 | 7406 | case OPC_EVPE: |
7344 | 7407 | check_insn(env, ctx, ASE_MT); |
7345 | - tcg_gen_helper_0_0(do_evpe); | |
7408 | + tcg_gen_helper_1_1(do_evpe, cpu_T[0], cpu_T[0]); | |
7346 | 7409 | break; |
7347 | 7410 | case OPC_DI: |
7348 | 7411 | check_insn(env, ctx, ISA_MIPS32R2); |
7349 | 7412 | save_cpu_state(ctx, 1); |
7350 | - tcg_gen_helper_0_0(do_di); | |
7413 | + tcg_gen_helper_1_1(do_di, cpu_T[0], cpu_T[0]); | |
7351 | 7414 | /* Stop translation as we may have switched the execution mode */ |
7352 | 7415 | ctx->bstate = BS_STOP; |
7353 | 7416 | break; |
7354 | 7417 | case OPC_EI: |
7355 | 7418 | check_insn(env, ctx, ISA_MIPS32R2); |
7356 | 7419 | save_cpu_state(ctx, 1); |
7357 | - tcg_gen_helper_0_0(do_ei); | |
7420 | + tcg_gen_helper_1_1(do_ei, cpu_T[0], cpu_T[0]); | |
7358 | 7421 | /* Stop translation as we may have switched the execution mode */ |
7359 | 7422 | ctx->bstate = BS_STOP; |
7360 | 7423 | break; |
... | ... | @@ -7367,13 +7430,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) |
7367 | 7430 | break; |
7368 | 7431 | case OPC_RDPGPR: |
7369 | 7432 | check_insn(env, ctx, ISA_MIPS32R2); |
7370 | - gen_load_srsgpr(cpu_T[0], rt); | |
7371 | - gen_store_gpr(cpu_T[0], rd); | |
7433 | + gen_load_srsgpr(rt, rd); | |
7372 | 7434 | break; |
7373 | 7435 | case OPC_WRPGPR: |
7374 | 7436 | check_insn(env, ctx, ISA_MIPS32R2); |
7375 | - gen_load_gpr(cpu_T[0], rt); | |
7376 | - gen_store_srsgpr(cpu_T[0], rd); | |
7437 | + gen_store_srsgpr(rt, rd); | |
7377 | 7438 | break; |
7378 | 7439 | default: |
7379 | 7440 | MIPS_INVAL("cp0"); |
... | ... | @@ -7643,7 +7704,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, |
7643 | 7704 | if (env->breakpoints[j] == ctx.pc) { |
7644 | 7705 | save_cpu_state(&ctx, 1); |
7645 | 7706 | ctx.bstate = BS_BRANCH; |
7646 | - tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG); | |
7707 | + tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG); | |
7647 | 7708 | /* Include the breakpoint location or the tb won't |
7648 | 7709 | * be flushed when it must be. */ |
7649 | 7710 | ctx.pc += 4; |
... | ... | @@ -7685,7 +7746,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, |
7685 | 7746 | } |
7686 | 7747 | if (env->singlestep_enabled) { |
7687 | 7748 | save_cpu_state(&ctx, ctx.bstate == BS_NONE); |
7688 | - tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG); | |
7749 | + tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG); | |
7689 | 7750 | } else { |
7690 | 7751 | switch (ctx.bstate) { |
7691 | 7752 | case BS_STOP: | ... | ... |