Commit bcb0126ff44a59e636c89b0b191e7203c83ff29f
1 parent
cb63669a
More TCGv type fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4553 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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11 additions
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3 deletions
target-sparc/translate.c
| ... | ... | @@ -4401,7 +4401,8 @@ static void disas_sparc_insn(DisasContext * dc) |
| 4401 | 4401 | /* V9 stqf, store quad fpreg */ |
| 4402 | 4402 | CHECK_FPU_FEATURE(dc, FLOAT128); |
| 4403 | 4403 | gen_op_load_fpr_QT0(QFPREG(rd)); |
| 4404 | - tcg_gen_helper_0_2(helper_stqf, cpu_addr, dc->mem_idx); | |
| 4404 | + tcg_gen_helper_0_2(helper_stqf, cpu_addr, | |
| 4405 | + tcg_const_i32(dc->mem_idx)); | |
| 4405 | 4406 | break; |
| 4406 | 4407 | #else /* !TARGET_SPARC64 */ |
| 4407 | 4408 | /* stdfq, store floating point queue */ | ... | ... |
tcg/tcg-op.h
| ... | ... | @@ -56,6 +56,13 @@ static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2) |
| 56 | 56 | *gen_opparam_ptr++ = arg2; |
| 57 | 57 | } |
| 58 | 58 | |
| 59 | +static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) | |
| 60 | +{ | |
| 61 | + *gen_opc_ptr++ = opc; | |
| 62 | + *gen_opparam_ptr++ = arg1; | |
| 63 | + *gen_opparam_ptr++ = arg2; | |
| 64 | +} | |
| 65 | + | |
| 59 | 66 | static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3) |
| 60 | 67 | { |
| 61 | 68 | *gen_opc_ptr++ = opc; |
| ... | ... | @@ -1406,8 +1413,8 @@ static inline void tcg_gen_debug_insn_start(uint64_t pc) |
| 1406 | 1413 | { |
| 1407 | 1414 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ |
| 1408 | 1415 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS |
| 1409 | - tcg_gen_op2i(INDEX_op_debug_insn_start, | |
| 1410 | - (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
| 1416 | + tcg_gen_op2ii(INDEX_op_debug_insn_start, | |
| 1417 | + (uint32_t)(pc), (uint32_t)(pc >> 32)); | |
| 1411 | 1418 | #else |
| 1412 | 1419 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
| 1413 | 1420 | #endif | ... | ... |