gwj / at91sam9263 · Commits

Commit b7da58fd27bfbe7c14bc8a0332135663f17caecc

Authored by aurel32
1 parent 80e8bd2b

target-ppc: create a helper function to allow more flexible RAM allocation for PPC 4xx 

The 4xx SDRAM controller supports a small number of banks, and each bank must
be one of a small set of sizes. The number of banks and the supported sizes
varies by SoC.

This function uses the user-specified RAM size to fill in the "ram_bases" and
"ram_sizes" arrays required by ppc4xx_sdram_init().

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6063 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 47 additions and 0 deletions
hw/ppc4xx.h
  View file @b7da58f
@@ -48,6 +48,11 @@ enum { @@ -48,6 +48,11 @@ enum {
48 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, 48 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
49 uint32_t dcr_base, int has_ssr, int has_vr); 49 uint32_t dcr_base, int has_ssr, int has_vr);
50 50
  51 +ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
  52 + target_phys_addr_t ram_bases[],
  53 + target_phys_addr_t ram_sizes[],
  54 + const unsigned int sdram_bank_sizes[]);
  55 +
51 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, 56 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
52 target_phys_addr_t *ram_bases, 57 target_phys_addr_t *ram_bases,
53 target_phys_addr_t *ram_sizes, 58 target_phys_addr_t *ram_sizes,
hw/ppc4xx_devs.c
  View file @b7da58f
@@ -873,3 +873,45 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, @@ -873,3 +873,45 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
873 sdram_map_bcr(sdram); 873 sdram_map_bcr(sdram);
874 } 874 }
875 } 875 }
  876 +
  877 +/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
  878 + *
  879 + * sdram_bank_sizes[] must be 0-terminated.
  880 + *
  881 + * The 4xx SDRAM controller supports a small number of banks, and each bank
  882 + * must be one of a small set of sizes. The number of banks and the supported
  883 + * sizes varies by SoC. */
  884 +ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
  885 + target_phys_addr_t ram_bases[],
  886 + target_phys_addr_t ram_sizes[],
  887 + const unsigned int sdram_bank_sizes[])
  888 +{
  889 + ram_addr_t ram_end = 0;
  890 + int i;
  891 + int j;
  892 +
  893 + for (i = 0; i < nr_banks; i++) {
  894 + for (j = 0; sdram_bank_sizes[j] != 0; j++) {
  895 + unsigned int bank_size = sdram_bank_sizes[j];
  896 +
  897 + if (bank_size <= ram_size) {
  898 + ram_bases[i] = ram_end;
  899 + ram_sizes[i] = bank_size;
  900 + ram_end += bank_size;
  901 + ram_size -= bank_size;
  902 + break;
  903 + }
  904 + }
  905 +
  906 + if (!ram_size) {
  907 + /* No need to use the remaining banks. */
  908 + break;
  909 + }
  910 + }
  911 +
  912 + if (ram_size)
  913 + printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
  914 + (int)(ram_end >> 20));
  915 +
  916 + return ram_end;
  917 +}