gwj / at91sam9263 · Commits

Commit ae5d8053a124508650140fc72cccf9f2bd131871

Authored by ths
1 parent c3d2689d

Fix MIPS cache configuration, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3092 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 19 additions and 11 deletions
target-mips/translate_init.c
  View file @ae5d805
@@ -28,15 +28,11 @@ @@ -28,15 +28,11 @@
28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ 28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
29 (0x2 << CP0C0_K0)) 29 (0x2 << CP0C0_K0))
30 30
31 -/* Have config2, 64 sets Icache, 16 bytes Icache line,  
32 - 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,  
33 - no coprocessor2 attached, no MDMX support attached, 31 +/* Have config2, no coprocessor2 attached, no MDMX support attached,
34 no performance counters, watch registers present, 32 no performance counters, watch registers present,
35 no code compression, EJTAG present, no FPU */ 33 no code compression, EJTAG present, no FPU */
36 #define MIPS_CONFIG1 \ 34 #define MIPS_CONFIG1 \
37 ((1 << CP0C1_M) | \ 35 ((1 << CP0C1_M) | \
38 - (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \  
39 - (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \  
40 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ 36 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
41 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ 37 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
42 (0 << CP0C1_FP)) 38 (0 << CP0C1_FP))
@@ -82,7 +78,9 @@ static mips_def_t mips_defs[] = @@ -82,7 +78,9 @@ static mips_def_t mips_defs[] =
82 .name = "4Kc", 78 .name = "4Kc",
83 .CP0_PRid = 0x00018000, 79 .CP0_PRid = 0x00018000,
84 .CP0_Config0 = MIPS_CONFIG0, 80 .CP0_Config0 = MIPS_CONFIG0,
85 - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), 81 + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  82 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  83 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
86 .CP0_Config2 = MIPS_CONFIG2, 84 .CP0_Config2 = MIPS_CONFIG2,
87 .CP0_Config3 = MIPS_CONFIG3, 85 .CP0_Config3 = MIPS_CONFIG3,
88 .SYNCI_Step = 32, 86 .SYNCI_Step = 32,
@@ -94,7 +92,9 @@ static mips_def_t mips_defs[] = @@ -94,7 +92,9 @@ static mips_def_t mips_defs[] =
94 .name = "4KEcR1", 92 .name = "4KEcR1",
95 .CP0_PRid = 0x00018400, 93 .CP0_PRid = 0x00018400,
96 .CP0_Config0 = MIPS_CONFIG0, 94 .CP0_Config0 = MIPS_CONFIG0,
97 - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), 95 + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  96 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  97 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
98 .CP0_Config2 = MIPS_CONFIG2, 98 .CP0_Config2 = MIPS_CONFIG2,
99 .CP0_Config3 = MIPS_CONFIG3, 99 .CP0_Config3 = MIPS_CONFIG3,
100 .SYNCI_Step = 32, 100 .SYNCI_Step = 32,
@@ -106,7 +106,9 @@ static mips_def_t mips_defs[] = @@ -106,7 +106,9 @@ static mips_def_t mips_defs[] =
106 .name = "4KEc", 106 .name = "4KEc",
107 .CP0_PRid = 0x00019000, 107 .CP0_PRid = 0x00019000,
108 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), 108 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
109 - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), 109 + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  110 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  111 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
110 .CP0_Config2 = MIPS_CONFIG2, 112 .CP0_Config2 = MIPS_CONFIG2,
111 .CP0_Config3 = MIPS_CONFIG3, 113 .CP0_Config3 = MIPS_CONFIG3,
112 .SYNCI_Step = 32, 114 .SYNCI_Step = 32,
@@ -118,7 +120,9 @@ static mips_def_t mips_defs[] = @@ -118,7 +120,9 @@ static mips_def_t mips_defs[] =
118 .name = "24Kc", 120 .name = "24Kc",
119 .CP0_PRid = 0x00019300, 121 .CP0_PRid = 0x00019300,
120 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), 122 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
121 - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), 123 + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  124 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  125 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
122 .CP0_Config2 = MIPS_CONFIG2, 126 .CP0_Config2 = MIPS_CONFIG2,
123 .CP0_Config3 = MIPS_CONFIG3, 127 .CP0_Config3 = MIPS_CONFIG3,
124 .SYNCI_Step = 32, 128 .SYNCI_Step = 32,
@@ -130,7 +134,9 @@ static mips_def_t mips_defs[] = @@ -130,7 +134,9 @@ static mips_def_t mips_defs[] =
130 .name = "24Kf", 134 .name = "24Kf",
131 .CP0_PRid = 0x00019300, 135 .CP0_PRid = 0x00019300,
132 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), 136 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
133 - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU), 137 + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
  138 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  139 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
134 .CP0_Config2 = MIPS_CONFIG2, 140 .CP0_Config2 = MIPS_CONFIG2,
135 .CP0_Config3 = MIPS_CONFIG3, 141 .CP0_Config3 = MIPS_CONFIG3,
136 .SYNCI_Step = 32, 142 .SYNCI_Step = 32,
@@ -145,7 +151,9 @@ static mips_def_t mips_defs[] = @@ -145,7 +151,9 @@ static mips_def_t mips_defs[] =
145 .name = "R4000", 151 .name = "R4000",
146 .CP0_PRid = 0x00000400, 152 .CP0_PRid = 0x00000400,
147 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT), 153 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
148 - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU), 154 + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
  155 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  156 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
149 .CP0_Config2 = MIPS_CONFIG2, 157 .CP0_Config2 = MIPS_CONFIG2,
150 .CP0_Config3 = MIPS_CONFIG3, 158 .CP0_Config3 = MIPS_CONFIG3,
151 .SYNCI_Step = 16, 159 .SYNCI_Step = 16,