gwj / at91sam9263 · Commits

Commit a8f48dcc7c877593b1c99bf43e33fc63079570af

Authored by blueswir1
1 parent e64d7d59

Remove address masking after some rearranging 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5854 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 142 additions and 99 deletions
hw/slavio_intctl.c
  View file @a8f48dc
... ... @@ -49,8 +49,9 @@ do { printf("IRQ: " fmt , ##args); } while (0)
49 49 #define MAX_CPUS 16
50 50 #define MAX_PILS 16
51 51  
  52 +struct SLAVIO_CPUINTCTLState;
  53 +
52 54 typedef struct SLAVIO_INTCTLState {
53   - uint32_t intreg_pending[MAX_CPUS];
54 55 uint32_t intregm_pending;
55 56 uint32_t intregm_disabled;
56 57 uint32_t target_cpu;
... ... @@ -61,13 +62,18 @@ typedef struct SLAVIO_INTCTLState {
61 62 const uint32_t *intbit_to_level;
62 63 uint32_t cputimer_lbit, cputimer_mbit;
63 64 uint32_t pil_out[MAX_CPUS];
  65 + struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
64 66 } SLAVIO_INTCTLState;
65 67  
  68 +typedef struct SLAVIO_CPUINTCTLState {
  69 + uint32_t intreg_pending;
  70 + SLAVIO_INTCTLState *master;
  71 + uint32_t cpu;
  72 +} SLAVIO_CPUINTCTLState;
  73 +
66 74 #define INTCTL_MAXADDR 0xf
67 75 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
68   -#define INTCTLM_MAXADDR 0x13
69   -#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
70   -#define INTCTLM_MASK 0x1f
  76 +#define INTCTLM_SIZE 0x14
71 77 #define MASTER_IRQ_MASK ~0x0fa2007f
72 78 #define MASTER_DISABLE 0x80000000
73 79 #define CPU_SOFTIRQ_MASK 0xfffe0000
... ... @@ -75,20 +81,18 @@ typedef struct SLAVIO_INTCTLState {
75 81 #define CPU_IRQ_INT15_IN 0x0004000
76 82 #define CPU_IRQ_INT15_MASK 0x80000000
77 83  
78   -static void slavio_check_interrupts(void *opaque);
  84 +static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
79 85  
80 86 // per-cpu interrupt controller
81 87 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
82 88 {
83   - SLAVIO_INTCTLState *s = opaque;
  89 + SLAVIO_CPUINTCTLState *s = opaque;
84 90 uint32_t saddr, ret;
85   - int cpu;
86 91  
87   - cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
88   - saddr = (addr & INTCTL_MAXADDR) >> 2;
  92 + saddr = addr >> 2;
89 93 switch (saddr) {
90 94 case 0:
91   - ret = s->intreg_pending[cpu];
  95 + ret = s->intreg_pending;
92 96 break;
93 97 default:
94 98 ret = 0;
... ... @@ -102,29 +106,27 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
102 106 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
103 107 uint32_t val)
104 108 {
105   - SLAVIO_INTCTLState *s = opaque;
  109 + SLAVIO_CPUINTCTLState *s = opaque;
106 110 uint32_t saddr;
107   - int cpu;
108 111  
109   - cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
110   - saddr = (addr & INTCTL_MAXADDR) >> 2;
  112 + saddr = addr >> 2;
111 113 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
112 114 switch (saddr) {
113 115 case 1: // clear pending softints
114 116 if (val & CPU_IRQ_INT15_IN)
115 117 val |= CPU_IRQ_INT15_MASK;
116 118 val &= CPU_SOFTIRQ_MASK;
117   - s->intreg_pending[cpu] &= ~val;
118   - slavio_check_interrupts(s);
119   - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val,
120   - s->intreg_pending[cpu]);
  119 + s->intreg_pending &= ~val;
  120 + slavio_check_interrupts(s->master);
  121 + DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
  122 + s->intreg_pending);
121 123 break;
122 124 case 2: // set softint
123 125 val &= CPU_SOFTIRQ_MASK;
124   - s->intreg_pending[cpu] |= val;
125   - slavio_check_interrupts(s);
126   - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val,
127   - s->intreg_pending[cpu]);
  126 + s->intreg_pending |= val;
  127 + slavio_check_interrupts(s->master);
  128 + DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
  129 + s->intreg_pending);
128 130 break;
129 131 default:
130 132 break;
... ... @@ -149,7 +151,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
149 151 SLAVIO_INTCTLState *s = opaque;
150 152 uint32_t saddr, ret;
151 153  
152   - saddr = (addr & INTCTLM_MASK) >> 2;
  154 + saddr = addr >> 2;
153 155 switch (saddr) {
154 156 case 0:
155 157 ret = s->intregm_pending & ~MASTER_DISABLE;
... ... @@ -175,7 +177,7 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
175 177 SLAVIO_INTCTLState *s = opaque;
176 178 uint32_t saddr;
177 179  
178   - saddr = (addr & INTCTLM_MASK) >> 2;
  180 + saddr = addr >> 2;
179 181 DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
180 182 switch (saddr) {
181 183 case 2: // clear (enable)
... ... @@ -223,7 +225,8 @@ void slavio_pic_info(void *opaque)
223 225 int i;
224 226  
225 227 for (i = 0; i < MAX_CPUS; i++) {
226   - term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
  228 + term_printf("per-cpu %d: pending 0x%08x\n", i,
  229 + s->slaves[i]->intreg_pending);
227 230 }
228 231 term_printf("master: pending 0x%08x, disabled 0x%08x\n",
229 232 s->intregm_pending, s->intregm_disabled);
... ... @@ -247,9 +250,8 @@ void slavio_irq_info(void *opaque)
247 250 #endif
248 251 }
249 252  
250   -static void slavio_check_interrupts(void *opaque)
  253 +static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
251 254 {
252   - SLAVIO_INTCTLState *s = opaque;
253 255 uint32_t pending = s->intregm_pending, pil_pending;
254 256 unsigned int i, j;
255 257  
... ... @@ -265,7 +267,7 @@ static void slavio_check_interrupts(void *opaque)
265 267 pil_pending |= 1 << s->intbit_to_level[j];
266 268 }
267 269 }
268   - pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
  270 + pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
269 271  
270 272 for (j = 0; j < MAX_PILS; j++) {
271 273 if (pil_pending & (1 << j)) {
... ... @@ -298,10 +300,10 @@ static void slavio_set_irq(void *opaque, int irq, int level)
298 300 s->irq_count[pil]++;
299 301 #endif
300 302 s->intregm_pending |= mask;
301   - s->intreg_pending[s->target_cpu] |= 1 << pil;
  303 + s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
302 304 } else {
303 305 s->intregm_pending &= ~mask;
304   - s->intreg_pending[s->target_cpu] &= ~(1 << pil);
  306 + s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
305 307 }
306 308 slavio_check_interrupts(s);
307 309 }
... ... @@ -315,10 +317,10 @@ static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
315 317  
316 318 if (level) {
317 319 s->intregm_pending |= s->cputimer_mbit;
318   - s->intreg_pending[cpu] |= s->cputimer_lbit;
  320 + s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
319 321 } else {
320 322 s->intregm_pending &= ~s->cputimer_mbit;
321   - s->intreg_pending[cpu] &= ~s->cputimer_lbit;
  323 + s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
322 324 }
323 325  
324 326 slavio_check_interrupts(s);
... ... @@ -330,7 +332,7 @@ static void slavio_intctl_save(QEMUFile *f, void *opaque)
330 332 int i;
331 333  
332 334 for (i = 0; i < MAX_CPUS; i++) {
333   - qemu_put_be32s(f, &s->intreg_pending[i]);
  335 + qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
334 336 }
335 337 qemu_put_be32s(f, &s->intregm_pending);
336 338 qemu_put_be32s(f, &s->intregm_disabled);
... ... @@ -346,7 +348,7 @@ static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
346 348 return -EINVAL;
347 349  
348 350 for (i = 0; i < MAX_CPUS; i++) {
349   - qemu_get_be32s(f, &s->intreg_pending[i]);
  351 + qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
350 352 }
351 353 qemu_get_be32s(f, &s->intregm_pending);
352 354 qemu_get_be32s(f, &s->intregm_disabled);
... ... @@ -361,7 +363,7 @@ static void slavio_intctl_reset(void *opaque)
361 363 int i;
362 364  
363 365 for (i = 0; i < MAX_CPUS; i++) {
364   - s->intreg_pending[i] = 0;
  366 + s->slaves[i]->intreg_pending = 0;
365 367 }
366 368 s->intregm_disabled = ~MASTER_IRQ_MASK;
367 369 s->intregm_pending = 0;
... ... @@ -376,6 +378,7 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
376 378 {
377 379 int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
378 380 SLAVIO_INTCTLState *s;
  381 + SLAVIO_CPUINTCTLState *slave;
379 382  
380 383 s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
381 384 if (!s)
... ... @@ -383,12 +386,21 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
383 386  
384 387 s->intbit_to_level = intbit_to_level;
385 388 for (i = 0; i < MAX_CPUS; i++) {
  389 + slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
  390 + if (!slave)
  391 + return NULL;
  392 +
  393 + slave->cpu = i;
  394 + slave->master = s;
  395 +
386 396 slavio_intctl_io_memory = cpu_register_io_memory(0,
387 397 slavio_intctl_mem_read,
388 398 slavio_intctl_mem_write,
389   - s);
390   - cpu_register_physical_memory_offset(addr + i * TARGET_PAGE_SIZE,
391   - INTCTL_SIZE, slavio_intctl_io_memory, i * TARGET_PAGE_SIZE);
  399 + slave);
  400 + cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
  401 + slavio_intctl_io_memory);
  402 +
  403 + s->slaves[i] = slave;
392 404 s->cpu_irqs[i] = parent_irq[i];
393 405 }
394 406  
... ...
hw/slavio_misc.c
  View file @a8f48dc
... ... @@ -55,8 +55,7 @@ typedef struct MiscState {
55 55 } MiscState;
56 56  
57 57 #define MISC_SIZE 1
58   -#define SYSCTRL_MAXADDR 3
59   -#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
  58 +#define SYSCTRL_SIZE 4
60 59 #define LED_MAXADDR 1
61 60 #define LED_SIZE (LED_MAXADDR + 1)
62 61  
... ... @@ -112,62 +111,96 @@ void slavio_set_power_fail(void *opaque, int power_failing)
112 111 slavio_misc_update_irq(s);
113 112 }
114 113  
115   -static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
  114 +static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
  115 + uint32_t val)
  116 +{
  117 + MiscState *s = opaque;
  118 +
  119 + MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
  120 + s->config = val & 0xff;
  121 + slavio_misc_update_irq(s);
  122 +}
  123 +
  124 +static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
  125 +{
  126 + MiscState *s = opaque;
  127 + uint32_t ret = 0;
  128 +
  129 + ret = s->config;
  130 + MISC_DPRINTF("Read config %2.2x\n", ret);
  131 + return ret;
  132 +}
  133 +
  134 +static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = {
  135 + slavio_cfg_mem_readb,
  136 + NULL,
  137 + NULL,
  138 +};
  139 +
  140 +static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = {
  141 + slavio_cfg_mem_writeb,
  142 + NULL,
  143 + NULL,
  144 +};
  145 +
  146 +static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
116 147 uint32_t val)
117 148 {
118 149 MiscState *s = opaque;
119 150  
120   - switch (addr & MISC_MASK) {
121   - case MISC_CFG:
122   - MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
123   - s->config = val & 0xff;
124   - slavio_misc_update_irq(s);
125   - break;
126   - case MISC_DIAG:
127   - MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
128   - s->diag = val & 0xff;
129   - break;
130   - case MISC_MDM:
131   - MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
132   - s->mctrl = val & 0xff;
133   - break;
134   - default:
135   - break;
136   - }
  151 + MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
  152 + s->diag = val & 0xff;
137 153 }
138 154  
139   -static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
  155 +static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
140 156 {
141 157 MiscState *s = opaque;
142 158 uint32_t ret = 0;
143 159  
144   - switch (addr & MISC_MASK) {
145   - case MISC_CFG:
146   - ret = s->config;
147   - MISC_DPRINTF("Read config %2.2x\n", ret);
148   - break;
149   - case MISC_DIAG:
150   - ret = s->diag;
151   - MISC_DPRINTF("Read diag %2.2x\n", ret);
152   - break;
153   - case MISC_MDM:
154   - ret = s->mctrl;
155   - MISC_DPRINTF("Read modem control %2.2x\n", ret);
156   - break;
157   - default:
158   - break;
159   - }
  160 + ret = s->diag;
  161 + MISC_DPRINTF("Read diag %2.2x\n", ret);
  162 + return ret;
  163 +}
  164 +
  165 +static CPUReadMemoryFunc *slavio_diag_mem_read[3] = {
  166 + slavio_diag_mem_readb,
  167 + NULL,
  168 + NULL,
  169 +};
  170 +
  171 +static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = {
  172 + slavio_diag_mem_writeb,
  173 + NULL,
  174 + NULL,
  175 +};
  176 +
  177 +static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
  178 + uint32_t val)
  179 +{
  180 + MiscState *s = opaque;
  181 +
  182 + MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
  183 + s->mctrl = val & 0xff;
  184 +}
  185 +
  186 +static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
  187 +{
  188 + MiscState *s = opaque;
  189 + uint32_t ret = 0;
  190 +
  191 + ret = s->mctrl;
  192 + MISC_DPRINTF("Read modem control %2.2x\n", ret);
160 193 return ret;
161 194 }
162 195  
163   -static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
164   - slavio_misc_mem_readb,
  196 +static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = {
  197 + slavio_mdm_mem_readb,
165 198 NULL,
166 199 NULL,
167 200 };
168 201  
169   -static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
170   - slavio_misc_mem_writeb,
  202 +static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = {
  203 + slavio_mdm_mem_writeb,
171 204 NULL,
172 205 NULL,
173 206 };
... ... @@ -282,10 +315,9 @@ static CPUWriteMemoryFunc *apc_mem_write[3] = {
282 315 static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
283 316 {
284 317 MiscState *s = opaque;
285   - uint32_t ret = 0, saddr;
  318 + uint32_t ret = 0;
286 319  
287   - saddr = addr & SYSCTRL_MAXADDR;
288   - switch (saddr) {
  320 + switch (addr) {
289 321 case 0:
290 322 ret = s->sysctrl;
291 323 break;
... ... @@ -301,12 +333,10 @@ static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
301 333 uint32_t val)
302 334 {
303 335 MiscState *s = opaque;
304   - uint32_t saddr;
305 336  
306   - saddr = addr & SYSCTRL_MAXADDR;
307 337 MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
308 338 val);
309   - switch (saddr) {
  339 + switch (addr) {
310 340 case 0:
311 341 if (val & SYS_RESET) {
312 342 s->sysctrl = SYS_RESETSTAT;
... ... @@ -333,10 +363,9 @@ static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
333 363 static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
334 364 {
335 365 MiscState *s = opaque;
336   - uint32_t ret = 0, saddr;
  366 + uint32_t ret = 0;
337 367  
338   - saddr = addr & LED_MAXADDR;
339   - switch (saddr) {
  368 + switch (addr) {
340 369 case 0:
341 370 ret = s->leds;
342 371 break;
... ... @@ -352,12 +381,10 @@ static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
352 381 uint32_t val)
353 382 {
354 383 MiscState *s = opaque;
355   - uint32_t saddr;
356 384  
357   - saddr = addr & LED_MAXADDR;
358 385 MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
359 386 val);
360   - switch (saddr) {
  387 + switch (addr) {
361 388 case 0:
362 389 s->leds = val;
363 390 break;
... ... @@ -428,17 +455,21 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
428 455  
429 456 if (base) {
430 457 /* 8 bit registers */
431   - io = cpu_register_io_memory(0, slavio_misc_mem_read,
432   - slavio_misc_mem_write, s);
  458 +
433 459 // Slavio control
434   - cpu_register_physical_memory_offset(base + MISC_CFG, MISC_SIZE, io,
435   - MISC_CFG);
  460 + io = cpu_register_io_memory(0, slavio_cfg_mem_read,
  461 + slavio_cfg_mem_write, s);
  462 + cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
  463 +
436 464 // Diagnostics
437   - cpu_register_physical_memory_offset(base + MISC_DIAG, MISC_SIZE, io,
438   - MISC_DIAG);
  465 + io = cpu_register_io_memory(0, slavio_diag_mem_read,
  466 + slavio_diag_mem_write, s);
  467 + cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
  468 +
439 469 // Modem control
440   - cpu_register_physical_memory_offset(base + MISC_MDM, MISC_SIZE, io,
441   - MISC_MDM);
  470 + io = cpu_register_io_memory(0, slavio_mdm_mem_read,
  471 + slavio_mdm_mem_write, s);
  472 + cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
442 473  
443 474 /* 16 bit registers */
444 475 io = cpu_register_io_memory(0, slavio_led_mem_read,
... ...