gwj / at91sam9263 · Commits

Commit a73d39ba06d996a8474dbb2f8807abebc827a54b

Authored by aurel32
1 parent ccc9cc5b

SH4: Convert dyngen registers moves to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5099 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 9 additions and 15 deletions
target-sh4/op.c
  View file @a73d39b
@@ -946,12 +946,6 @@ void OPPROTO op_tst_imm_rN(void) @@ -946,12 +946,6 @@ void OPPROTO op_tst_imm_rN(void)
946 RETURN(); 946 RETURN();
947 } 947 }
948 948
949 -void OPPROTO op_movl_T0_T1(void)  
950 -{  
951 - T1 = T0;  
952 - RETURN();  
953 -}  
954 -  
955 void OPPROTO op_movl_fpul_FT0(void) 949 void OPPROTO op_movl_fpul_FT0(void)
956 { 950 {
957 FT0 = *(float32 *)&env->fpul; 951 FT0 = *(float32 *)&env->fpul;
target-sh4/translate.c
  View file @a73d39b
@@ -584,7 +584,7 @@ void _decode_opc(DisasContext * ctx) @@ -584,7 +584,7 @@ void _decode_opc(DisasContext * ctx)
584 case 0x000f: /* mac.l @Rm+,@Rn+ */ 584 case 0x000f: /* mac.l @Rm+,@Rn+ */
585 gen_op_movl_rN_T0(REG(B11_8)); 585 gen_op_movl_rN_T0(REG(B11_8));
586 gen_op_ldl_T0_T0(ctx); 586 gen_op_ldl_T0_T0(ctx);
587 - gen_op_movl_T0_T1(); 587 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
588 gen_op_movl_rN_T0(REG(B7_4)); 588 gen_op_movl_rN_T0(REG(B7_4));
589 gen_op_ldl_T0_T0(ctx); 589 gen_op_ldl_T0_T0(ctx);
590 gen_op_macl_T0_T1(); 590 gen_op_macl_T0_T1();
@@ -594,7 +594,7 @@ void _decode_opc(DisasContext * ctx) @@ -594,7 +594,7 @@ void _decode_opc(DisasContext * ctx)
594 case 0x400f: /* mac.w @Rm+,@Rn+ */ 594 case 0x400f: /* mac.w @Rm+,@Rn+ */
595 gen_op_movl_rN_T0(REG(B11_8)); 595 gen_op_movl_rN_T0(REG(B11_8));
596 gen_op_ldl_T0_T0(ctx); 596 gen_op_ldl_T0_T0(ctx);
597 - gen_op_movl_T0_T1(); 597 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
598 gen_op_movl_rN_T0(REG(B7_4)); 598 gen_op_movl_rN_T0(REG(B7_4));
599 gen_op_ldl_T0_T0(ctx); 599 gen_op_ldl_T0_T0(ctx);
600 gen_op_macw_T0_T1(); 600 gen_op_macw_T0_T1();
@@ -813,7 +813,7 @@ void _decode_opc(DisasContext * ctx) @@ -813,7 +813,7 @@ void _decode_opc(DisasContext * ctx)
813 case 0xcd00: /* and.b #imm,@(R0,GBR) */ 813 case 0xcd00: /* and.b #imm,@(R0,GBR) */
814 gen_op_movl_rN_T0(REG(0)); 814 gen_op_movl_rN_T0(REG(0));
815 gen_op_addl_GBR_T0(); 815 gen_op_addl_GBR_T0();
816 - gen_op_movl_T0_T1(); 816 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
817 gen_op_ldub_T0_T0(ctx); 817 gen_op_ldub_T0_T0(ctx);
818 gen_op_and_imm_T0(B7_0); 818 gen_op_and_imm_T0(B7_0);
819 gen_op_stb_T0_T1(ctx); 819 gen_op_stb_T0_T1(ctx);
@@ -865,21 +865,21 @@ void _decode_opc(DisasContext * ctx) @@ -865,21 +865,21 @@ void _decode_opc(DisasContext * ctx)
865 case 0xc000: /* mov.b R0,@(disp,GBR) */ 865 case 0xc000: /* mov.b R0,@(disp,GBR) */
866 gen_op_stc_gbr_T0(); 866 gen_op_stc_gbr_T0();
867 gen_op_addl_imm_T0(B7_0); 867 gen_op_addl_imm_T0(B7_0);
868 - gen_op_movl_T0_T1(); 868 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
869 gen_op_movl_rN_T0(REG(0)); 869 gen_op_movl_rN_T0(REG(0));
870 gen_op_stb_T0_T1(ctx); 870 gen_op_stb_T0_T1(ctx);
871 return; 871 return;
872 case 0xc100: /* mov.w R0,@(disp,GBR) */ 872 case 0xc100: /* mov.w R0,@(disp,GBR) */
873 gen_op_stc_gbr_T0(); 873 gen_op_stc_gbr_T0();
874 gen_op_addl_imm_T0(B7_0 * 2); 874 gen_op_addl_imm_T0(B7_0 * 2);
875 - gen_op_movl_T0_T1(); 875 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
876 gen_op_movl_rN_T0(REG(0)); 876 gen_op_movl_rN_T0(REG(0));
877 gen_op_stw_T0_T1(ctx); 877 gen_op_stw_T0_T1(ctx);
878 return; 878 return;
879 case 0xc200: /* mov.l R0,@(disp,GBR) */ 879 case 0xc200: /* mov.l R0,@(disp,GBR) */
880 gen_op_stc_gbr_T0(); 880 gen_op_stc_gbr_T0();
881 gen_op_addl_imm_T0(B7_0 * 4); 881 gen_op_addl_imm_T0(B7_0 * 4);
882 - gen_op_movl_T0_T1(); 882 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
883 gen_op_movl_rN_T0(REG(0)); 883 gen_op_movl_rN_T0(REG(0));
884 gen_op_stl_T0_T1(ctx); 884 gen_op_stl_T0_T1(ctx);
885 return; 885 return;
@@ -917,7 +917,7 @@ void _decode_opc(DisasContext * ctx) @@ -917,7 +917,7 @@ void _decode_opc(DisasContext * ctx)
917 case 0xcf00: /* or.b #imm,@(R0,GBR) */ 917 case 0xcf00: /* or.b #imm,@(R0,GBR) */
918 gen_op_movl_rN_T0(REG(0)); 918 gen_op_movl_rN_T0(REG(0));
919 gen_op_addl_GBR_T0(); 919 gen_op_addl_GBR_T0();
920 - gen_op_movl_T0_T1(); 920 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
921 gen_op_ldub_T0_T0(ctx); 921 gen_op_ldub_T0_T0(ctx);
922 gen_op_or_imm_T0(B7_0); 922 gen_op_or_imm_T0(B7_0);
923 gen_op_stb_T0_T1(ctx); 923 gen_op_stb_T0_T1(ctx);
@@ -942,7 +942,7 @@ void _decode_opc(DisasContext * ctx) @@ -942,7 +942,7 @@ void _decode_opc(DisasContext * ctx)
942 case 0xce00: /* xor.b #imm,@(R0,GBR) */ 942 case 0xce00: /* xor.b #imm,@(R0,GBR) */
943 gen_op_movl_rN_T0(REG(0)); 943 gen_op_movl_rN_T0(REG(0));
944 gen_op_addl_GBR_T0(); 944 gen_op_addl_GBR_T0();
945 - gen_op_movl_T0_T1(); 945 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
946 gen_op_ldub_T0_T0(ctx); 946 gen_op_ldub_T0_T0(ctx);
947 gen_op_xor_imm_T0(B7_0); 947 gen_op_xor_imm_T0(B7_0);
948 gen_op_stb_T0_T1(ctx); 948 gen_op_stb_T0_T1(ctx);
@@ -1110,7 +1110,7 @@ void _decode_opc(DisasContext * ctx) @@ -1110,7 +1110,7 @@ void _decode_opc(DisasContext * ctx)
1110 return; 1110 return;
1111 case 0x401b: /* tas.b @Rn */ 1111 case 0x401b: /* tas.b @Rn */
1112 gen_op_movl_rN_T0(REG(B11_8)); 1112 gen_op_movl_rN_T0(REG(B11_8));
1113 - gen_op_movl_T0_T1(); 1113 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1114 gen_op_ldub_T0_T0(ctx); 1114 gen_op_ldub_T0_T0(ctx);
1115 gen_op_cmp_eq_imm_T0(0); 1115 gen_op_cmp_eq_imm_T0(0);
1116 gen_op_or_imm_T0(0x80); 1116 gen_op_or_imm_T0(0x80);