gwj / at91sam9263 · Commits

Commit ccc9cc5bab6158b70ca333878358a9fbfb149f89

Authored by aurel32
1 parent f36672ae

SH4: Convert immediate loads to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 4 additions and 16 deletions
target-sh4/op.c
  View file @ccc9cc5
... ... @@ -37,18 +37,6 @@ static inline void cond_t(int cond)
37 37 clr_t();
38 38 }
39 39  
40   -void OPPROTO op_movl_imm_T0(void)
41   -{
42   - T0 = (uint32_t) PARAM1;
43   - RETURN();
44   -}
45   -
46   -void OPPROTO op_movl_imm_T1(void)
47   -{
48   - T1 = (uint32_t) PARAM1;
49   - RETURN();
50   -}
51   -
52 40 void OPPROTO op_cmp_eq_imm_T0(void)
53 41 {
54 42 cond_t((int32_t) T0 == (int32_t) PARAM1);
... ...
target-sh4/translate.c
  View file @ccc9cc5
... ... @@ -337,12 +337,12 @@ void _decode_opc(DisasContext * ctx)
337 337 gen_op_movl_imm_rN(B7_0s, REG(B11_8));
338 338 return;
339 339 case 0x9000: /* mov.w @(disp,PC),Rn */
340   - gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2);
  340 + tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
341 341 gen_op_ldw_T0_T0(ctx);
342 342 gen_op_movl_T0_rN(REG(B11_8));
343 343 return;
344 344 case 0xd000: /* mov.l @(disp,PC),Rn */
345   - gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3);
  345 + tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
346 346 gen_op_ldl_T0_T0(ctx);
347 347 gen_op_movl_T0_rN(REG(B11_8));
348 348 return;
... ... @@ -1181,14 +1181,14 @@ void _decode_opc(DisasContext * ctx)
1181 1181 break;
1182 1182 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1183 1183 if (!(ctx->fpscr & FPSCR_PR)) {
1184   - gen_op_movl_imm_T0(0);
  1184 + tcg_gen_movi_tl(cpu_T[0], 0);
1185 1185 gen_op_fmov_T0_frN(FREG(B11_8));
1186 1186 return;
1187 1187 }
1188 1188 break;
1189 1189 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1190 1190 if (!(ctx->fpscr & FPSCR_PR)) {
1191   - gen_op_movl_imm_T0(0x3f800000);
  1191 + tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
1192 1192 gen_op_fmov_T0_frN(FREG(B11_8));
1193 1193 return;
1194 1194 }
... ...