gwj / at91sam9263 · Commits

Commit a5e26afa6130c122949039e9483bd0c2c588cc91

Authored by aurel32
1 parent 1d542695

ppc: Convert FPR moves to TCG 

Replace op_{load,store}_fpr with tcg_gen_mov_i64.
Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].

This obsoletes op_template.h for REG > 7.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 65 additions and 182 deletions
target-ppc/op.c
  View file @a5e26af
... ... @@ -50,78 +50,6 @@
50 50 #define REG 7
51 51 #include "op_template.h"
52 52  
53   -#define REG 8
54   -#include "op_template.h"
55   -
56   -#define REG 9
57   -#include "op_template.h"
58   -
59   -#define REG 10
60   -#include "op_template.h"
61   -
62   -#define REG 11
63   -#include "op_template.h"
64   -
65   -#define REG 12
66   -#include "op_template.h"
67   -
68   -#define REG 13
69   -#include "op_template.h"
70   -
71   -#define REG 14
72   -#include "op_template.h"
73   -
74   -#define REG 15
75   -#include "op_template.h"
76   -
77   -#define REG 16
78   -#include "op_template.h"
79   -
80   -#define REG 17
81   -#include "op_template.h"
82   -
83   -#define REG 18
84   -#include "op_template.h"
85   -
86   -#define REG 19
87   -#include "op_template.h"
88   -
89   -#define REG 20
90   -#include "op_template.h"
91   -
92   -#define REG 21
93   -#include "op_template.h"
94   -
95   -#define REG 22
96   -#include "op_template.h"
97   -
98   -#define REG 23
99   -#include "op_template.h"
100   -
101   -#define REG 24
102   -#include "op_template.h"
103   -
104   -#define REG 25
105   -#include "op_template.h"
106   -
107   -#define REG 26
108   -#include "op_template.h"
109   -
110   -#define REG 27
111   -#include "op_template.h"
112   -
113   -#define REG 28
114   -#include "op_template.h"
115   -
116   -#define REG 29
117   -#include "op_template.h"
118   -
119   -#define REG 30
120   -#include "op_template.h"
121   -
122   -#define REG 31
123   -#include "op_template.h"
124   -
125 53 void OPPROTO op_print_mem_EA (void)
126 54 {
127 55 do_print_mem_EA(T0);
... ...
target-ppc/op_template.h
  View file @a5e26af
... ... @@ -18,7 +18,6 @@
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20 20  
21   -#if REG <= 7
22 21 /* Condition register moves */
23 22 void OPPROTO glue(op_load_crf_T0_crf, REG) (void)
24 23 {
... ... @@ -38,53 +37,4 @@ void OPPROTO glue(op_store_T0_crf_crf, REG) (void)
38 37 RETURN();
39 38 }
40 39  
41   -#if 0 // Unused
42   -void OPPROTO glue(op_store_T1_crf_crf, REG) (void)
43   -{
44   - env->crf[REG] = T1;
45   - RETURN();
46   -}
47   -#endif
48   -
49   -#endif /* REG <= 7 */
50   -
51   -/* floating point registers moves */
52   -void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void)
53   -{
54   - FT0 = env->fpr[REG];
55   - RETURN();
56   -}
57   -
58   -void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void)
59   -{
60   - env->fpr[REG] = FT0;
61   - RETURN();
62   -}
63   -
64   -void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void)
65   -{
66   - FT1 = env->fpr[REG];
67   - RETURN();
68   -}
69   -
70   -void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void)
71   -{
72   - env->fpr[REG] = FT1;
73   - RETURN();
74   -}
75   -
76   -void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void)
77   -{
78   - FT2 = env->fpr[REG];
79   - RETURN();
80   -}
81   -
82   -#if 0 // unused
83   -void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void)
84   -{
85   - env->fpr[REG] = FT2;
86   - RETURN();
87   -}
88   -#endif
89   -
90 40 #undef REG
... ...
target-ppc/translate.c
  View file @a5e26af
... ... @@ -50,11 +50,13 @@ static char cpu_reg_names[10*3 + 22*4 /* GPR */
50 50 #if !defined(TARGET_PPC64)
51 51 + 10*4 + 22*5 /* SPE GPRh */
52 52 #endif
  53 + + 10*4 + 22*5 /* FPR */
53 54 + 2*(10*6 + 22*7) /* AVRh, AVRl */];
54 55 static TCGv cpu_gpr[32];
55 56 #if !defined(TARGET_PPC64)
56 57 static TCGv cpu_gprh[32];
57 58 #endif
  59 +static TCGv cpu_fpr[32];
58 60 static TCGv cpu_avrh[32], cpu_avrl[32];
59 61  
60 62 /* dyngen register indexes */
... ... @@ -64,6 +66,7 @@ static TCGv cpu_T[3];
64 66 #else
65 67 static TCGv cpu_T64[3];
66 68 #endif
  69 +static TCGv cpu_FT[3];
67 70 static TCGv cpu_AVRh[3], cpu_AVRl[3];
68 71  
69 72 #include "gen-icount.h"
... ... @@ -101,6 +104,14 @@ void ppc_translate_init(void)
101 104 TCG_AREG0, offsetof(CPUState, t2_64),
102 105 "T2_64");
103 106 #endif
  107 +
  108 + cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  109 + offsetof(CPUState, ft0), "FT0");
  110 + cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  111 + offsetof(CPUState, ft1), "FT1");
  112 + cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  113 + offsetof(CPUState, ft2), "FT2");
  114 +
104 115 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
105 116 offsetof(CPUState, avr0.u64[0]), "AVR0H");
106 117 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
... ... @@ -127,6 +138,10 @@ void ppc_translate_init(void)
127 138 p += (i < 10) ? 4 : 5;
128 139 #endif
129 140  
  141 + sprintf(p, "fp%d", i);
  142 + cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  143 + offsetof(CPUState, fpr[i]), p);
  144 +
130 145 sprintf(p, "avr%dH", i);
131 146 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 147 offsetof(CPUState, avr[i].u64[0]), p);
... ... @@ -196,16 +211,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
196 211 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
197 212 #endif
198 213  
199   -/* floating point registers moves */
200   -GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
201   -GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
202   -GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
203   -GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
204   -GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
205   -#if 0 // unused
206   -GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
207   -#endif
208   -
209 214 /* internal defines */
210 215 typedef struct DisasContext {
211 216 struct TranslationBlock *tb;
... ... @@ -1780,15 +1785,15 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1780 1785 GEN_EXCP_NO_FP(ctx); \
1781 1786 return; \
1782 1787 } \
1783   - gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1784   - gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1785   - gen_op_load_fpr_FT2(rB(ctx->opcode)); \
  1788 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
  1789 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
  1790 + tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
1786 1791 gen_reset_fpstatus(); \
1787 1792 gen_op_f##op(); \
1788 1793 if (isfloat) { \
1789 1794 gen_op_frsp(); \
1790 1795 } \
1791   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  1796 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
1792 1797 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1793 1798 }
1794 1799  
... ... @@ -1803,14 +1808,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1803 1808 GEN_EXCP_NO_FP(ctx); \
1804 1809 return; \
1805 1810 } \
1806   - gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1807   - gen_op_load_fpr_FT1(rB(ctx->opcode)); \
  1811 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
  1812 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
1808 1813 gen_reset_fpstatus(); \
1809 1814 gen_op_f##op(); \
1810 1815 if (isfloat) { \
1811 1816 gen_op_frsp(); \
1812 1817 } \
1813   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  1818 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
1814 1819 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1815 1820 }
1816 1821 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
... ... @@ -1824,14 +1829,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1824 1829 GEN_EXCP_NO_FP(ctx); \
1825 1830 return; \
1826 1831 } \
1827   - gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1828   - gen_op_load_fpr_FT1(rC(ctx->opcode)); \
  1832 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
  1833 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1829 1834 gen_reset_fpstatus(); \
1830 1835 gen_op_f##op(); \
1831 1836 if (isfloat) { \
1832 1837 gen_op_frsp(); \
1833 1838 } \
1834   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  1839 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
1835 1840 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1836 1841 }
1837 1842 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
... ... @@ -1845,10 +1850,10 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1845 1850 GEN_EXCP_NO_FP(ctx); \
1846 1851 return; \
1847 1852 } \
1848   - gen_op_load_fpr_FT0(rB(ctx->opcode)); \
  1853 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
1849 1854 gen_reset_fpstatus(); \
1850 1855 gen_op_f##name(); \
1851   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  1856 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
1852 1857 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1853 1858 }
1854 1859  
... ... @@ -1859,10 +1864,10 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1859 1864 GEN_EXCP_NO_FP(ctx); \
1860 1865 return; \
1861 1866 } \
1862   - gen_op_load_fpr_FT0(rB(ctx->opcode)); \
  1867 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
1863 1868 gen_reset_fpstatus(); \
1864 1869 gen_op_f##name(); \
1865   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  1870 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
1866 1871 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1867 1872 }
1868 1873  
... ... @@ -1902,10 +1907,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1902 1907 GEN_EXCP_NO_FP(ctx);
1903 1908 return;
1904 1909 }
1905   - gen_op_load_fpr_FT0(rB(ctx->opcode));
  1910 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
1906 1911 gen_reset_fpstatus();
1907 1912 gen_op_fsqrt();
1908   - gen_op_store_FT0_fpr(rD(ctx->opcode));
  1913 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
1909 1914 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1910 1915 }
1911 1916  
... ... @@ -1915,11 +1920,11 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1915 1920 GEN_EXCP_NO_FP(ctx);
1916 1921 return;
1917 1922 }
1918   - gen_op_load_fpr_FT0(rB(ctx->opcode));
  1923 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
1919 1924 gen_reset_fpstatus();
1920 1925 gen_op_fsqrt();
1921 1926 gen_op_frsp();
1922   - gen_op_store_FT0_fpr(rD(ctx->opcode));
  1927 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
1923 1928 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1924 1929 }
1925 1930  
... ... @@ -1966,8 +1971,8 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1966 1971 GEN_EXCP_NO_FP(ctx);
1967 1972 return;
1968 1973 }
1969   - gen_op_load_fpr_FT0(rA(ctx->opcode));
1970   - gen_op_load_fpr_FT1(rB(ctx->opcode));
  1974 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
  1975 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
1971 1976 gen_reset_fpstatus();
1972 1977 gen_op_fcmpo();
1973 1978 gen_op_store_T0_crf(crfD(ctx->opcode));
... ... @@ -1981,8 +1986,8 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1981 1986 GEN_EXCP_NO_FP(ctx);
1982 1987 return;
1983 1988 }
1984   - gen_op_load_fpr_FT0(rA(ctx->opcode));
1985   - gen_op_load_fpr_FT1(rB(ctx->opcode));
  1989 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
  1990 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
1986 1991 gen_reset_fpstatus();
1987 1992 gen_op_fcmpu();
1988 1993 gen_op_store_T0_crf(crfD(ctx->opcode));
... ... @@ -2002,8 +2007,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2002 2007 GEN_EXCP_NO_FP(ctx);
2003 2008 return;
2004 2009 }
2005   - gen_op_load_fpr_FT0(rB(ctx->opcode));
2006   - gen_op_store_FT0_fpr(rD(ctx->opcode));
  2010 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
  2011 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2007 2012 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
2008 2013 }
2009 2014  
... ... @@ -2041,7 +2046,7 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2041 2046 gen_optimize_fprf();
2042 2047 gen_reset_fpstatus();
2043 2048 gen_op_load_fpscr_FT0();
2044   - gen_op_store_FT0_fpr(rD(ctx->opcode));
  2049 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2045 2050 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
2046 2051 }
2047 2052  
... ... @@ -2096,7 +2101,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2096 2101 return;
2097 2102 }
2098 2103 gen_optimize_fprf();
2099   - gen_op_load_fpr_FT0(rB(ctx->opcode));
  2104 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2100 2105 gen_reset_fpstatus();
2101 2106 gen_op_store_fpscr(FM(ctx->opcode));
2102 2107 if (unlikely(Rc(ctx->opcode) != 0)) {
... ... @@ -2716,7 +2721,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2716 2721 } \
2717 2722 gen_addr_imm_index(ctx, 0); \
2718 2723 op_ldst(l##width); \
2719   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  2724 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2720 2725 }
2721 2726  
2722 2727 #define GEN_LDUF(width, opc, type) \
... ... @@ -2732,7 +2737,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2732 2737 } \
2733 2738 gen_addr_imm_index(ctx, 0); \
2734 2739 op_ldst(l##width); \
2735   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  2740 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2736 2741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2737 2742 }
2738 2743  
... ... @@ -2749,7 +2754,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2749 2754 } \
2750 2755 gen_addr_reg_index(ctx); \
2751 2756 op_ldst(l##width); \
2752   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  2757 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2753 2758 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2754 2759 }
2755 2760  
... ... @@ -2762,7 +2767,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2762 2767 } \
2763 2768 gen_addr_reg_index(ctx); \
2764 2769 op_ldst(l##width); \
2765   - gen_op_store_FT0_fpr(rD(ctx->opcode)); \
  2770 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2766 2771 }
2767 2772  
2768 2773 #define GEN_LDFS(width, op, type) \
... ... @@ -2786,7 +2791,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2786 2791 return; \
2787 2792 } \
2788 2793 gen_addr_imm_index(ctx, 0); \
2789   - gen_op_load_fpr_FT0(rS(ctx->opcode)); \
  2794 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2790 2795 op_ldst(st##width); \
2791 2796 }
2792 2797  
... ... @@ -2802,7 +2807,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2802 2807 return; \
2803 2808 } \
2804 2809 gen_addr_imm_index(ctx, 0); \
2805   - gen_op_load_fpr_FT0(rS(ctx->opcode)); \
  2810 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2806 2811 op_ldst(st##width); \
2807 2812 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2808 2813 }
... ... @@ -2819,7 +2824,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2819 2824 return; \
2820 2825 } \
2821 2826 gen_addr_reg_index(ctx); \
2822   - gen_op_load_fpr_FT0(rS(ctx->opcode)); \
  2827 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2823 2828 op_ldst(st##width); \
2824 2829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2825 2830 }
... ... @@ -2832,7 +2837,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2832 2837 return; \
2833 2838 } \
2834 2839 gen_addr_reg_index(ctx); \
2835   - gen_op_load_fpr_FT0(rS(ctx->opcode)); \
  2840 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2836 2841 op_ldst(st##width); \
2837 2842 }
2838 2843  
... ... @@ -4522,8 +4527,8 @@ GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4522 4527 gen_update_nip(ctx, ctx->nip - 4);
4523 4528 gen_addr_imm_index(ctx, 0);
4524 4529 op_POWER2_lfq();
4525   - gen_op_store_FT0_fpr(rD(ctx->opcode));
4526   - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
  4530 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
  4531 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4527 4532 }
4528 4533  
4529 4534 /* lfqu */
... ... @@ -4535,8 +4540,8 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4535 4540 gen_update_nip(ctx, ctx->nip - 4);
4536 4541 gen_addr_imm_index(ctx, 0);
4537 4542 op_POWER2_lfq();
4538   - gen_op_store_FT0_fpr(rD(ctx->opcode));
4539   - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
  4543 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
  4544 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4540 4545 if (ra != 0)
4541 4546 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4542 4547 }
... ... @@ -4550,8 +4555,8 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4550 4555 gen_update_nip(ctx, ctx->nip - 4);
4551 4556 gen_addr_reg_index(ctx);
4552 4557 op_POWER2_lfq();
4553   - gen_op_store_FT0_fpr(rD(ctx->opcode));
4554   - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
  4558 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
  4559 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4555 4560 if (ra != 0)
4556 4561 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4557 4562 }
... ... @@ -4563,8 +4568,8 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4563 4568 gen_update_nip(ctx, ctx->nip - 4);
4564 4569 gen_addr_reg_index(ctx);
4565 4570 op_POWER2_lfq();
4566   - gen_op_store_FT0_fpr(rD(ctx->opcode));
4567   - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
  4571 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
  4572 + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4568 4573 }
4569 4574  
4570 4575 /* stfq */
... ... @@ -4573,8 +4578,8 @@ GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4573 4578 /* NIP cannot be restored if the memory exception comes from an helper */
4574 4579 gen_update_nip(ctx, ctx->nip - 4);
4575 4580 gen_addr_imm_index(ctx, 0);
4576   - gen_op_load_fpr_FT0(rS(ctx->opcode));
4577   - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
  4581 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
  4582 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4578 4583 op_POWER2_stfq();
4579 4584 }
4580 4585  
... ... @@ -4586,8 +4591,8 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4586 4591 /* NIP cannot be restored if the memory exception comes from an helper */
4587 4592 gen_update_nip(ctx, ctx->nip - 4);
4588 4593 gen_addr_imm_index(ctx, 0);
4589   - gen_op_load_fpr_FT0(rS(ctx->opcode));
4590   - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
  4594 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
  4595 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4591 4596 op_POWER2_stfq();
4592 4597 if (ra != 0)
4593 4598 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
... ... @@ -4601,8 +4606,8 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4601 4606 /* NIP cannot be restored if the memory exception comes from an helper */
4602 4607 gen_update_nip(ctx, ctx->nip - 4);
4603 4608 gen_addr_reg_index(ctx);
4604   - gen_op_load_fpr_FT0(rS(ctx->opcode));
4605   - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
  4609 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
  4610 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4606 4611 op_POWER2_stfq();
4607 4612 if (ra != 0)
4608 4613 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
... ... @@ -4614,8 +4619,8 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4614 4619 /* NIP cannot be restored if the memory exception comes from an helper */
4615 4620 gen_update_nip(ctx, ctx->nip - 4);
4616 4621 gen_addr_reg_index(ctx);
4617   - gen_op_load_fpr_FT0(rS(ctx->opcode));
4618   - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
  4622 + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
  4623 + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4619 4624 op_POWER2_stfq();
4620 4625 }
4621 4626  
... ...