gwj / at91sam9263 · Commits

Commit 1d54269590484a7b87c6d342ef6d2e8333a62674

Authored by aurel32
1 parent bd7d9a6d

ppc: Convert Altivec register moves to TCG 

Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 38 additions and 53 deletions
target-ppc/op_template.h
  View file @1d54269
... ... @@ -18,45 +18,6 @@
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20 20  
21   -/* Altivec registers moves */
22   -void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
23   -{
24   - AVR0 = env->avr[REG];
25   - RETURN();
26   -}
27   -
28   -void OPPROTO glue(op_load_avr_A1_avr, REG) (void)
29   -{
30   - AVR1 = env->avr[REG];
31   - RETURN();
32   -}
33   -
34   -void OPPROTO glue(op_load_avr_A2_avr, REG) (void)
35   -{
36   - AVR2 = env->avr[REG];
37   - RETURN();
38   -}
39   -
40   -void OPPROTO glue(op_store_A0_avr_avr, REG) (void)
41   -{
42   - env->avr[REG] = AVR0;
43   - RETURN();
44   -}
45   -
46   -void OPPROTO glue(op_store_A1_avr_avr, REG) (void)
47   -{
48   - env->avr[REG] = AVR1;
49   - RETURN();
50   -}
51   -
52   -#if 0 // unused
53   -void OPPROTO glue(op_store_A2_avr_avr, REG) (void)
54   -{
55   - env->avr[REG] = AVR2;
56   - RETURN();
57   -}
58   -#endif
59   -
60 21 #if REG <= 7
61 22 /* Condition register moves */
62 23 void OPPROTO glue(op_load_crf_T0_crf, REG) (void)
... ...
target-ppc/translate.c
  View file @1d54269
... ... @@ -46,15 +46,16 @@
46 46  
47 47 /* global register indexes */
48 48 static TCGv cpu_env;
49   -static char cpu_reg_names[10*3 + 22*4
  49 +static char cpu_reg_names[10*3 + 22*4 /* GPR */
50 50 #if !defined(TARGET_PPC64)
51   - + 10*4 + 22*5
  51 + + 10*4 + 22*5 /* SPE GPRh */
52 52 #endif
53   -];
  53 + + 2*(10*6 + 22*7) /* AVRh, AVRl */];
54 54 static TCGv cpu_gpr[32];
55 55 #if !defined(TARGET_PPC64)
56 56 static TCGv cpu_gprh[32];
57 57 #endif
  58 +static TCGv cpu_avrh[32], cpu_avrl[32];
58 59  
59 60 /* dyngen register indexes */
60 61 static TCGv cpu_T[3];
... ... @@ -63,6 +64,7 @@ static TCGv cpu_T[3];
63 64 #else
64 65 static TCGv cpu_T64[3];
65 66 #endif
  67 +static TCGv cpu_AVRh[3], cpu_AVRl[3];
66 68  
67 69 #include "gen-icount.h"
68 70  
... ... @@ -99,7 +101,19 @@ void ppc_translate_init(void)
99 101 TCG_AREG0, offsetof(CPUState, t2_64),
100 102 "T2_64");
101 103 #endif
102   -
  104 + cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  105 + offsetof(CPUState, avr0.u64[0]), "AVR0H");
  106 + cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  107 + offsetof(CPUState, avr0.u64[1]), "AVR0L");
  108 + cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  109 + offsetof(CPUState, avr1.u64[0]), "AVR1H");
  110 + cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  111 + offsetof(CPUState, avr1.u64[1]), "AVR1L");
  112 + cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  113 + offsetof(CPUState, avr2.u64[0]), "AVR2H");
  114 + cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  115 + offsetof(CPUState, avr2.u64[1]), "AVR2L");
  116 +
103 117 p = cpu_reg_names;
104 118 for (i = 0; i < 32; i++) {
105 119 sprintf(p, "r%d", i);
... ... @@ -112,6 +126,15 @@ void ppc_translate_init(void)
112 126 offsetof(CPUState, gprh[i]), p);
113 127 p += (i < 10) ? 4 : 5;
114 128 #endif
  129 +
  130 + sprintf(p, "avr%dH", i);
  131 + cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  132 + offsetof(CPUState, avr[i].u64[0]), p);
  133 + p += (i < 10) ? 6 : 7;
  134 + sprintf(p, "avr%dL", i);
  135 + cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  136 + offsetof(CPUState, avr[i].u64[1]), p);
  137 + p += (i < 10) ? 6 : 7;
115 138 }
116 139  
117 140 /* register helpers */
... ... @@ -5241,15 +5264,16 @@ GEN_HANDLER2(icbt_440, &quot;icbt&quot;, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5241 5264  
5242 5265 /*** Altivec vector extension ***/
5243 5266 /* Altivec registers moves */
5244   -GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5245   -GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5246   -GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5247 5267  
5248   -GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5249   -GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5250   -#if 0 // unused
5251   -GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5252   -#endif
  5268 +static always_inline void gen_load_avr(int t, int reg) {
  5269 + tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
  5270 + tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
  5271 +}
  5272 +
  5273 +static always_inline void gen_store_avr(int reg, int t) {
  5274 + tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
  5275 + tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
  5276 +}
5253 5277  
5254 5278 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5255 5279 #define OP_VR_LD_TABLE(name) \
... ... @@ -5270,7 +5294,7 @@ GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5270 5294 } \
5271 5295 gen_addr_reg_index(ctx); \
5272 5296 op_vr_ldst(vr_l##name); \
5273   - gen_op_store_A0_avr(rD(ctx->opcode)); \
  5297 + gen_store_avr(rD(ctx->opcode), 0); \
5274 5298 }
5275 5299  
5276 5300 #define GEN_VR_STX(name, opc2, opc3) \
... ... @@ -5281,7 +5305,7 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5281 5305 return; \
5282 5306 } \
5283 5307 gen_addr_reg_index(ctx); \
5284   - gen_op_load_avr_A0(rS(ctx->opcode)); \
  5308 + gen_load_avr(0, rS(ctx->opcode)); \
5285 5309 op_vr_ldst(vr_st##name); \
5286 5310 }
5287 5311  
... ...