gwj / at91sam9263 · Commits

Commit a456d59c20fb959c431069cee0f94d5b4628a198

Authored by blueswir1
1 parent 9b64997f

VM load/save support for PPC CPU 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6143 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 165 additions and 0 deletions
target-ppc/machine.c
  View file @a456d59
... ... @@ -13,9 +13,174 @@ void register_machines(void)
13 13  
14 14 void cpu_save(QEMUFile *f, void *opaque)
15 15 {
  16 + CPUState *env = (CPUState *)opaque;
  17 + unsigned int i, j;
  18 +
  19 + for (i = 0; i < 32; i++)
  20 + qemu_put_betls(f, &env->gpr[i]);
  21 +#if !defined(TARGET_PPC64)
  22 + for (i = 0; i < 32; i++)
  23 + qemu_put_betls(f, &env->gprh[i]);
  24 +#endif
  25 + qemu_put_betls(f, &env->lr);
  26 + qemu_put_betls(f, &env->ctr);
  27 + for (i = 0; i < 8; i++)
  28 + qemu_put_be32s(f, &env->crf[i]);
  29 + qemu_put_betls(f, &env->xer);
  30 + qemu_put_betls(f, &env->reserve);
  31 + qemu_put_betls(f, &env->msr);
  32 + for (i = 0; i < 4; i++)
  33 + qemu_put_betls(f, &env->tgpr[i]);
  34 + for (i = 0; i < 32; i++) {
  35 + union {
  36 + float64 d;
  37 + uint64_t l;
  38 + } u;
  39 + u.d = env->fpr[i];
  40 + qemu_put_be64(f, u.l);
  41 + }
  42 + qemu_put_be32s(f, &env->fpscr);
  43 + qemu_put_sbe32s(f, &env->access_type);
  44 +#if !defined(CONFIG_USER_ONLY)
  45 +#if defined(TARGET_PPC64)
  46 + qemu_put_betls(f, &env->asr);
  47 + qemu_put_sbe32s(f, &env->slb_nr);
  48 +#endif
  49 + qemu_put_betls(f, &env->sdr1);
  50 + for (i = 0; i < 32; i++)
  51 + qemu_put_betls(f, &env->sr[i]);
  52 + for (i = 0; i < 2; i++)
  53 + for (j = 0; j < 8; j++)
  54 + qemu_put_betls(f, &env->DBAT[i][j]);
  55 + for (i = 0; i < 2; i++)
  56 + for (j = 0; j < 8; j++)
  57 + qemu_put_betls(f, &env->IBAT[i][j]);
  58 + qemu_put_sbe32s(f, &env->nb_tlb);
  59 + qemu_put_sbe32s(f, &env->tlb_per_way);
  60 + qemu_put_sbe32s(f, &env->nb_ways);
  61 + qemu_put_sbe32s(f, &env->last_way);
  62 + qemu_put_sbe32s(f, &env->id_tlbs);
  63 + qemu_put_sbe32s(f, &env->nb_pids);
  64 + if (env->tlb) {
  65 + // XXX assumes 6xx
  66 + for (i = 0; i < env->nb_tlb; i++) {
  67 + qemu_put_betls(f, &env->tlb[i].tlb6.pte0);
  68 + qemu_put_betls(f, &env->tlb[i].tlb6.pte1);
  69 + qemu_put_betls(f, &env->tlb[i].tlb6.EPN);
  70 + }
  71 + }
  72 + for (i = 0; i < 4; i++)
  73 + qemu_put_betls(f, &env->pb[i]);
  74 +#endif
  75 + for (i = 0; i < 1024; i++)
  76 + qemu_put_betls(f, &env->spr[i]);
  77 + qemu_put_be32s(f, &env->vscr);
  78 + qemu_put_be64s(f, &env->spe_acc);
  79 + qemu_put_be32s(f, &env->spe_fscr);
  80 + qemu_put_betls(f, &env->msr_mask);
  81 + qemu_put_be32s(f, &env->flags);
  82 + qemu_put_sbe32s(f, &env->error_code);
  83 + qemu_put_be32s(f, &env->pending_interrupts);
  84 +#if !defined(CONFIG_USER_ONLY)
  85 + qemu_put_be32s(f, &env->irq_input_state);
  86 + for (i = 0; i < POWERPC_EXCP_NB; i++)
  87 + qemu_put_betls(f, &env->excp_vectors[i]);
  88 + qemu_put_betls(f, &env->excp_prefix);
  89 + qemu_put_betls(f, &env->ivor_mask);
  90 + qemu_put_betls(f, &env->ivpr_mask);
  91 + qemu_put_betls(f, &env->hreset_vector);
  92 +#endif
  93 + qemu_put_betls(f, &env->nip);
  94 + qemu_put_betls(f, &env->hflags);
  95 + qemu_put_betls(f, &env->hflags_nmsr);
  96 + qemu_put_sbe32s(f, &env->mmu_idx);
  97 + qemu_put_sbe32s(f, &env->power_mode);
16 98 }
17 99  
18 100 int cpu_load(QEMUFile *f, void *opaque, int version_id)
19 101 {
  102 + CPUState *env = (CPUState *)opaque;
  103 + unsigned int i, j;
  104 +
  105 + for (i = 0; i < 32; i++)
  106 + qemu_get_betls(f, &env->gpr[i]);
  107 +#if !defined(TARGET_PPC64)
  108 + for (i = 0; i < 32; i++)
  109 + qemu_get_betls(f, &env->gprh[i]);
  110 +#endif
  111 + qemu_get_betls(f, &env->lr);
  112 + qemu_get_betls(f, &env->ctr);
  113 + for (i = 0; i < 8; i++)
  114 + qemu_get_be32s(f, &env->crf[i]);
  115 + qemu_get_betls(f, &env->xer);
  116 + qemu_get_betls(f, &env->reserve);
  117 + qemu_get_betls(f, &env->msr);
  118 + for (i = 0; i < 4; i++)
  119 + qemu_get_betls(f, &env->tgpr[i]);
  120 + for (i = 0; i < 32; i++) {
  121 + union {
  122 + float64 d;
  123 + uint64_t l;
  124 + } u;
  125 + u.l = qemu_get_be64(f);
  126 + env->fpr[i] = u.d;
  127 + }
  128 + qemu_get_be32s(f, &env->fpscr);
  129 + qemu_get_sbe32s(f, &env->access_type);
  130 +#if !defined(CONFIG_USER_ONLY)
  131 +#if defined(TARGET_PPC64)
  132 + qemu_get_betls(f, &env->asr);
  133 + qemu_get_sbe32s(f, &env->slb_nr);
  134 +#endif
  135 + qemu_get_betls(f, &env->sdr1);
  136 + for (i = 0; i < 32; i++)
  137 + qemu_get_betls(f, &env->sr[i]);
  138 + for (i = 0; i < 2; i++)
  139 + for (j = 0; j < 8; j++)
  140 + qemu_get_betls(f, &env->DBAT[i][j]);
  141 + for (i = 0; i < 2; i++)
  142 + for (j = 0; j < 8; j++)
  143 + qemu_get_betls(f, &env->IBAT[i][j]);
  144 + qemu_get_sbe32s(f, &env->nb_tlb);
  145 + qemu_get_sbe32s(f, &env->tlb_per_way);
  146 + qemu_get_sbe32s(f, &env->nb_ways);
  147 + qemu_get_sbe32s(f, &env->last_way);
  148 + qemu_get_sbe32s(f, &env->id_tlbs);
  149 + qemu_get_sbe32s(f, &env->nb_pids);
  150 + if (env->tlb) {
  151 + // XXX assumes 6xx
  152 + for (i = 0; i < env->nb_tlb; i++) {
  153 + qemu_get_betls(f, &env->tlb[i].tlb6.pte0);
  154 + qemu_get_betls(f, &env->tlb[i].tlb6.pte1);
  155 + qemu_get_betls(f, &env->tlb[i].tlb6.EPN);
  156 + }
  157 + }
  158 + for (i = 0; i < 4; i++)
  159 + qemu_get_betls(f, &env->pb[i]);
  160 +#endif
  161 + for (i = 0; i < 1024; i++)
  162 + qemu_get_betls(f, &env->spr[i]);
  163 + qemu_get_be32s(f, &env->vscr);
  164 + qemu_get_be64s(f, &env->spe_acc);
  165 + qemu_get_be32s(f, &env->spe_fscr);
  166 + qemu_get_betls(f, &env->msr_mask);
  167 + qemu_get_be32s(f, &env->flags);
  168 + qemu_get_sbe32s(f, &env->error_code);
  169 + qemu_get_be32s(f, &env->pending_interrupts);
  170 +#if !defined(CONFIG_USER_ONLY)
  171 + qemu_get_be32s(f, &env->irq_input_state);
  172 + for (i = 0; i < POWERPC_EXCP_NB; i++)
  173 + qemu_get_betls(f, &env->excp_vectors[i]);
  174 + qemu_get_betls(f, &env->excp_prefix);
  175 + qemu_get_betls(f, &env->ivor_mask);
  176 + qemu_get_betls(f, &env->ivpr_mask);
  177 + qemu_get_betls(f, &env->hreset_vector);
  178 +#endif
  179 + qemu_get_betls(f, &env->nip);
  180 + qemu_get_betls(f, &env->hflags);
  181 + qemu_get_betls(f, &env->hflags_nmsr);
  182 + qemu_get_sbe32s(f, &env->mmu_idx);
  183 + qemu_get_sbe32s(f, &env->power_mode);
  184 +
20 185 return 0;
21 186 }
... ...