Commit 9b64997f464bcef06739e9c81a927bf48c375255
1 parent
ac0df51d
VM load/save support for PPC devices
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6142 c046a42c-6fe2-441c-8c8c-71466251a162
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7 changed files
with
326 additions
and
65 deletions
hw/adb.c
... | ... | @@ -262,6 +262,31 @@ static int adb_kbd_request(ADBDevice *d, uint8_t *obuf, |
262 | 262 | return olen; |
263 | 263 | } |
264 | 264 | |
265 | +static void adb_kbd_save(QEMUFile *f, void *opaque) | |
266 | +{ | |
267 | + KBDState *s = (KBDState *)opaque; | |
268 | + | |
269 | + qemu_put_buffer(f, s->data, sizeof(s->data)); | |
270 | + qemu_put_sbe32s(f, &s->rptr); | |
271 | + qemu_put_sbe32s(f, &s->wptr); | |
272 | + qemu_put_sbe32s(f, &s->count); | |
273 | +} | |
274 | + | |
275 | +static int adb_kbd_load(QEMUFile *f, void *opaque, int version_id) | |
276 | +{ | |
277 | + KBDState *s = (KBDState *)opaque; | |
278 | + | |
279 | + if (version_id != 1) | |
280 | + return -EINVAL; | |
281 | + | |
282 | + qemu_get_buffer(f, s->data, sizeof(s->data)); | |
283 | + qemu_get_sbe32s(f, &s->rptr); | |
284 | + qemu_get_sbe32s(f, &s->wptr); | |
285 | + qemu_get_sbe32s(f, &s->count); | |
286 | + | |
287 | + return 0; | |
288 | +} | |
289 | + | |
265 | 290 | static int adb_kbd_reset(ADBDevice *d) |
266 | 291 | { |
267 | 292 | KBDState *s = d->opaque; |
... | ... | @@ -281,6 +306,8 @@ void adb_kbd_init(ADBBusState *bus) |
281 | 306 | d = adb_register_device(bus, ADB_KEYBOARD, adb_kbd_request, |
282 | 307 | adb_kbd_reset, s); |
283 | 308 | qemu_add_kbd_event_handler(adb_kbd_put_keycode, d); |
309 | + register_savevm("adb_kbd", -1, 1, adb_kbd_save, | |
310 | + adb_kbd_load, s); | |
284 | 311 | } |
285 | 312 | |
286 | 313 | /***************************************************************/ |
... | ... | @@ -413,6 +440,33 @@ static int adb_mouse_reset(ADBDevice *d) |
413 | 440 | return 0; |
414 | 441 | } |
415 | 442 | |
443 | +static void adb_mouse_save(QEMUFile *f, void *opaque) | |
444 | +{ | |
445 | + MouseState *s = (MouseState *)opaque; | |
446 | + | |
447 | + qemu_put_sbe32s(f, &s->buttons_state); | |
448 | + qemu_put_sbe32s(f, &s->last_buttons_state); | |
449 | + qemu_put_sbe32s(f, &s->dx); | |
450 | + qemu_put_sbe32s(f, &s->dy); | |
451 | + qemu_put_sbe32s(f, &s->dz); | |
452 | +} | |
453 | + | |
454 | +static int adb_mouse_load(QEMUFile *f, void *opaque, int version_id) | |
455 | +{ | |
456 | + MouseState *s = (MouseState *)opaque; | |
457 | + | |
458 | + if (version_id != 1) | |
459 | + return -EINVAL; | |
460 | + | |
461 | + qemu_get_sbe32s(f, &s->buttons_state); | |
462 | + qemu_get_sbe32s(f, &s->last_buttons_state); | |
463 | + qemu_get_sbe32s(f, &s->dx); | |
464 | + qemu_get_sbe32s(f, &s->dy); | |
465 | + qemu_get_sbe32s(f, &s->dz); | |
466 | + | |
467 | + return 0; | |
468 | +} | |
469 | + | |
416 | 470 | void adb_mouse_init(ADBBusState *bus) |
417 | 471 | { |
418 | 472 | ADBDevice *d; |
... | ... | @@ -422,4 +476,6 @@ void adb_mouse_init(ADBBusState *bus) |
422 | 476 | d = adb_register_device(bus, ADB_MOUSE, adb_mouse_request, |
423 | 477 | adb_mouse_reset, s); |
424 | 478 | qemu_add_mouse_event_handler(adb_mouse_event, d, 0, "QEMU ADB Mouse"); |
479 | + register_savevm("adb_mouse", -1, 1, adb_mouse_save, | |
480 | + adb_mouse_load, s); | |
425 | 481 | } | ... | ... |
hw/cuda.c
... | ... | @@ -633,6 +633,79 @@ static CPUReadMemoryFunc *cuda_read[] = { |
633 | 633 | &cuda_readl, |
634 | 634 | }; |
635 | 635 | |
636 | +static void cuda_save_timer(QEMUFile *f, CUDATimer *s) | |
637 | +{ | |
638 | + qemu_put_be16s(f, &s->latch); | |
639 | + qemu_put_be16s(f, &s->counter_value); | |
640 | + qemu_put_sbe64s(f, &s->load_time); | |
641 | + qemu_put_sbe64s(f, &s->next_irq_time); | |
642 | + if (s->timer) | |
643 | + qemu_put_timer(f, s->timer); | |
644 | +} | |
645 | + | |
646 | +static void cuda_save(QEMUFile *f, void *opaque) | |
647 | +{ | |
648 | + CUDAState *s = (CUDAState *)opaque; | |
649 | + | |
650 | + qemu_put_ubyte(f, s->b); | |
651 | + qemu_put_ubyte(f, s->a); | |
652 | + qemu_put_ubyte(f, s->dirb); | |
653 | + qemu_put_ubyte(f, s->dira); | |
654 | + qemu_put_ubyte(f, s->sr); | |
655 | + qemu_put_ubyte(f, s->acr); | |
656 | + qemu_put_ubyte(f, s->pcr); | |
657 | + qemu_put_ubyte(f, s->ifr); | |
658 | + qemu_put_ubyte(f, s->ier); | |
659 | + qemu_put_ubyte(f, s->anh); | |
660 | + qemu_put_sbe32s(f, &s->data_in_size); | |
661 | + qemu_put_sbe32s(f, &s->data_in_index); | |
662 | + qemu_put_sbe32s(f, &s->data_out_index); | |
663 | + qemu_put_ubyte(f, s->autopoll); | |
664 | + qemu_put_buffer(f, s->data_in, sizeof(s->data_in)); | |
665 | + qemu_put_buffer(f, s->data_out, sizeof(s->data_out)); | |
666 | + cuda_save_timer(f, &s->timers[0]); | |
667 | + cuda_save_timer(f, &s->timers[1]); | |
668 | +} | |
669 | + | |
670 | +static void cuda_load_timer(QEMUFile *f, CUDATimer *s) | |
671 | +{ | |
672 | + qemu_get_be16s(f, &s->latch); | |
673 | + qemu_get_be16s(f, &s->counter_value); | |
674 | + qemu_get_sbe64s(f, &s->load_time); | |
675 | + qemu_get_sbe64s(f, &s->next_irq_time); | |
676 | + if (s->timer) | |
677 | + qemu_get_timer(f, s->timer); | |
678 | +} | |
679 | + | |
680 | +static int cuda_load(QEMUFile *f, void *opaque, int version_id) | |
681 | +{ | |
682 | + CUDAState *s = (CUDAState *)opaque; | |
683 | + | |
684 | + if (version_id != 1) | |
685 | + return -EINVAL; | |
686 | + | |
687 | + s->b = qemu_get_ubyte(f); | |
688 | + s->a = qemu_get_ubyte(f); | |
689 | + s->dirb = qemu_get_ubyte(f); | |
690 | + s->dira = qemu_get_ubyte(f); | |
691 | + s->sr = qemu_get_ubyte(f); | |
692 | + s->acr = qemu_get_ubyte(f); | |
693 | + s->pcr = qemu_get_ubyte(f); | |
694 | + s->ifr = qemu_get_ubyte(f); | |
695 | + s->ier = qemu_get_ubyte(f); | |
696 | + s->anh = qemu_get_ubyte(f); | |
697 | + qemu_get_sbe32s(f, &s->data_in_size); | |
698 | + qemu_get_sbe32s(f, &s->data_in_index); | |
699 | + qemu_get_sbe32s(f, &s->data_out_index); | |
700 | + s->autopoll = qemu_get_ubyte(f); | |
701 | + qemu_get_buffer(f, s->data_in, sizeof(s->data_in)); | |
702 | + qemu_get_buffer(f, s->data_out, sizeof(s->data_out)); | |
703 | + cuda_load_timer(f, &s->timers[0]); | |
704 | + cuda_load_timer(f, &s->timers[1]); | |
705 | + | |
706 | + return 0; | |
707 | +} | |
708 | + | |
636 | 709 | static void cuda_reset(void *opaque) |
637 | 710 | { |
638 | 711 | CUDAState *s = opaque; |
... | ... | @@ -673,6 +746,7 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq) |
673 | 746 | |
674 | 747 | s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
675 | 748 | *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s); |
749 | + register_savevm("cuda", -1, 1, cuda_save, cuda_load, s); | |
676 | 750 | qemu_register_reset(cuda_reset, s); |
677 | 751 | cuda_reset(s); |
678 | 752 | } | ... | ... |
hw/grackle_pci.c
... | ... | @@ -105,6 +105,23 @@ static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) |
105 | 105 | qemu_set_irq(pic[irq_num + 0x15], level); |
106 | 106 | } |
107 | 107 | |
108 | +static void pci_grackle_save(QEMUFile* f, void *opaque) | |
109 | +{ | |
110 | + PCIDevice *d = opaque; | |
111 | + | |
112 | + pci_device_save(d, f); | |
113 | +} | |
114 | + | |
115 | +static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id) | |
116 | +{ | |
117 | + PCIDevice *d = opaque; | |
118 | + | |
119 | + if (version_id != 1) | |
120 | + return -EINVAL; | |
121 | + | |
122 | + return pci_device_load(d, f); | |
123 | +} | |
124 | + | |
108 | 125 | static void pci_grackle_reset(void *opaque) |
109 | 126 | { |
110 | 127 | } |
... | ... | @@ -164,6 +181,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) |
164 | 181 | d->config[0x26] = 0x00; // prefetchable_memory_limit |
165 | 182 | d->config[0x27] = 0x85; |
166 | 183 | #endif |
184 | + register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d); | |
167 | 185 | qemu_register_reset(pci_grackle_reset, d); |
168 | 186 | pci_grackle_reset(d); |
169 | 187 | ... | ... |
hw/heathrow_pic.c
... | ... | @@ -165,6 +165,43 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level) |
165 | 165 | heathrow_pic_update(s); |
166 | 166 | } |
167 | 167 | |
168 | +static void heathrow_pic_save_one(QEMUFile *f, HeathrowPIC *s) | |
169 | +{ | |
170 | + qemu_put_be32s(f, &s->events); | |
171 | + qemu_put_be32s(f, &s->mask); | |
172 | + qemu_put_be32s(f, &s->levels); | |
173 | + qemu_put_be32s(f, &s->level_triggered); | |
174 | +} | |
175 | + | |
176 | +static void heathrow_pic_save(QEMUFile *f, void *opaque) | |
177 | +{ | |
178 | + HeathrowPICS *s = (HeathrowPICS *)opaque; | |
179 | + | |
180 | + heathrow_pic_save_one(f, &s->pics[0]); | |
181 | + heathrow_pic_save_one(f, &s->pics[1]); | |
182 | +} | |
183 | + | |
184 | +static void heathrow_pic_load_one(QEMUFile *f, HeathrowPIC *s) | |
185 | +{ | |
186 | + qemu_get_be32s(f, &s->events); | |
187 | + qemu_get_be32s(f, &s->mask); | |
188 | + qemu_get_be32s(f, &s->levels); | |
189 | + qemu_get_be32s(f, &s->level_triggered); | |
190 | +} | |
191 | + | |
192 | +static int heathrow_pic_load(QEMUFile *f, void *opaque, int version_id) | |
193 | +{ | |
194 | + HeathrowPICS *s = (HeathrowPICS *)opaque; | |
195 | + | |
196 | + if (version_id != 1) | |
197 | + return -EINVAL; | |
198 | + | |
199 | + heathrow_pic_load_one(f, &s->pics[0]); | |
200 | + heathrow_pic_load_one(f, &s->pics[1]); | |
201 | + | |
202 | + return 0; | |
203 | +} | |
204 | + | |
168 | 205 | static void heathrow_pic_reset_one(HeathrowPIC *s) |
169 | 206 | { |
170 | 207 | memset(s, '\0', sizeof(HeathrowPIC)); |
... | ... | @@ -191,6 +228,8 @@ qemu_irq *heathrow_pic_init(int *pmem_index, |
191 | 228 | s->irqs = irqs[0]; |
192 | 229 | *pmem_index = cpu_register_io_memory(0, pic_read, pic_write, s); |
193 | 230 | |
231 | + register_savevm("heathrow_pic", -1, 1, heathrow_pic_save, | |
232 | + heathrow_pic_load, s); | |
194 | 233 | qemu_register_reset(heathrow_pic_reset, s); |
195 | 234 | heathrow_pic_reset(s); |
196 | 235 | return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64); | ... | ... |
hw/ide.c
... | ... | @@ -3058,6 +3058,71 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num, |
3058 | 3058 | } |
3059 | 3059 | } |
3060 | 3060 | |
3061 | +static void pci_ide_save(QEMUFile* f, void *opaque) | |
3062 | +{ | |
3063 | + PCIIDEState *d = opaque; | |
3064 | + int i; | |
3065 | + | |
3066 | + pci_device_save(&d->dev, f); | |
3067 | + | |
3068 | + for(i = 0; i < 2; i++) { | |
3069 | + BMDMAState *bm = &d->bmdma[i]; | |
3070 | + qemu_put_8s(f, &bm->cmd); | |
3071 | + qemu_put_8s(f, &bm->status); | |
3072 | + qemu_put_be32s(f, &bm->addr); | |
3073 | + /* XXX: if a transfer is pending, we do not save it yet */ | |
3074 | + } | |
3075 | + | |
3076 | + /* per IDE interface data */ | |
3077 | + for(i = 0; i < 2; i++) { | |
3078 | + IDEState *s = &d->ide_if[i * 2]; | |
3079 | + uint8_t drive1_selected; | |
3080 | + qemu_put_8s(f, &s->cmd); | |
3081 | + drive1_selected = (s->cur_drive != s); | |
3082 | + qemu_put_8s(f, &drive1_selected); | |
3083 | + } | |
3084 | + | |
3085 | + /* per IDE drive data */ | |
3086 | + for(i = 0; i < 4; i++) { | |
3087 | + ide_save(f, &d->ide_if[i]); | |
3088 | + } | |
3089 | +} | |
3090 | + | |
3091 | +static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) | |
3092 | +{ | |
3093 | + PCIIDEState *d = opaque; | |
3094 | + int ret, i; | |
3095 | + | |
3096 | + if (version_id != 1) | |
3097 | + return -EINVAL; | |
3098 | + ret = pci_device_load(&d->dev, f); | |
3099 | + if (ret < 0) | |
3100 | + return ret; | |
3101 | + | |
3102 | + for(i = 0; i < 2; i++) { | |
3103 | + BMDMAState *bm = &d->bmdma[i]; | |
3104 | + qemu_get_8s(f, &bm->cmd); | |
3105 | + qemu_get_8s(f, &bm->status); | |
3106 | + qemu_get_be32s(f, &bm->addr); | |
3107 | + /* XXX: if a transfer is pending, we do not save it yet */ | |
3108 | + } | |
3109 | + | |
3110 | + /* per IDE interface data */ | |
3111 | + for(i = 0; i < 2; i++) { | |
3112 | + IDEState *s = &d->ide_if[i * 2]; | |
3113 | + uint8_t drive1_selected; | |
3114 | + qemu_get_8s(f, &s->cmd); | |
3115 | + qemu_get_8s(f, &drive1_selected); | |
3116 | + s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)]; | |
3117 | + } | |
3118 | + | |
3119 | + /* per IDE drive data */ | |
3120 | + for(i = 0; i < 4; i++) { | |
3121 | + ide_load(f, &d->ide_if[i]); | |
3122 | + } | |
3123 | + return 0; | |
3124 | +} | |
3125 | + | |
3061 | 3126 | /* XXX: call it also when the MRDMODE is changed from the PCI config |
3062 | 3127 | registers */ |
3063 | 3128 | static void cmd646_update_irq(PCIIDEState *d) |
... | ... | @@ -3145,75 +3210,11 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table, |
3145 | 3210 | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]); |
3146 | 3211 | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]); |
3147 | 3212 | |
3213 | + register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); | |
3148 | 3214 | qemu_register_reset(cmd646_reset, d); |
3149 | 3215 | cmd646_reset(d); |
3150 | 3216 | } |
3151 | 3217 | |
3152 | -static void pci_ide_save(QEMUFile* f, void *opaque) | |
3153 | -{ | |
3154 | - PCIIDEState *d = opaque; | |
3155 | - int i; | |
3156 | - | |
3157 | - pci_device_save(&d->dev, f); | |
3158 | - | |
3159 | - for(i = 0; i < 2; i++) { | |
3160 | - BMDMAState *bm = &d->bmdma[i]; | |
3161 | - qemu_put_8s(f, &bm->cmd); | |
3162 | - qemu_put_8s(f, &bm->status); | |
3163 | - qemu_put_be32s(f, &bm->addr); | |
3164 | - /* XXX: if a transfer is pending, we do not save it yet */ | |
3165 | - } | |
3166 | - | |
3167 | - /* per IDE interface data */ | |
3168 | - for(i = 0; i < 2; i++) { | |
3169 | - IDEState *s = &d->ide_if[i * 2]; | |
3170 | - uint8_t drive1_selected; | |
3171 | - qemu_put_8s(f, &s->cmd); | |
3172 | - drive1_selected = (s->cur_drive != s); | |
3173 | - qemu_put_8s(f, &drive1_selected); | |
3174 | - } | |
3175 | - | |
3176 | - /* per IDE drive data */ | |
3177 | - for(i = 0; i < 4; i++) { | |
3178 | - ide_save(f, &d->ide_if[i]); | |
3179 | - } | |
3180 | -} | |
3181 | - | |
3182 | -static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) | |
3183 | -{ | |
3184 | - PCIIDEState *d = opaque; | |
3185 | - int ret, i; | |
3186 | - | |
3187 | - if (version_id != 1) | |
3188 | - return -EINVAL; | |
3189 | - ret = pci_device_load(&d->dev, f); | |
3190 | - if (ret < 0) | |
3191 | - return ret; | |
3192 | - | |
3193 | - for(i = 0; i < 2; i++) { | |
3194 | - BMDMAState *bm = &d->bmdma[i]; | |
3195 | - qemu_get_8s(f, &bm->cmd); | |
3196 | - qemu_get_8s(f, &bm->status); | |
3197 | - qemu_get_be32s(f, &bm->addr); | |
3198 | - /* XXX: if a transfer is pending, we do not save it yet */ | |
3199 | - } | |
3200 | - | |
3201 | - /* per IDE interface data */ | |
3202 | - for(i = 0; i < 2; i++) { | |
3203 | - IDEState *s = &d->ide_if[i * 2]; | |
3204 | - uint8_t drive1_selected; | |
3205 | - qemu_get_8s(f, &s->cmd); | |
3206 | - qemu_get_8s(f, &drive1_selected); | |
3207 | - s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)]; | |
3208 | - } | |
3209 | - | |
3210 | - /* per IDE drive data */ | |
3211 | - for(i = 0; i < 4; i++) { | |
3212 | - ide_load(f, &d->ide_if[i]); | |
3213 | - } | |
3214 | - return 0; | |
3215 | -} | |
3216 | - | |
3217 | 3218 | static void piix3_reset(void *opaque) |
3218 | 3219 | { |
3219 | 3220 | PCIIDEState *d = opaque; |
... | ... | @@ -3417,6 +3418,44 @@ static CPUReadMemoryFunc *pmac_ide_read[] = { |
3417 | 3418 | pmac_ide_readl, |
3418 | 3419 | }; |
3419 | 3420 | |
3421 | +static void pmac_ide_save(QEMUFile *f, void *opaque) | |
3422 | +{ | |
3423 | + IDEState *s = (IDEState *)opaque; | |
3424 | + uint8_t drive1_selected; | |
3425 | + unsigned int i; | |
3426 | + | |
3427 | + /* per IDE interface data */ | |
3428 | + qemu_put_8s(f, &s->cmd); | |
3429 | + drive1_selected = (s->cur_drive != s); | |
3430 | + qemu_put_8s(f, &drive1_selected); | |
3431 | + | |
3432 | + /* per IDE drive data */ | |
3433 | + for(i = 0; i < 2; i++) { | |
3434 | + ide_save(f, &s[i]); | |
3435 | + } | |
3436 | +} | |
3437 | + | |
3438 | +static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id) | |
3439 | +{ | |
3440 | + IDEState *s = (IDEState *)opaque; | |
3441 | + uint8_t drive1_selected; | |
3442 | + unsigned int i; | |
3443 | + | |
3444 | + if (version_id != 1) | |
3445 | + return -EINVAL; | |
3446 | + | |
3447 | + /* per IDE interface data */ | |
3448 | + qemu_get_8s(f, &s->cmd); | |
3449 | + qemu_get_8s(f, &drive1_selected); | |
3450 | + s->cur_drive = &s[(drive1_selected != 0)]; | |
3451 | + | |
3452 | + /* per IDE drive data */ | |
3453 | + for(i = 0; i < 2; i++) { | |
3454 | + ide_load(f, &s[i]); | |
3455 | + } | |
3456 | + return 0; | |
3457 | +} | |
3458 | + | |
3420 | 3459 | static void pmac_ide_reset(void *opaque) |
3421 | 3460 | { |
3422 | 3461 | IDEState *s = (IDEState *)opaque; |
... | ... | @@ -3438,6 +3477,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq) |
3438 | 3477 | |
3439 | 3478 | pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read, |
3440 | 3479 | pmac_ide_write, &ide_if[0]); |
3480 | + register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, &ide_if[0]); | |
3441 | 3481 | qemu_register_reset(pmac_ide_reset, &ide_if[0]); |
3442 | 3482 | pmac_ide_reset(&ide_if[0]); |
3443 | 3483 | return pmac_ide_memory; | ... | ... |
hw/mac_dbdma.c
... | ... | @@ -88,6 +88,18 @@ static CPUReadMemoryFunc *dbdma_read[] = { |
88 | 88 | &dbdma_readl, |
89 | 89 | }; |
90 | 90 | |
91 | +static void dbdma_save(QEMUFile *f, void *opaque) | |
92 | +{ | |
93 | +} | |
94 | + | |
95 | +static int dbdma_load(QEMUFile *f, void *opaque, int version_id) | |
96 | +{ | |
97 | + if (version_id != 1) | |
98 | + return -EINVAL; | |
99 | + | |
100 | + return 0; | |
101 | +} | |
102 | + | |
91 | 103 | static void dbdma_reset(void *opaque) |
92 | 104 | { |
93 | 105 | } |
... | ... | @@ -95,6 +107,7 @@ static void dbdma_reset(void *opaque) |
95 | 107 | void dbdma_init (int *dbdma_mem_index) |
96 | 108 | { |
97 | 109 | *dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); |
110 | + register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, NULL); | |
98 | 111 | qemu_register_reset(dbdma_reset, NULL); |
99 | 112 | dbdma_reset(NULL); |
100 | 113 | } | ... | ... |
hw/mac_nvram.c
... | ... | @@ -104,6 +104,25 @@ static CPUReadMemoryFunc *nvram_read[] = { |
104 | 104 | &macio_nvram_readb, |
105 | 105 | }; |
106 | 106 | |
107 | +static void macio_nvram_save(QEMUFile *f, void *opaque) | |
108 | +{ | |
109 | + MacIONVRAMState *s = (MacIONVRAMState *)opaque; | |
110 | + | |
111 | + qemu_put_buffer(f, s->data, s->size); | |
112 | +} | |
113 | + | |
114 | +static int macio_nvram_load(QEMUFile *f, void *opaque, int version_id) | |
115 | +{ | |
116 | + MacIONVRAMState *s = (MacIONVRAMState *)opaque; | |
117 | + | |
118 | + if (version_id != 1) | |
119 | + return -EINVAL; | |
120 | + | |
121 | + qemu_get_buffer(f, s->data, s->size); | |
122 | + | |
123 | + return 0; | |
124 | +} | |
125 | + | |
107 | 126 | static void macio_nvram_reset(void *opaque) |
108 | 127 | { |
109 | 128 | } |
... | ... | @@ -124,6 +143,8 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size) |
124 | 143 | |
125 | 144 | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); |
126 | 145 | *mem_index = s->mem_index; |
146 | + register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load, | |
147 | + s); | |
127 | 148 | qemu_register_reset(macio_nvram_reset, s); |
128 | 149 | macio_nvram_reset(s); |
129 | 150 | ... | ... |