Commit 9bc921b82fcaed68a28be552fcf6eef77e635e22
1 parent
ac7e6319
Added port ID to PIO
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2 changed files
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20 additions
and
5 deletions
hw/at91_pio.c
... | ... | @@ -89,6 +89,7 @@ typedef struct PIOState { |
89 | 89 | /* Mask of unknown state of PIO pins, needed for pull-up resistor |
90 | 90 | implementation */ |
91 | 91 | uint32_t unknown_state; |
92 | + int portid; | |
92 | 93 | } PIOState; |
93 | 94 | |
94 | 95 | void at91_pio_set_pin(void *opaque, int pin, int level) |
... | ... | @@ -186,7 +187,7 @@ static void at91_pio_mem_write(void *opaque, target_phys_addr_t offset, |
186 | 187 | PIOState *s = opaque; |
187 | 188 | int i; |
188 | 189 | |
189 | - DPRINTF("Writing PIO: offset=0x%08lx, value=0x%08x\n",offset,value); | |
190 | + DPRINTF("Writing PIO: portid=%d, offset=0x%08lx, value=0x%08x\n", s->portid, offset, value); | |
190 | 191 | |
191 | 192 | offset &= PIO_SIZE - 1; |
192 | 193 | |
... | ... | @@ -219,7 +220,7 @@ static void at91_pio_mem_write(void *opaque, target_phys_addr_t offset, |
219 | 220 | qemu_set_irq(s->out[i], 1); |
220 | 221 | if(prev != s->odsr) |
221 | 222 | { |
222 | - printf("Pin %d set\n",i); | |
223 | + printf("Port %c%d set\n",'A' + s->portid, i); | |
223 | 224 | } |
224 | 225 | } |
225 | 226 | break; |
... | ... | @@ -232,7 +233,7 @@ static void at91_pio_mem_write(void *opaque, target_phys_addr_t offset, |
232 | 233 | qemu_set_irq(s->out[i], 0); |
233 | 234 | if(prev != s->odsr) |
234 | 235 | { |
235 | - printf("Pin %d reset\n",i); | |
236 | + printf("Port %c%d reset\n",'A' + s->portid, i); | |
236 | 237 | } |
237 | 238 | } |
238 | 239 | break; |
... | ... | @@ -355,6 +356,7 @@ static void at91_pio_init(SysBusDevice *dev) |
355 | 356 | { |
356 | 357 | DPRINTF("at91_pio_init called\n"); |
357 | 358 | PIOState *s = FROM_SYSBUS(typeof (*s), dev); |
359 | + s->portid = at91_io_cnt; | |
358 | 360 | at91_io_state[at91_io_cnt++] = s; |
359 | 361 | int pio_regs; |
360 | 362 | ... | ... |
virtual_lab/main.c
1 | 1 | #include <stdint.h> |
2 | 2 | #include <stdbool.h> |
3 | 3 | |
4 | +#define PA_PER (*((volatile uint32_t*)0xFFFFF200)) | |
5 | +#define PA_OER (*((volatile uint32_t*)0xFFFFF210)) | |
6 | +#define PA_SODR (*((volatile uint32_t*)0xFFFFF230)) | |
7 | +#define PA_CODR (*((volatile uint32_t*)0xFFFFF234)) | |
8 | +#define PA_PDSR (*((volatile uint32_t*)0xFFFFF23C)) | |
9 | + | |
10 | + | |
4 | 11 | #define PB_PER (*((volatile uint32_t*)0xFFFFF400)) |
5 | 12 | #define PB_OER (*((volatile uint32_t*)0xFFFFF410)) |
6 | 13 | #define PB_SODR (*((volatile uint32_t*)0xFFFFF430)) |
... | ... | @@ -33,13 +40,18 @@ void dbgu_print_ascii(){};; |
33 | 40 | |
34 | 41 | void delay(void) |
35 | 42 | { |
36 | - volatile uint32_t i; | |
37 | - for(i = 0; i < 1000000; i++); | |
43 | + volatile uint64_t i; | |
44 | + for(i = 0; i < 100000000; i++); | |
38 | 45 | } |
39 | 46 | |
40 | 47 | int main(void) |
41 | 48 | { |
42 | 49 | PMC_PCER = 1 << PER_ID_PBIOC_TO_PIOE; |
50 | + | |
51 | + PA_PER = 0x23; //PIO enable register | |
52 | + PA_OER = 0x54; //PIO controller output enable register | |
53 | + | |
54 | + | |
43 | 55 | PB_PER = DS1; //PIO enable register |
44 | 56 | PB_OER = DS1; //PIO controller output enable register |
45 | 57 | PC_PER = DS2 | BT1 | BT2; //PIO enable register |
... | ... | @@ -48,6 +60,7 @@ int main(void) |
48 | 60 | PC_PUER = BT1 | BT2; |
49 | 61 | while(true) |
50 | 62 | { |
63 | + delay(); | |
51 | 64 | /* |
52 | 65 | PB_SODR = DS1; |
53 | 66 | PC_CODR = DS2; | ... | ... |