Commit ac7e6319512e6ba971de0a78ae63590d5d62d3e6
1 parent
254a2710
Clean up messages from PIO
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1 changed file
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24 additions
and
9 deletions
hw/at91_pio.c
... | ... | @@ -26,6 +26,11 @@ |
26 | 26 | |
27 | 27 | #include "sysbus.h" |
28 | 28 | |
29 | +//#define DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) | |
30 | +#define DPRINTF(fmt, ...) do { } while (0) | |
31 | + | |
32 | + | |
33 | + | |
29 | 34 | /* |
30 | 35 | * Input/Output GPIO pins: |
31 | 36 | * 32x PIO device |
... | ... | @@ -88,7 +93,7 @@ typedef struct PIOState { |
88 | 93 | |
89 | 94 | void at91_pio_set_pin(void *opaque, int pin, int level) |
90 | 95 | { |
91 | - printf("In at91_pio_set_pin, opaque=%p, pin=%d, level=%d\n", opaque, pin, level); | |
96 | + DPRINTF("In at91_pio_set_pin, opaque=%p, pin=%d, level=%d\n", opaque, pin, level); | |
92 | 97 | PIOState *s = opaque; |
93 | 98 | int mask = 1 << (pin % PIO_PINS); |
94 | 99 | int input_set = pin / PIO_PINS; |
... | ... | @@ -98,7 +103,7 @@ void at91_pio_set_pin(void *opaque, int pin, int level) |
98 | 103 | if (input_set == 0) { |
99 | 104 | /* PIO pin -> Peripheral / IO */ |
100 | 105 | |
101 | - printf("In at91_pio_set_pin, s->osr=%08x, s->psr=%08x, mask=%08x\n",s->osr, s->psr, mask); | |
106 | + DPRINTF("In at91_pio_set_pin, s->osr=%08x, s->psr=%08x, mask=%08x\n",s->osr, s->psr, mask); | |
102 | 107 | |
103 | 108 | /* Skip input if output mode is enabled for the pin */ |
104 | 109 | if (s->osr & mask) |
... | ... | @@ -111,7 +116,7 @@ void at91_pio_set_pin(void *opaque, int pin, int level) |
111 | 116 | if (level == -1) { |
112 | 117 | s->unknown_state |= mask; |
113 | 118 | } else if (level) { |
114 | - printf("In at91_pio_set_pin, setting level\n"); | |
119 | + DPRINTF("In at91_pio_set_pin, setting level\n"); | |
115 | 120 | s->unknown_state &= ~mask; |
116 | 121 | s->pdsr |= mask; |
117 | 122 | } |
... | ... | @@ -122,7 +127,7 @@ void at91_pio_set_pin(void *opaque, int pin, int level) |
122 | 127 | } else { |
123 | 128 | qemu_set_irq(s->out[PIO_PINS + (output_set * PIO_PINS)], level); |
124 | 129 | } |
125 | - printf("In at91_pio_set_pin, s->pdsr=%08x\n",s->pdsr); | |
130 | + DPRINTF("In at91_pio_set_pin, s->pdsr=%08x\n",s->pdsr); | |
126 | 131 | |
127 | 132 | } else { |
128 | 133 | /* Peripheral -> PIO pin */ |
... | ... | @@ -148,7 +153,7 @@ static uint32_t at91_pio_mem_read(void *opaque, target_phys_addr_t offset) |
148 | 153 | case PIO_ODSR: |
149 | 154 | return s->odsr; |
150 | 155 | case PIO_PDSR: |
151 | - printf("In at91_pio_mem_read, reading PDSR, s->pdsr=%08x, s->unknown_state=%08x, retval=%08x\n", | |
156 | + DPRINTF("In at91_pio_mem_read, reading PDSR, s->pdsr=%08x, s->unknown_state=%08x, retval=%08x\n", | |
152 | 157 | s->pdsr, s->unknown_state, |
153 | 158 | (s->pdsr & ~s->unknown_state) | |
154 | 159 | (s->ppusr & s->unknown_state)); |
... | ... | @@ -181,9 +186,11 @@ static void at91_pio_mem_write(void *opaque, target_phys_addr_t offset, |
181 | 186 | PIOState *s = opaque; |
182 | 187 | int i; |
183 | 188 | |
184 | - printf("Writing PIO: offset=0x%08lx, value=0x%08x\n",offset,value); | |
189 | + DPRINTF("Writing PIO: offset=0x%08lx, value=0x%08x\n",offset,value); | |
185 | 190 | |
186 | 191 | offset &= PIO_SIZE - 1; |
192 | + | |
193 | + uint32_t prev; | |
187 | 194 | switch (offset) { |
188 | 195 | case PIO_PER: |
189 | 196 | s->psr |= value; |
... | ... | @@ -204,21 +211,29 @@ static void at91_pio_mem_write(void *opaque, target_phys_addr_t offset, |
204 | 211 | s->ifsr &= ~value; |
205 | 212 | break; |
206 | 213 | case PIO_SODR: |
214 | + prev = s->odsr; | |
207 | 215 | s->odsr |= value; |
208 | 216 | for (i = 0; i < PIO_PINS; i++) |
209 | 217 | if (value & (1 << i) & s->osr) |
210 | 218 | { |
211 | 219 | qemu_set_irq(s->out[i], 1); |
212 | - printf("Pin %d set\n",i); | |
220 | + if(prev != s->odsr) | |
221 | + { | |
222 | + printf("Pin %d set\n",i); | |
223 | + } | |
213 | 224 | } |
214 | 225 | break; |
215 | 226 | case PIO_CODR: |
227 | + prev = s->odsr; | |
216 | 228 | s->odsr &= ~value; |
217 | 229 | for (i = 0; i < PIO_PINS; i++) |
218 | 230 | if (value & (1 << i) & s->osr) |
219 | 231 | { |
220 | 232 | qemu_set_irq(s->out[i], 0); |
221 | - printf("Pin %d reset\n",i); | |
233 | + if(prev != s->odsr) | |
234 | + { | |
235 | + printf("Pin %d reset\n",i); | |
236 | + } | |
222 | 237 | } |
223 | 238 | break; |
224 | 239 | case PIO_ODSR: |
... | ... | @@ -338,7 +353,7 @@ int at91_io_cnt = 0; |
338 | 353 | |
339 | 354 | static void at91_pio_init(SysBusDevice *dev) |
340 | 355 | { |
341 | - printf("at91_pio_init called\n"); | |
356 | + DPRINTF("at91_pio_init called\n"); | |
342 | 357 | PIOState *s = FROM_SYSBUS(typeof (*s), dev); |
343 | 358 | at91_io_state[at91_io_cnt++] = s; |
344 | 359 | int pio_regs; | ... | ... |