gwj / at91sam9263 · Commits

Commit 963262debc52f771c99c2bf2605a63f60134410d

Authored by blueswir1
1 parent 8fa211e8

Better SuperSPARC emulation (Robert Reif) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6123 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 28 additions and 23 deletions
target-sparc/cpu.h
  View file @963262d
@@ -210,6 +210,7 @@ typedef struct sparc_def_t { @@ -210,6 +210,7 @@ typedef struct sparc_def_t {
210 uint32_t mmu_cxr_mask; 210 uint32_t mmu_cxr_mask;
211 uint32_t mmu_sfsr_mask; 211 uint32_t mmu_sfsr_mask;
212 uint32_t mmu_trcr_mask; 212 uint32_t mmu_trcr_mask;
  213 + uint32_t mxcc_version;
213 uint32_t features; 214 uint32_t features;
214 uint32_t nwindows; 215 uint32_t nwindows;
215 uint32_t maxtl; 216 uint32_t maxtl;
target-sparc/helper.c
  View file @963262d
@@ -688,6 +688,7 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) @@ -688,6 +688,7 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
688 #if !defined(TARGET_SPARC64) 688 #if !defined(TARGET_SPARC64)
689 env->mmuregs[0] |= def->mmu_version; 689 env->mmuregs[0] |= def->mmu_version;
690 cpu_sparc_set_id(env, 0); 690 cpu_sparc_set_id(env, 0);
  691 + env->mxccregs[7] |= def->mxcc_version;
691 #else 692 #else
692 env->mmu_version = def->mmu_version; 693 env->mmu_version = def->mmu_version;
693 env->maxtl = def->maxtl; 694 env->maxtl = def->maxtl;
@@ -972,19 +973,6 @@ static const sparc_def_t sparc_defs[] = { @@ -972,19 +973,6 @@ static const sparc_def_t sparc_defs[] = {
972 CPU_FEATURE_FSMULD, 973 CPU_FEATURE_FSMULD,
973 }, 974 },
974 { 975 {
975 - .name = "TI SuperSparc II",  
976 - .iu_version = 0x40000000,  
977 - .fpu_version = 0 << 17,  
978 - .mmu_version = 0x04000000,  
979 - .mmu_bm = 0x00002000,  
980 - .mmu_ctpr_mask = 0xffffffc0,  
981 - .mmu_cxr_mask = 0x0000ffff,  
982 - .mmu_sfsr_mask = 0xffffffff,  
983 - .mmu_trcr_mask = 0xffffffff,  
984 - .nwindows = 8,  
985 - .features = CPU_DEFAULT_FEATURES,  
986 - },  
987 - {  
988 .name = "TI MicroSparc I", 976 .name = "TI MicroSparc I",
989 .iu_version = 0x41000000, 977 .iu_version = 0x41000000,
990 .fpu_version = 4 << 17, 978 .fpu_version = 4 << 17,
@@ -1027,9 +1015,9 @@ static const sparc_def_t sparc_defs[] = { @@ -1027,9 +1015,9 @@ static const sparc_def_t sparc_defs[] = {
1027 }, 1015 },
1028 { 1016 {
1029 .name = "TI SuperSparc 40", // STP1020NPGA 1017 .name = "TI SuperSparc 40", // STP1020NPGA
1030 - .iu_version = 0x41000000, 1018 + .iu_version = 0x41000000, // SuperSPARC 2.x
1031 .fpu_version = 0 << 17, 1019 .fpu_version = 0 << 17,
1032 - .mmu_version = 0x00000000, 1020 + .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
1033 .mmu_bm = 0x00002000, 1021 .mmu_bm = 0x00002000,
1034 .mmu_ctpr_mask = 0xffffffc0, 1022 .mmu_ctpr_mask = 0xffffffc0,
1035 .mmu_cxr_mask = 0x0000ffff, 1023 .mmu_cxr_mask = 0x0000ffff,
@@ -1040,9 +1028,9 @@ static const sparc_def_t sparc_defs[] = { @@ -1040,9 +1028,9 @@ static const sparc_def_t sparc_defs[] = {
1040 }, 1028 },
1041 { 1029 {
1042 .name = "TI SuperSparc 50", // STP1020PGA 1030 .name = "TI SuperSparc 50", // STP1020PGA
1043 - .iu_version = 0x40000000, 1031 + .iu_version = 0x40000000, // SuperSPARC 3.x
1044 .fpu_version = 0 << 17, 1032 .fpu_version = 0 << 17,
1045 - .mmu_version = 0x04000000, 1033 + .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1046 .mmu_bm = 0x00002000, 1034 .mmu_bm = 0x00002000,
1047 .mmu_ctpr_mask = 0xffffffc0, 1035 .mmu_ctpr_mask = 0xffffffc0,
1048 .mmu_cxr_mask = 0x0000ffff, 1036 .mmu_cxr_mask = 0x0000ffff,
@@ -1053,22 +1041,23 @@ static const sparc_def_t sparc_defs[] = { @@ -1053,22 +1041,23 @@ static const sparc_def_t sparc_defs[] = {
1053 }, 1041 },
1054 { 1042 {
1055 .name = "TI SuperSparc 51", 1043 .name = "TI SuperSparc 51",
1056 - .iu_version = 0x43000000, 1044 + .iu_version = 0x40000000, // SuperSPARC 3.x
1057 .fpu_version = 0 << 17, 1045 .fpu_version = 0 << 17,
1058 - .mmu_version = 0x04000000, 1046 + .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1059 .mmu_bm = 0x00002000, 1047 .mmu_bm = 0x00002000,
1060 .mmu_ctpr_mask = 0xffffffc0, 1048 .mmu_ctpr_mask = 0xffffffc0,
1061 .mmu_cxr_mask = 0x0000ffff, 1049 .mmu_cxr_mask = 0x0000ffff,
1062 .mmu_sfsr_mask = 0xffffffff, 1050 .mmu_sfsr_mask = 0xffffffff,
1063 .mmu_trcr_mask = 0xffffffff, 1051 .mmu_trcr_mask = 0xffffffff,
  1052 + .mxcc_version = 0x00000104,
1064 .nwindows = 8, 1053 .nwindows = 8,
1065 .features = CPU_DEFAULT_FEATURES, 1054 .features = CPU_DEFAULT_FEATURES,
1066 }, 1055 },
1067 { 1056 {
1068 .name = "TI SuperSparc 60", // STP1020APGA 1057 .name = "TI SuperSparc 60", // STP1020APGA
1069 - .iu_version = 0x40000000, 1058 + .iu_version = 0x40000000, // SuperSPARC 3.x
1070 .fpu_version = 0 << 17, 1059 .fpu_version = 0 << 17,
1071 - .mmu_version = 0x03000000, 1060 + .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1072 .mmu_bm = 0x00002000, 1061 .mmu_bm = 0x00002000,
1073 .mmu_ctpr_mask = 0xffffffc0, 1062 .mmu_ctpr_mask = 0xffffffc0,
1074 .mmu_cxr_mask = 0x0000ffff, 1063 .mmu_cxr_mask = 0x0000ffff,
@@ -1079,14 +1068,29 @@ static const sparc_def_t sparc_defs[] = { @@ -1079,14 +1068,29 @@ static const sparc_def_t sparc_defs[] = {
1079 }, 1068 },
1080 { 1069 {
1081 .name = "TI SuperSparc 61", 1070 .name = "TI SuperSparc 61",
1082 - .iu_version = 0x44000000, 1071 + .iu_version = 0x44000000, // SuperSPARC 3.x
1083 .fpu_version = 0 << 17, 1072 .fpu_version = 0 << 17,
1084 - .mmu_version = 0x04000000, 1073 + .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
  1074 + .mmu_bm = 0x00002000,
  1075 + .mmu_ctpr_mask = 0xffffffc0,
  1076 + .mmu_cxr_mask = 0x0000ffff,
  1077 + .mmu_sfsr_mask = 0xffffffff,
  1078 + .mmu_trcr_mask = 0xffffffff,
  1079 + .mxcc_version = 0x00000104,
  1080 + .nwindows = 8,
  1081 + .features = CPU_DEFAULT_FEATURES,
  1082 + },
  1083 + {
  1084 + .name = "TI SuperSparc II",
  1085 + .iu_version = 0x40000000, // SuperSPARC II 1.x
  1086 + .fpu_version = 0 << 17,
  1087 + .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
1085 .mmu_bm = 0x00002000, 1088 .mmu_bm = 0x00002000,
1086 .mmu_ctpr_mask = 0xffffffc0, 1089 .mmu_ctpr_mask = 0xffffffc0,
1087 .mmu_cxr_mask = 0x0000ffff, 1090 .mmu_cxr_mask = 0x0000ffff,
1088 .mmu_sfsr_mask = 0xffffffff, 1091 .mmu_sfsr_mask = 0xffffffff,
1089 .mmu_trcr_mask = 0xffffffff, 1092 .mmu_trcr_mask = 0xffffffff,
  1093 + .mxcc_version = 0x00000104,
1090 .nwindows = 8, 1094 .nwindows = 8,
1091 .features = CPU_DEFAULT_FEATURES, 1095 .features = CPU_DEFAULT_FEATURES,
1092 }, 1096 },