Commit 8fa211e881ff386f8555c113b409aa3373dca7e1
1 parent
69dd5c9f
Implement tick interrupt disable bits
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6122 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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22 additions
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10 deletions
hw/sun4u.c
| ... | ... | @@ -57,6 +57,9 @@ |
| 57 | 57 | |
| 58 | 58 | #define MAX_PILS 16 |
| 59 | 59 | |
| 60 | +#define TICK_INT_DIS 0x8000000000000000ULL | |
| 61 | +#define TICK_MAX 0x7fffffffffffffffULL | |
| 62 | + | |
| 60 | 63 | struct hwdef { |
| 61 | 64 | const char * const default_cpu_model; |
| 62 | 65 | uint16_t machine_id; |
| ... | ... | @@ -269,11 +272,14 @@ static void main_cpu_reset(void *opaque) |
| 269 | 272 | CPUState *env = s->env; |
| 270 | 273 | |
| 271 | 274 | cpu_reset(env); |
| 272 | - ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); | |
| 275 | + env->tick_cmpr = TICK_INT_DIS | 0; | |
| 276 | + ptimer_set_limit(env->tick, TICK_MAX, 1); | |
| 273 | 277 | ptimer_run(env->tick, 0); |
| 274 | - ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); | |
| 278 | + env->stick_cmpr = TICK_INT_DIS | 0; | |
| 279 | + ptimer_set_limit(env->stick, TICK_MAX, 1); | |
| 275 | 280 | ptimer_run(env->stick, 0); |
| 276 | - ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); | |
| 281 | + env->hstick_cmpr = TICK_INT_DIS | 0; | |
| 282 | + ptimer_set_limit(env->hstick, TICK_MAX, 1); | |
| 277 | 283 | ptimer_run(env->hstick, 0); |
| 278 | 284 | env->gregs[1] = 0; // Memory start |
| 279 | 285 | env->gregs[2] = ram_size; // Memory size |
| ... | ... | @@ -286,24 +292,29 @@ static void tick_irq(void *opaque) |
| 286 | 292 | { |
| 287 | 293 | CPUState *env = opaque; |
| 288 | 294 | |
| 289 | - env->softint |= SOFTINT_TIMER; | |
| 290 | - cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
| 295 | + if (!(env->tick_cmpr & TICK_INT_DIS)) { | |
| 296 | + env->softint |= SOFTINT_TIMER; | |
| 297 | + cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
| 298 | + } | |
| 291 | 299 | } |
| 292 | 300 | |
| 293 | 301 | static void stick_irq(void *opaque) |
| 294 | 302 | { |
| 295 | 303 | CPUState *env = opaque; |
| 296 | 304 | |
| 297 | - env->softint |= SOFTINT_TIMER; | |
| 298 | - cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
| 305 | + if (!(env->stick_cmpr & TICK_INT_DIS)) { | |
| 306 | + env->softint |= SOFTINT_STIMER; | |
| 307 | + cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
| 308 | + } | |
| 299 | 309 | } |
| 300 | 310 | |
| 301 | 311 | static void hstick_irq(void *opaque) |
| 302 | 312 | { |
| 303 | 313 | CPUState *env = opaque; |
| 304 | 314 | |
| 305 | - env->softint |= SOFTINT_TIMER; | |
| 306 | - cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
| 315 | + if (!(env->hstick_cmpr & TICK_INT_DIS)) { | |
| 316 | + cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
| 317 | + } | |
| 307 | 318 | } |
| 308 | 319 | |
| 309 | 320 | void cpu_tick_set_count(void *opaque, uint64_t count) | ... | ... |
target-sparc/cpu.h
| ... | ... | @@ -330,7 +330,8 @@ typedef struct CPUSPARCState { |
| 330 | 330 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
| 331 | 331 | void *hstick; // UA 2005 |
| 332 | 332 | uint32_t softint; |
| 333 | -#define SOFTINT_TIMER 1 | |
| 333 | +#define SOFTINT_TIMER 1 | |
| 334 | +#define SOFTINT_STIMER (1 << 16) | |
| 334 | 335 | #endif |
| 335 | 336 | sparc_def_t *def; |
| 336 | 337 | } CPUSPARCState; | ... | ... |