gwj / at91sam9263 · Commits

Commit 8bb6e981e09c914783c0a7d43c711de4e4f36ad4

Authored by aurel32
1 parent f4ed8679

target-alpha: convert palcode ops to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 9 changed files with 349 additions and 536 deletions
configure
  View file @8bb6e98
... ... @@ -1425,10 +1425,8 @@ case &quot;$target_cpu&quot; in
1425 1425 ;;
1426 1426 alpha)
1427 1427 echo "TARGET_ARCH=alpha" >> $config_mak
1428   - echo "CONFIG_DYNGEN_OP=yes" >> $config_mak
1429 1428 echo "#define TARGET_ARCH \"alpha\"" >> $config_h
1430 1429 echo "#define TARGET_ALPHA 1" >> $config_h
1431   - echo "#define CONFIG_DYNGEN_OP 1" >> $config_h
1432 1430 ;;
1433 1431 arm|armeb)
1434 1432 echo "TARGET_ARCH=arm" >> $config_mak
... ...
target-alpha/exec.h
  View file @8bb6e98
... ... @@ -29,29 +29,10 @@
29 29  
30 30 register struct CPUAlphaState *env asm(AREG0);
31 31  
32   -#if TARGET_LONG_BITS > HOST_LONG_BITS
33   -
34   -/* no registers can be used */
35   -#define T0 (env->t0)
36   -#define T1 (env->t1)
37   -
38   -#else
39   -
40   -register uint64_t T0 asm(AREG1);
41   -register uint64_t T1 asm(AREG2);
42   -
43   -#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
44   -
45 32 #define PARAM(n) ((uint64_t)PARAM##n)
46 33 #define SPARAM(n) ((int32_t)PARAM##n)
47 34 #define FP_STATUS (env->fp_status)
48 35  
49   -#if defined (DEBUG_OP)
50   -#define RETURN() __asm__ __volatile__("nop" : : : "memory");
51   -#else
52   -#define RETURN() __asm__ __volatile__("" : : : "memory");
53   -#endif
54   -
55 36 #include "cpu.h"
56 37 #include "exec-all.h"
57 38  
... ...
target-alpha/helper.c
  View file @8bb6e98
... ... @@ -436,13 +436,3 @@ void cpu_dump_state (CPUState *env, FILE *f,
436 436 }
437 437 }
438 438  
439   -void cpu_dump_EA (target_ulong EA)
440   -{
441   - FILE *f;
442   -
443   - if (logfile)
444   - f = logfile;
445   - else
446   - f = stdout;
447   - fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
448   -}
... ...
target-alpha/helper.h
  View file @8bb6e98
... ... @@ -108,3 +108,26 @@ DEF_HELPER(uint64_t, helper_cvtql, (uint64_t))
108 108 DEF_HELPER(uint64_t, helper_cvtqlv, (uint64_t))
109 109 DEF_HELPER(uint64_t, helper_cvtqlsv, (uint64_t))
110 110  
  111 +#if !defined (CONFIG_USER_ONLY)
  112 +DEF_HELPER(void, helper_hw_rei, (void))
  113 +DEF_HELPER(void, helper_hw_ret, (uint64_t))
  114 +DEF_HELPER(uint64_t, helper_mfpr, (int, uint64_t))
  115 +DEF_HELPER(void, helper_mtpr, (int, uint64_t))
  116 +DEF_HELPER(void, helper_set_alt_mode, (void))
  117 +DEF_HELPER(void, helper_restore_mode, (void))
  118 +
  119 +DEF_HELPER(uint64_t, helper_ld_virt_to_phys, (uint64_t))
  120 +DEF_HELPER(uint64_t, helper_st_virt_to_phys, (uint64_t))
  121 +DEF_HELPER(void, helper_ldl_raw, (uint64_t, uint64_t))
  122 +DEF_HELPER(void, helper_ldq_raw, (uint64_t, uint64_t))
  123 +DEF_HELPER(void, helper_ldl_l_raw, (uint64_t, uint64_t))
  124 +DEF_HELPER(void, helper_ldq_l_raw, (uint64_t, uint64_t))
  125 +DEF_HELPER(void, helper_ldl_kernel, (uint64_t, uint64_t))
  126 +DEF_HELPER(void, helper_ldq_kernel, (uint64_t, uint64_t))
  127 +DEF_HELPER(void, helper_ldl_data, (uint64_t, uint64_t))
  128 +DEF_HELPER(void, helper_ldq_data, (uint64_t, uint64_t))
  129 +DEF_HELPER(void, helper_stl_raw, (uint64_t, uint64_t))
  130 +DEF_HELPER(void, helper_stq_raw, (uint64_t, uint64_t))
  131 +DEF_HELPER(uint64_t, helper_stl_c_raw, (uint64_t, uint64_t))
  132 +DEF_HELPER(uint64_t, helper_stq_c_raw, (uint64_t, uint64_t))
  133 +#endif
... ...
target-alpha/op.c deleted 100644 → 0
  View file @f4ed867
1   -/*
2   - * Alpha emulation cpu micro-operations for qemu.
3   - *
4   - * Copyright (c) 2007 Jocelyn Mayer
5   - *
6   - * This library is free software; you can redistribute it and/or
7   - * modify it under the terms of the GNU Lesser General Public
8   - * License as published by the Free Software Foundation; either
9   - * version 2 of the License, or (at your option) any later version.
10   - *
11   - * This library is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14   - * Lesser General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU Lesser General Public
17   - * License along with this library; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19   - */
20   -
21   -#define DEBUG_OP
22   -
23   -#include "config.h"
24   -#include "exec.h"
25   -#include "host-utils.h"
26   -#include "op_helper.h"
27   -
28   -/* Load and stores */
29   -#define MEMSUFFIX _raw
30   -#include "op_mem.h"
31   -#if !defined(CONFIG_USER_ONLY)
32   -#define MEMSUFFIX _kernel
33   -#include "op_mem.h"
34   -#define MEMSUFFIX _executive
35   -#include "op_mem.h"
36   -#define MEMSUFFIX _supervisor
37   -#include "op_mem.h"
38   -#define MEMSUFFIX _user
39   -#include "op_mem.h"
40   -/* This is used for pal modes */
41   -#define MEMSUFFIX _data
42   -#include "op_mem.h"
43   -#endif
44   -
45   -/* PALcode support special instructions */
46   -#if !defined (CONFIG_USER_ONLY)
47   -void OPPROTO op_hw_rei (void)
48   -{
49   - env->pc = env->ipr[IPR_EXC_ADDR] & ~3;
50   - env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
51   - /* XXX: re-enable interrupts and memory mapping */
52   - RETURN();
53   -}
54   -
55   -void OPPROTO op_hw_ret (void)
56   -{
57   - env->pc = T0 & ~3;
58   - env->ipr[IPR_EXC_ADDR] = T0 & 1;
59   - /* XXX: re-enable interrupts and memory mapping */
60   - RETURN();
61   -}
62   -
63   -void OPPROTO op_mfpr (void)
64   -{
65   - helper_mfpr(PARAM(1));
66   - RETURN();
67   -}
68   -
69   -void OPPROTO op_mtpr (void)
70   -{
71   - helper_mtpr(PARAM(1));
72   - RETURN();
73   -}
74   -
75   -void OPPROTO op_set_alt_mode (void)
76   -{
77   - env->saved_mode = env->ps & 0xC;
78   - env->ps = (env->ps & ~0xC) | (env->ipr[IPR_ALT_MODE] & 0xC);
79   - RETURN();
80   -}
81   -
82   -void OPPROTO op_restore_mode (void)
83   -{
84   - env->ps = (env->ps & ~0xC) | env->saved_mode;
85   - RETURN();
86   -}
87   -
88   -void OPPROTO op_ld_phys_to_virt (void)
89   -{
90   - helper_ld_phys_to_virt();
91   - RETURN();
92   -}
93   -
94   -void OPPROTO op_st_phys_to_virt (void)
95   -{
96   - helper_st_phys_to_virt();
97   - RETURN();
98   -}
99   -#endif /* !defined (CONFIG_USER_ONLY) */
target-alpha/op_helper.c
  View file @8bb6e98
... ... @@ -22,19 +22,11 @@
22 22 #include "host-utils.h"
23 23 #include "softfloat.h"
24 24  
25   -#include "op_helper.h"
26   -
27 25 void helper_tb_flush (void)
28 26 {
29 27 tlb_flush(env, 1);
30 28 }
31 29  
32   -void cpu_dump_EA (target_ulong EA);
33   -void helper_print_mem_EA (target_ulong EA)
34   -{
35   - cpu_dump_EA(EA);
36   -}
37   -
38 30 /*****************************************************************************/
39 31 /* Exceptions processing helpers */
40 32 void helper_excp (int excp, int error)
... ... @@ -990,19 +982,48 @@ uint64_t helper_cvtqlsv (uint64_t a)
990 982 return __helper_cvtql(a, 1, 1);
991 983 }
992 984  
  985 +/* PALcode support special instructions */
993 986 #if !defined (CONFIG_USER_ONLY)
994   -void helper_mfpr (int iprn)
  987 +void helper_hw_rei (void)
  988 +{
  989 + env->pc = env->ipr[IPR_EXC_ADDR] & ~3;
  990 + env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
  991 + /* XXX: re-enable interrupts and memory mapping */
  992 +}
  993 +
  994 +void helper_hw_ret (uint64_t a)
  995 +{
  996 + env->pc = a & ~3;
  997 + env->ipr[IPR_EXC_ADDR] = a & 1;
  998 + /* XXX: re-enable interrupts and memory mapping */
  999 +}
  1000 +
  1001 +uint64_t helper_mfpr (int iprn, uint64_t val)
  1002 +{
  1003 + uint64_t tmp;
  1004 +
  1005 + if (cpu_alpha_mfpr(env, iprn, &tmp) == 0)
  1006 + val = tmp;
  1007 +
  1008 + return val;
  1009 +}
  1010 +
  1011 +void helper_mtpr (int iprn, uint64_t val)
995 1012 {
996   - uint64_t val;
  1013 + cpu_alpha_mtpr(env, iprn, val, NULL);
  1014 +}
997 1015  
998   - if (cpu_alpha_mfpr(env, iprn, &val) == 0)
999   - T0 = val;
  1016 +void helper_set_alt_mode (void)
  1017 +{
  1018 + env->saved_mode = env->ps & 0xC;
  1019 + env->ps = (env->ps & ~0xC) | (env->ipr[IPR_ALT_MODE] & 0xC);
1000 1020 }
1001 1021  
1002   -void helper_mtpr (int iprn)
  1022 +void helper_restore_mode (void)
1003 1023 {
1004   - cpu_alpha_mtpr(env, iprn, T0, NULL);
  1024 + env->ps = (env->ps & ~0xC) | env->saved_mode;
1005 1025 }
  1026 +
1006 1027 #endif
1007 1028  
1008 1029 /*****************************************************************************/
... ... @@ -1013,48 +1034,130 @@ void helper_mtpr (int iprn)
1013 1034 * Hopefully, we emulate the PALcode, then we should never see
1014 1035 * HW_LD / HW_ST instructions.
1015 1036 */
1016   -void helper_ld_phys_to_virt (void)
  1037 +uint64_t helper_ld_virt_to_phys (uint64_t virtaddr)
1017 1038 {
1018 1039 uint64_t tlb_addr, physaddr;
1019 1040 int index, mmu_idx;
1020 1041 void *retaddr;
1021 1042  
1022 1043 mmu_idx = cpu_mmu_index(env);
1023   - index = (T0 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
  1044 + index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1024 1045 redo:
1025 1046 tlb_addr = env->tlb_table[mmu_idx][index].addr_read;
1026   - if ((T0 & TARGET_PAGE_MASK) ==
  1047 + if ((virtaddr & TARGET_PAGE_MASK) ==
1027 1048 (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1028   - physaddr = T0 + env->tlb_table[mmu_idx][index].addend;
  1049 + physaddr = virtaddr + env->tlb_table[mmu_idx][index].addend;
1029 1050 } else {
1030 1051 /* the page is not in the TLB : fill it */
1031 1052 retaddr = GETPC();
1032   - tlb_fill(T0, 0, mmu_idx, retaddr);
  1053 + tlb_fill(virtaddr, 0, mmu_idx, retaddr);
1033 1054 goto redo;
1034 1055 }
1035   - T0 = physaddr;
  1056 + return physaddr;
1036 1057 }
1037 1058  
1038   -void helper_st_phys_to_virt (void)
  1059 +uint64_t helper_st_virt_to_phys (uint64_t virtaddr)
1039 1060 {
1040 1061 uint64_t tlb_addr, physaddr;
1041 1062 int index, mmu_idx;
1042 1063 void *retaddr;
1043 1064  
1044 1065 mmu_idx = cpu_mmu_index(env);
1045   - index = (T0 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
  1066 + index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1046 1067 redo:
1047 1068 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
1048   - if ((T0 & TARGET_PAGE_MASK) ==
  1069 + if ((virtaddr & TARGET_PAGE_MASK) ==
1049 1070 (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1050   - physaddr = T0 + env->tlb_table[mmu_idx][index].addend;
  1071 + physaddr = virtaddr + env->tlb_table[mmu_idx][index].addend;
1051 1072 } else {
1052 1073 /* the page is not in the TLB : fill it */
1053 1074 retaddr = GETPC();
1054   - tlb_fill(T0, 1, mmu_idx, retaddr);
  1075 + tlb_fill(virtaddr, 1, mmu_idx, retaddr);
1055 1076 goto redo;
1056 1077 }
1057   - T0 = physaddr;
  1078 + return physaddr;
  1079 +}
  1080 +
  1081 +void helper_ldl_raw(uint64_t t0, uint64_t t1)
  1082 +{
  1083 + ldl_raw(t1, t0);
  1084 +}
  1085 +
  1086 +void helper_ldq_raw(uint64_t t0, uint64_t t1)
  1087 +{
  1088 + ldq_raw(t1, t0);
  1089 +}
  1090 +
  1091 +void helper_ldl_l_raw(uint64_t t0, uint64_t t1)
  1092 +{
  1093 + env->lock = t1;
  1094 + ldl_raw(t1, t0);
  1095 +}
  1096 +
  1097 +void helper_ldq_l_raw(uint64_t t0, uint64_t t1)
  1098 +{
  1099 + env->lock = t1;
  1100 + ldl_raw(t1, t0);
  1101 +}
  1102 +
  1103 +void helper_ldl_kernel(uint64_t t0, uint64_t t1)
  1104 +{
  1105 + ldl_kernel(t1, t0);
  1106 +}
  1107 +
  1108 +void helper_ldq_kernel(uint64_t t0, uint64_t t1)
  1109 +{
  1110 + ldq_kernel(t1, t0);
  1111 +}
  1112 +
  1113 +void helper_ldl_data(uint64_t t0, uint64_t t1)
  1114 +{
  1115 + ldl_data(t1, t0);
  1116 +}
  1117 +
  1118 +void helper_ldq_data(uint64_t t0, uint64_t t1)
  1119 +{
  1120 + ldq_data(t1, t0);
  1121 +}
  1122 +
  1123 +void helper_stl_raw(uint64_t t0, uint64_t t1)
  1124 +{
  1125 + stl_raw(t1, t0);
  1126 +}
  1127 +
  1128 +void helper_stq_raw(uint64_t t0, uint64_t t1)
  1129 +{
  1130 + stq_raw(t1, t0);
  1131 +}
  1132 +
  1133 +uint64_t helper_stl_c_raw(uint64_t t0, uint64_t t1)
  1134 +{
  1135 + uint64_t ret;
  1136 +
  1137 + if (t1 == env->lock) {
  1138 + stl_raw(t1, t0);
  1139 + ret = 0;
  1140 + } else
  1141 + ret = 1;
  1142 +
  1143 + env->lock = 1;
  1144 +
  1145 + return ret;
  1146 +}
  1147 +
  1148 +uint64_t helper_stq_c_raw(uint64_t t0, uint64_t t1)
  1149 +{
  1150 + uint64_t ret;
  1151 +
  1152 + if (t1 == env->lock) {
  1153 + stq_raw(t1, t0);
  1154 + ret = 0;
  1155 + } else
  1156 + ret = 1;
  1157 +
  1158 + env->lock = 1;
  1159 +
  1160 + return ret;
1058 1161 }
1059 1162  
1060 1163 #define MMUSUFFIX _mmu
... ...
target-alpha/op_helper.h deleted 100644 → 0
  View file @f4ed867
1   -/*
2   - * Alpha emulation cpu micro-operations helpers definitions for qemu.
3   - *
4   - * Copyright (c) 2007 Jocelyn Mayer
5   - *
6   - * This library is free software; you can redistribute it and/or
7   - * modify it under the terms of the GNU Lesser General Public
8   - * License as published by the Free Software Foundation; either
9   - * version 2 of the License, or (at your option) any later version.
10   - *
11   - * This library is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14   - * Lesser General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU Lesser General Public
17   - * License along with this library; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19   - */
20   -
21   -void helper_call_pal (uint32_t palcode);
22   -
23   -double helper_ldff_raw (target_ulong ea);
24   -void helper_stff_raw (target_ulong ea, double op);
25   -double helper_ldfg_raw (target_ulong ea);
26   -void helper_stfg_raw (target_ulong ea, double op);
27   -#if !defined(CONFIG_USER_ONLY)
28   -double helper_ldff_user (target_ulong ea);
29   -void helper_stff_user (target_ulong ea, double op);
30   -double helper_ldff_kernel (target_ulong ea);
31   -void helper_stff_kernel (target_ulong ea, double op);
32   -double helper_ldff_data (target_ulong ea);
33   -void helper_stff_data (target_ulong ea, double op);
34   -double helper_ldfg_user (target_ulong ea);
35   -void helper_stfg_user (target_ulong ea, double op);
36   -double helper_ldfg_kernel (target_ulong ea);
37   -void helper_stfg_kernel (target_ulong ea, double op);
38   -double helper_ldfg_data (target_ulong ea);
39   -void helper_stfg_data (target_ulong ea, double op);
40   -#endif
41   -
42   -void helper_mfpr (int iprn);
43   -void helper_mtpr (int iprn);
44   -void helper_ld_phys_to_virt (void);
45   -void helper_st_phys_to_virt (void);
46   -
target-alpha/op_mem.h deleted 100644 → 0
  View file @f4ed867
1   -/*
2   - * Alpha emulation cpu micro-operations for memory accesses for qemu.
3   - *
4   - * Copyright (c) 2007 Jocelyn Mayer
5   - *
6   - * This library is free software; you can redistribute it and/or
7   - * modify it under the terms of the GNU Lesser General Public
8   - * License as published by the Free Software Foundation; either
9   - * version 2 of the License, or (at your option) any later version.
10   - *
11   - * This library is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14   - * Lesser General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU Lesser General Public
17   - * License along with this library; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19   - */
20   -
21   -//#define DEBUG_MEM_ACCESSES
22   -#if defined (DEBUG_MEM_ACCESSES)
23   -void helper_print_mem_EA (target_ulong EA);
24   -#define print_mem_EA(EA) do { helper_print_mem_EA(EA); } while (0)
25   -#else
26   -#define print_mem_EA(EA) do { } while (0)
27   -#endif
28   -
29   -static always_inline uint32_t glue(ldl_l, MEMSUFFIX) (target_ulong EA)
30   -{
31   - env->lock = EA;
32   -
33   - return glue(ldl, MEMSUFFIX)(EA);
34   -}
35   -
36   -static always_inline uint32_t glue(ldq_l, MEMSUFFIX) (target_ulong EA)
37   -{
38   - env->lock = EA;
39   -
40   - return glue(ldq, MEMSUFFIX)(EA);
41   -}
42   -
43   -static always_inline void glue(stl_c, MEMSUFFIX) (target_ulong EA,
44   - uint32_t data)
45   -{
46   - if (EA == env->lock) {
47   - glue(stl, MEMSUFFIX)(EA, data);
48   - T0 = 0;
49   - } else {
50   - T0 = 1;
51   - }
52   - env->lock = -1;
53   -}
54   -
55   -static always_inline void glue(stq_c, MEMSUFFIX) (target_ulong EA,
56   - uint64_t data)
57   -{
58   - if (EA == env->lock) {
59   - glue(stq, MEMSUFFIX)(EA, data);
60   - T0 = 0;
61   - } else {
62   - T0 = 1;
63   - }
64   - env->lock = -1;
65   -}
66   -
67   -#define ALPHA_LD_OP(name, op) \
68   -void OPPROTO glue(glue(op_ld, name), MEMSUFFIX) (void) \
69   -{ \
70   - print_mem_EA(T0); \
71   - T1 = glue(op, MEMSUFFIX)(T0); \
72   - RETURN(); \
73   -}
74   -
75   -#define ALPHA_ST_OP(name, op) \
76   -void OPPROTO glue(glue(op_st, name), MEMSUFFIX) (void) \
77   -{ \
78   - print_mem_EA(T0); \
79   - glue(op, MEMSUFFIX)(T0, T1); \
80   - RETURN(); \
81   -}
82   -
83   -ALPHA_LD_OP(l, ldl);
84   -ALPHA_ST_OP(l, stl);
85   -ALPHA_LD_OP(q, ldq);
86   -ALPHA_ST_OP(q, stq);
87   -
88   -ALPHA_LD_OP(l_l, ldl_l);
89   -ALPHA_LD_OP(q_l, ldq_l);
90   -ALPHA_ST_OP(l_c, stl_c);
91   -ALPHA_ST_OP(q_c, stq_c);
92   -
93   -#undef MEMSUFFIX
target-alpha/translate.c
  View file @8bb6e98
... ... @@ -51,9 +51,6 @@ static TCGv cpu_fir[31];
51 51 static TCGv cpu_pc;
52 52 static TCGv cpu_lock;
53 53  
54   -/* dyngen register indexes */
55   -static TCGv cpu_T[2];
56   -
57 54 /* register names */
58 55 static char cpu_reg_names[10*4+21*5 + 10*5+21*6];
59 56  
... ... @@ -70,16 +67,6 @@ static void alpha_translate_init(void)
70 67  
71 68 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
72 69  
73   -#if TARGET_LONG_BITS > HOST_LONG_BITS
74   - cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
75   - offsetof(CPUState, t0), "T0");
76   - cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
77   - offsetof(CPUState, t1), "T1");
78   -#else
79   - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
80   - cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
81   -#endif
82   -
83 70 p = cpu_reg_names;
84 71 for (i = 0; i < 31; i++) {
85 72 sprintf(p, "ir%d", i);
... ... @@ -107,56 +94,6 @@ static void alpha_translate_init(void)
107 94 done_init = 1;
108 95 }
109 96  
110   -/* Memory moves */
111   -#if defined(CONFIG_USER_ONLY)
112   -#define OP_LD_TABLE(width) \
113   -static GenOpFunc *gen_op_ld##width[] = { \
114   - &gen_op_ld##width##_raw, \
115   -}
116   -#define OP_ST_TABLE(width) \
117   -static GenOpFunc *gen_op_st##width[] = { \
118   - &gen_op_st##width##_raw, \
119   -}
120   -#else
121   -#define OP_LD_TABLE(width) \
122   -static GenOpFunc *gen_op_ld##width[] = { \
123   - &gen_op_ld##width##_kernel, \
124   - &gen_op_ld##width##_executive, \
125   - &gen_op_ld##width##_supervisor, \
126   - &gen_op_ld##width##_user, \
127   -}
128   -#define OP_ST_TABLE(width) \
129   -static GenOpFunc *gen_op_st##width[] = { \
130   - &gen_op_st##width##_kernel, \
131   - &gen_op_st##width##_executive, \
132   - &gen_op_st##width##_supervisor, \
133   - &gen_op_st##width##_user, \
134   -}
135   -#endif
136   -
137   -#define GEN_LD(width) \
138   -OP_LD_TABLE(width); \
139   -static always_inline void gen_ld##width (DisasContext *ctx) \
140   -{ \
141   - (*gen_op_ld##width[ctx->mem_idx])(); \
142   -}
143   -
144   -#define GEN_ST(width) \
145   -OP_ST_TABLE(width); \
146   -static always_inline void gen_st##width (DisasContext *ctx) \
147   -{ \
148   - (*gen_op_st##width[ctx->mem_idx])(); \
149   -}
150   -
151   -GEN_LD(l);
152   -GEN_ST(l);
153   -GEN_LD(q);
154   -GEN_ST(q);
155   -GEN_LD(l_l);
156   -GEN_ST(l_c);
157   -GEN_LD(q_l);
158   -GEN_ST(q_c);
159   -
160 97 static always_inline void gen_excp (DisasContext *ctx,
161 98 int exception, int error_code)
162 99 {
... ... @@ -1027,7 +964,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
1027 964 if (ra != 31) {
1028 965 if (islit)
1029 966 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1030   - else
  967 + else
1031 968 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1032 969 } else {
1033 970 if (islit)
... ... @@ -1701,9 +1638,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
1701 1638 #else
1702 1639 if (!ctx->pal_mode)
1703 1640 goto invalid_opc;
1704   - gen_op_mfpr(insn & 0xFF);
1705   - if (ra != 31)
1706   - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
  1641 + if (ra != 31) {
  1642 + TCGv tmp = tcg_const_i32(insn & 0xFF);
  1643 + tcg_gen_helper_1_2(helper_mfpr, cpu_ir[ra], tmp, cpu_ir[ra]);
  1644 + tcg_temp_free(tmp);
  1645 + }
1707 1646 break;
1708 1647 #endif
1709 1648 case 0x1A:
... ... @@ -1737,94 +1676,94 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
1737 1676 #else
1738 1677 if (!ctx->pal_mode)
1739 1678 goto invalid_opc;
1740   - if (rb != 31)
1741   - tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1742   - else
1743   - tcg_gen_movi_i64(cpu_T[0], 0);
1744   - tcg_gen_movi_i64(cpu_T[1], disp12);
1745   - tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1746   - switch ((insn >> 12) & 0xF) {
1747   - case 0x0:
1748   - /* Longword physical access */
1749   - gen_op_ldl_raw();
1750   - break;
1751   - case 0x1:
1752   - /* Quadword physical access */
1753   - gen_op_ldq_raw();
1754   - break;
1755   - case 0x2:
1756   - /* Longword physical access with lock */
1757   - gen_op_ldl_l_raw();
1758   - break;
1759   - case 0x3:
1760   - /* Quadword physical access with lock */
1761   - gen_op_ldq_l_raw();
1762   - break;
1763   - case 0x4:
1764   - /* Longword virtual PTE fetch */
1765   - gen_op_ldl_kernel();
1766   - break;
1767   - case 0x5:
1768   - /* Quadword virtual PTE fetch */
1769   - gen_op_ldq_kernel();
1770   - break;
1771   - case 0x6:
1772   - /* Invalid */
1773   - goto invalid_opc;
1774   - case 0x7:
1775   - /* Invalid */
1776   - goto invalid_opc;
1777   - case 0x8:
1778   - /* Longword virtual access */
1779   - gen_op_ld_phys_to_virt();
1780   - gen_op_ldl_raw();
1781   - break;
1782   - case 0x9:
1783   - /* Quadword virtual access */
1784   - gen_op_ld_phys_to_virt();
1785   - gen_op_ldq_raw();
1786   - break;
1787   - case 0xA:
1788   - /* Longword virtual access with protection check */
1789   - gen_ldl(ctx);
1790   - break;
1791   - case 0xB:
1792   - /* Quadword virtual access with protection check */
1793   - gen_ldq(ctx);
1794   - break;
1795   - case 0xC:
1796   - /* Longword virtual access with altenate access mode */
1797   - gen_op_set_alt_mode();
1798   - gen_op_ld_phys_to_virt();
1799   - gen_op_ldl_raw();
1800   - gen_op_restore_mode();
1801   - break;
1802   - case 0xD:
1803   - /* Quadword virtual access with altenate access mode */
1804   - gen_op_set_alt_mode();
1805   - gen_op_ld_phys_to_virt();
1806   - gen_op_ldq_raw();
1807   - gen_op_restore_mode();
1808   - break;
1809   - case 0xE:
1810   - /* Longword virtual access with alternate access mode and
1811   - * protection checks
1812   - */
1813   - gen_op_set_alt_mode();
1814   - gen_op_ldl_data();
1815   - gen_op_restore_mode();
1816   - break;
1817   - case 0xF:
1818   - /* Quadword virtual access with alternate access mode and
1819   - * protection checks
1820   - */
1821   - gen_op_set_alt_mode();
1822   - gen_op_ldq_data();
1823   - gen_op_restore_mode();
1824   - break;
  1679 + if (ra != 31) {
  1680 + TCGv addr = tcg_temp_new(TCG_TYPE_I64);
  1681 + if (rb != 31)
  1682 + tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
  1683 + else
  1684 + tcg_gen_movi_i64(addr, disp12);
  1685 + switch ((insn >> 12) & 0xF) {
  1686 + case 0x0:
  1687 + /* Longword physical access */
  1688 + tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr);
  1689 + break;
  1690 + case 0x1:
  1691 + /* Quadword physical access */
  1692 + tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr);
  1693 + break;
  1694 + case 0x2:
  1695 + /* Longword physical access with lock */
  1696 + tcg_gen_helper_0_2(helper_ldl_l_raw, cpu_ir[ra], addr);
  1697 + break;
  1698 + case 0x3:
  1699 + /* Quadword physical access with lock */
  1700 + tcg_gen_helper_0_2(helper_ldq_l_raw, cpu_ir[ra], addr);
  1701 + break;
  1702 + case 0x4:
  1703 + /* Longword virtual PTE fetch */
  1704 + tcg_gen_helper_0_2(helper_ldl_kernel, cpu_ir[ra], addr);
  1705 + break;
  1706 + case 0x5:
  1707 + /* Quadword virtual PTE fetch */
  1708 + tcg_gen_helper_0_2(helper_ldq_kernel, cpu_ir[ra], addr);
  1709 + break;
  1710 + case 0x6:
  1711 + /* Incpu_ir[ra]id */
  1712 + goto incpu_ir[ra]id_opc;
  1713 + case 0x7:
  1714 + /* Incpu_ir[ra]id */
  1715 + goto incpu_ir[ra]id_opc;
  1716 + case 0x8:
  1717 + /* Longword virtual access */
  1718 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  1719 + tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr);
  1720 + break;
  1721 + case 0x9:
  1722 + /* Quadword virtual access */
  1723 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  1724 + tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr);
  1725 + break;
  1726 + case 0xA:
  1727 + /* Longword virtual access with protection check */
  1728 + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags);
  1729 + break;
  1730 + case 0xB:
  1731 + /* Quadword virtual access with protection check */
  1732 + tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags);
  1733 + break;
  1734 + case 0xC:
  1735 + /* Longword virtual access with altenate access mode */
  1736 + tcg_gen_helper_0_0(helper_set_alt_mode);
  1737 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  1738 + tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr);
  1739 + tcg_gen_helper_0_0(helper_restore_mode);
  1740 + break;
  1741 + case 0xD:
  1742 + /* Quadword virtual access with altenate access mode */
  1743 + tcg_gen_helper_0_0(helper_set_alt_mode);
  1744 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  1745 + tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr);
  1746 + tcg_gen_helper_0_0(helper_restore_mode);
  1747 + break;
  1748 + case 0xE:
  1749 + /* Longword virtual access with alternate access mode and
  1750 + * protection checks
  1751 + */
  1752 + tcg_gen_helper_0_0(helper_set_alt_mode);
  1753 + tcg_gen_helper_0_2(helper_ldl_data, cpu_ir[ra], addr);
  1754 + tcg_gen_helper_0_0(helper_restore_mode);
  1755 + break;
  1756 + case 0xF:
  1757 + /* Quadword virtual access with alternate access mode and
  1758 + * protection checks
  1759 + */
  1760 + tcg_gen_helper_0_0(helper_set_alt_mode);
  1761 + tcg_gen_helper_0_2(helper_ldq_data, cpu_ir[ra], addr);
  1762 + tcg_gen_helper_0_0(helper_restore_mode);
  1763 + break;
  1764 + }
  1765 + tcg_temp_free(addr);
1825 1766 }
1826   - if (ra != 31)
1827   - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
1828 1767 break;
1829 1768 #endif
1830 1769 case 0x1C:
... ... @@ -2014,12 +1953,18 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2014 1953 #else
2015 1954 if (!ctx->pal_mode)
2016 1955 goto invalid_opc;
2017   - if (ra != 31)
2018   - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
2019   - else
2020   - tcg_gen_movi_i64(cpu_T[0], 0);
2021   - gen_op_mtpr(insn & 0xFF);
2022   - ret = 2;
  1956 + else {
  1957 + TCGv tmp1 = tcg_const_i32(insn & 0xFF);
  1958 + if (ra != 31)
  1959 + tcg_gen_helper(helper_mtpr, tmp1, cpu_ir[ra]);
  1960 + else {
  1961 + TCGv tmp2 = tcg_const_i64(0);
  1962 + tcg_gen_helper(helper_mtpr, tmp1, tmp2);
  1963 + tcg_temp_free(tmp2);
  1964 + }
  1965 + tcg_temp_free(tmp1);
  1966 + ret = 2;
  1967 + }
2023 1968 break;
2024 1969 #endif
2025 1970 case 0x1E:
... ... @@ -2031,15 +1976,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2031 1976 goto invalid_opc;
2032 1977 if (rb == 31) {
2033 1978 /* "Old" alpha */
2034   - gen_op_hw_rei();
  1979 + tcg_gen_helper_0_0(helper_hw_rei);
2035 1980 } else {
2036   - if (ra != 31)
2037   - tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
2038   - else
2039   - tcg_gen_movi_i64(cpu_T[0], 0);
2040   - tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
2041   - tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2042   - gen_op_hw_ret();
  1981 + TCGv tmp;
  1982 +
  1983 + if (ra != 31) {
  1984 + tmp = tcg_temp_new(TCG_TYPE_I64);
  1985 + tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
  1986 + } else
  1987 + tmp = tcg_const_i64(((int64_t)insn << 51) >> 51);
  1988 + tcg_gen_helper_0_1(helper_hw_ret, tmp);
  1989 + tcg_temp_free(tmp);
2043 1990 }
2044 1991 ret = 2;
2045 1992 break;
... ... @@ -2051,79 +1998,88 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2051 1998 #else
2052 1999 if (!ctx->pal_mode)
2053 2000 goto invalid_opc;
2054   - if (ra != 31)
2055   - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
2056   - else
2057   - tcg_gen_movi_i64(cpu_T[0], disp12);
2058   - if (ra != 31)
2059   - tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
2060   - else
2061   - tcg_gen_movi_i64(cpu_T[1], 0);
2062   - switch ((insn >> 12) & 0xF) {
2063   - case 0x0:
2064   - /* Longword physical access */
2065   - gen_op_stl_raw();
2066   - break;
2067   - case 0x1:
2068   - /* Quadword physical access */
2069   - gen_op_stq_raw();
2070   - break;
2071   - case 0x2:
2072   - /* Longword physical access with lock */
2073   - gen_op_stl_c_raw();
2074   - break;
2075   - case 0x3:
2076   - /* Quadword physical access with lock */
2077   - gen_op_stq_c_raw();
2078   - break;
2079   - case 0x4:
2080   - /* Longword virtual access */
2081   - gen_op_st_phys_to_virt();
2082   - gen_op_stl_raw();
2083   - break;
2084   - case 0x5:
2085   - /* Quadword virtual access */
2086   - gen_op_st_phys_to_virt();
2087   - gen_op_stq_raw();
2088   - break;
2089   - case 0x6:
2090   - /* Invalid */
2091   - goto invalid_opc;
2092   - case 0x7:
2093   - /* Invalid */
2094   - goto invalid_opc;
2095   - case 0x8:
2096   - /* Invalid */
2097   - goto invalid_opc;
2098   - case 0x9:
2099   - /* Invalid */
2100   - goto invalid_opc;
2101   - case 0xA:
2102   - /* Invalid */
2103   - goto invalid_opc;
2104   - case 0xB:
2105   - /* Invalid */
2106   - goto invalid_opc;
2107   - case 0xC:
2108   - /* Longword virtual access with alternate access mode */
2109   - gen_op_set_alt_mode();
2110   - gen_op_st_phys_to_virt();
2111   - gen_op_ldl_raw();
2112   - gen_op_restore_mode();
2113   - break;
2114   - case 0xD:
2115   - /* Quadword virtual access with alternate access mode */
2116   - gen_op_set_alt_mode();
2117   - gen_op_st_phys_to_virt();
2118   - gen_op_ldq_raw();
2119   - gen_op_restore_mode();
2120   - break;
2121   - case 0xE:
2122   - /* Invalid */
2123   - goto invalid_opc;
2124   - case 0xF:
2125   - /* Invalid */
2126   - goto invalid_opc;
  2001 + else {
  2002 + TCGv addr, val;
  2003 + addr = tcg_temp_new(TCG_TYPE_I64);
  2004 + if (rb != 31)
  2005 + tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
  2006 + else
  2007 + tcg_gen_movi_i64(addr, disp12);
  2008 + if (ra != 31)
  2009 + val = cpu_ir[ra];
  2010 + else {
  2011 + val = tcg_temp_new(TCG_TYPE_I64);
  2012 + tcg_gen_movi_i64(val, 0);
  2013 + }
  2014 + switch ((insn >> 12) & 0xF) {
  2015 + case 0x0:
  2016 + /* Longword physical access */
  2017 + tcg_gen_helper_0_2(helper_stl_raw, val, addr);
  2018 + break;
  2019 + case 0x1:
  2020 + /* Quadword physical access */
  2021 + tcg_gen_helper_0_2(helper_stq_raw, val, addr);
  2022 + break;
  2023 + case 0x2:
  2024 + /* Longword physical access with lock */
  2025 + tcg_gen_helper_1_2(helper_stl_c_raw, val, val, addr);
  2026 + break;
  2027 + case 0x3:
  2028 + /* Quadword physical access with lock */
  2029 + tcg_gen_helper_1_2(helper_stq_c_raw, val, val, addr);
  2030 + break;
  2031 + case 0x4:
  2032 + /* Longword virtual access */
  2033 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  2034 + tcg_gen_helper_0_2(helper_stl_raw, val, addr);
  2035 + break;
  2036 + case 0x5:
  2037 + /* Quadword virtual access */
  2038 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  2039 + tcg_gen_helper_0_2(helper_stq_raw, val, addr);
  2040 + break;
  2041 + case 0x6:
  2042 + /* Invalid */
  2043 + goto invalid_opc;
  2044 + case 0x7:
  2045 + /* Invalid */
  2046 + goto invalid_opc;
  2047 + case 0x8:
  2048 + /* Invalid */
  2049 + goto invalid_opc;
  2050 + case 0x9:
  2051 + /* Invalid */
  2052 + goto invalid_opc;
  2053 + case 0xA:
  2054 + /* Invalid */
  2055 + goto invalid_opc;
  2056 + case 0xB:
  2057 + /* Invalid */
  2058 + goto invalid_opc;
  2059 + case 0xC:
  2060 + /* Longword virtual access with alternate access mode */
  2061 + tcg_gen_helper_0_0(helper_set_alt_mode);
  2062 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  2063 + tcg_gen_helper_0_2(helper_stl_raw, val, addr);
  2064 + tcg_gen_helper_0_0(helper_restore_mode);
  2065 + break;
  2066 + case 0xD:
  2067 + /* Quadword virtual access with alternate access mode */
  2068 + tcg_gen_helper_0_0(helper_set_alt_mode);
  2069 + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
  2070 + tcg_gen_helper_0_2(helper_stl_raw, val, addr);
  2071 + tcg_gen_helper_0_0(helper_restore_mode);
  2072 + break;
  2073 + case 0xE:
  2074 + /* Invalid */
  2075 + goto invalid_opc;
  2076 + case 0xF:
  2077 + /* Invalid */
  2078 + goto invalid_opc;
  2079 + }
  2080 + if (ra != 31)
  2081 + tcg_temp_free(val);
  2082 + tcg_temp_free(addr);
2127 2083 }
2128 2084 ret = 2;
2129 2085 break;
... ...