gwj / at91sam9263 · Commits

Commit f4ed86794cf6f2e3d5cdc63424e99358da6248cf

Authored by aurel32
1 parent e820e3f4

target-alpha: convert locked load/store to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5359 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 52 additions and 40 deletions
target-alpha/translate.c
  View file @f4ed867
... ... @@ -49,6 +49,7 @@ static TCGv cpu_env;
49 49 static TCGv cpu_ir[31];
50 50 static TCGv cpu_fir[31];
51 51 static TCGv cpu_pc;
  52 +static TCGv cpu_lock;
52 53  
53 54 /* dyngen register indexes */
54 55 static TCGv cpu_T[2];
... ... @@ -95,6 +96,9 @@ static void alpha_translate_init(void)
95 96 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
96 97 offsetof(CPUState, pc), "pc");
97 98  
  99 + cpu_lock = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
  100 + offsetof(CPUState, lock), "lock");
  101 +
98 102 /* register helpers */
99 103 #undef DEF_HELPER
100 104 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
... ... @@ -171,24 +175,6 @@ static always_inline void gen_invalid (DisasContext *ctx)
171 175 gen_excp(ctx, EXCP_OPCDEC, 0);
172 176 }
173 177  
174   -static always_inline void gen_load_mem_dyngen (DisasContext *ctx,
175   - void (*gen_load_op)(DisasContext *ctx),
176   - int ra, int rb, int32_t disp16,
177   - int clear)
178   -{
179   - if (ra != 31 || disp16 != 0) {
180   - if (rb != 31)
181   - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
182   - else
183   - tcg_gen_movi_i64(cpu_T[0], disp16);
184   - if (clear)
185   - tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
186   - (*gen_load_op)(ctx);
187   - if (ra != 31)
188   - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
189   - }
190   -}
191   -
192 178 static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
193 179 {
194 180 TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
... ... @@ -213,6 +199,18 @@ static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
213 199 tcg_temp_free(tmp);
214 200 }
215 201  
  202 +static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
  203 +{
  204 + tcg_gen_mov_i64(cpu_lock, t1);
  205 + tcg_gen_qemu_ld32s(t0, t1, flags);
  206 +}
  207 +
  208 +static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
  209 +{
  210 + tcg_gen_mov_i64(cpu_lock, t1);
  211 + tcg_gen_qemu_ld64(t0, t1, flags);
  212 +}
  213 +
216 214 static always_inline void gen_load_mem (DisasContext *ctx,
217 215 void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
218 216 int ra, int rb, int32_t disp16,
... ... @@ -240,24 +238,6 @@ static always_inline void gen_load_mem (DisasContext *ctx,
240 238 tcg_temp_free(addr);
241 239 }
242 240  
243   -static always_inline void gen_store_mem_dyngen (DisasContext *ctx,
244   - void (*gen_store_op)(DisasContext *ctx),
245   - int ra, int rb, int32_t disp16,
246   - int clear)
247   -{
248   - if (rb != 31)
249   - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
250   - else
251   - tcg_gen_movi_i64(cpu_T[0], disp16);
252   - if (clear)
253   - tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
254   - if (ra != 31)
255   - tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
256   - else
257   - tcg_gen_movi_i64(cpu_T[1], 0);
258   - (*gen_store_op)(ctx);
259   -}
260   -
261 241 static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
262 242 {
263 243 TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
... ... @@ -282,6 +262,38 @@ static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
282 262 tcg_temp_free(tmp);
283 263 }
284 264  
  265 +static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
  266 +{
  267 + int l1, l2;
  268 +
  269 + l1 = gen_new_label();
  270 + l2 = gen_new_label();
  271 + tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);
  272 + tcg_gen_qemu_st32(t0, t1, flags);
  273 + tcg_gen_movi_i64(t0, 0);
  274 + tcg_gen_br(l2);
  275 + gen_set_label(l1);
  276 + tcg_gen_movi_i64(t0, 1);
  277 + gen_set_label(l2);
  278 + tcg_gen_movi_i64(cpu_lock, -1);
  279 +}
  280 +
  281 +static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
  282 +{
  283 + int l1, l2;
  284 +
  285 + l1 = gen_new_label();
  286 + l2 = gen_new_label();
  287 + tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);
  288 + tcg_gen_qemu_st64(t0, t1, flags);
  289 + tcg_gen_movi_i64(t0, 0);
  290 + tcg_gen_br(l2);
  291 + gen_set_label(l1);
  292 + tcg_gen_movi_i64(t0, 1);
  293 + gen_set_label(l2);
  294 + tcg_gen_movi_i64(cpu_lock, -1);
  295 +}
  296 +
285 297 static always_inline void gen_store_mem (DisasContext *ctx,
286 298 void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
287 299 int ra, int rb, int32_t disp16,
... ... @@ -2158,11 +2170,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2158 2170 break;
2159 2171 case 0x2A:
2160 2172 /* LDL_L */
2161   - gen_load_mem_dyngen(ctx, &gen_ldl_l, ra, rb, disp16, 0);
  2173 + gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
2162 2174 break;
2163 2175 case 0x2B:
2164 2176 /* LDQ_L */
2165   - gen_load_mem_dyngen(ctx, &gen_ldq_l, ra, rb, disp16, 0);
  2177 + gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
2166 2178 break;
2167 2179 case 0x2C:
2168 2180 /* STL */
... ... @@ -2174,11 +2186,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2174 2186 break;
2175 2187 case 0x2E:
2176 2188 /* STL_C */
2177   - gen_store_mem_dyngen(ctx, &gen_stl_c, ra, rb, disp16, 0);
  2189 + gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0);
2178 2190 break;
2179 2191 case 0x2F:
2180 2192 /* STQ_C */
2181   - gen_store_mem_dyngen(ctx, &gen_stq_c, ra, rb, disp16, 0);
  2193 + gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0);
2182 2194 break;
2183 2195 case 0x30:
2184 2196 /* BR */
... ...