Commit 7debeb82ffad5480c230c116ba17a9c1d8e32016

Authored by blueswir1
1 parent 498fbd8a

Name the magic constants, use correct value for AUX2_PWRFAIL


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3754 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 51 additions and 32 deletions
hw/slavio_misc.c
@@ -58,11 +58,30 @@ typedef struct MiscState { @@ -58,11 +58,30 @@ typedef struct MiscState {
58 #define LED_MAXADDR 2 58 #define LED_MAXADDR 2
59 #define LED_SIZE (LED_MAXADDR + 1) 59 #define LED_SIZE (LED_MAXADDR + 1)
60 60
  61 +#define MISC_MASK 0x0fff0000
  62 +#define MISC_LEDS 0x01600000
  63 +#define MISC_CFG 0x01800000
  64 +#define MISC_AUX1 0x01900000
  65 +#define MISC_AUX2 0x01910000
  66 +#define MISC_DIAG 0x01a00000
  67 +#define MISC_MDM 0x01b00000
  68 +#define MISC_SYS 0x01f00000
  69 +#define MISC_PWR 0x0a000000
  70 +
  71 +#define AUX2_PWROFF 0x01
  72 +#define AUX2_PWRINTCLR 0x02
  73 +#define AUX2_PWRFAIL 0x20
  74 +
  75 +#define CFG_PWRINTEN 0x08
  76 +
  77 +#define SYS_RESET 0x01
  78 +#define SYS_RESETSTAT 0x02
  79 +
61 static void slavio_misc_update_irq(void *opaque) 80 static void slavio_misc_update_irq(void *opaque)
62 { 81 {
63 MiscState *s = opaque; 82 MiscState *s = opaque;
64 83
65 - if ((s->aux2 & 0x4) && (s->config & 0x8)) { 84 + if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
66 MISC_DPRINTF("Raise IRQ\n"); 85 MISC_DPRINTF("Raise IRQ\n");
67 qemu_irq_raise(s->irq); 86 qemu_irq_raise(s->irq);
68 } else { 87 } else {
@@ -84,10 +103,10 @@ void slavio_set_power_fail(void *opaque, int power_failing) @@ -84,10 +103,10 @@ void slavio_set_power_fail(void *opaque, int power_failing)
84 MiscState *s = opaque; 103 MiscState *s = opaque;
85 104
86 MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config); 105 MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
87 - if (power_failing && (s->config & 0x8)) {  
88 - s->aux2 |= 0x4; 106 + if (power_failing && (s->config & CFG_PWRINTEN)) {
  107 + s->aux2 |= AUX2_PWRFAIL;
89 } else { 108 } else {
90 - s->aux2 &= ~0x4; 109 + s->aux2 &= ~AUX2_PWRFAIL;
91 } 110 }
92 slavio_misc_update_irq(s); 111 slavio_misc_update_irq(s);
93 } 112 }
@@ -97,36 +116,36 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, @@ -97,36 +116,36 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
97 { 116 {
98 MiscState *s = opaque; 117 MiscState *s = opaque;
99 118
100 - switch (addr & 0xfff0000) {  
101 - case 0x1800000: 119 + switch (addr & MISC_MASK) {
  120 + case MISC_CFG:
102 MISC_DPRINTF("Write config %2.2x\n", val & 0xff); 121 MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
103 s->config = val & 0xff; 122 s->config = val & 0xff;
104 slavio_misc_update_irq(s); 123 slavio_misc_update_irq(s);
105 break; 124 break;
106 - case 0x1900000: 125 + case MISC_AUX1:
107 MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); 126 MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
108 s->aux1 = val & 0xff; 127 s->aux1 = val & 0xff;
109 break; 128 break;
110 - case 0x1910000:  
111 - val &= 0x3; 129 + case MISC_AUX2:
  130 + val &= AUX2_PWRINTCLR | AUX2_PWROFF;
112 MISC_DPRINTF("Write aux2 %2.2x\n", val); 131 MISC_DPRINTF("Write aux2 %2.2x\n", val);
113 - val |= s->aux2 & 0x4;  
114 - if (val & 0x2) // Clear Power Fail int  
115 - val &= 0x1; 132 + val |= s->aux2 & AUX2_PWRFAIL;
  133 + if (val & AUX2_PWRINTCLR) // Clear Power Fail int
  134 + val &= AUX2_PWROFF;
116 s->aux2 = val; 135 s->aux2 = val;
117 - if (val & 1) 136 + if (val & AUX2_PWROFF)
118 qemu_system_shutdown_request(); 137 qemu_system_shutdown_request();
119 slavio_misc_update_irq(s); 138 slavio_misc_update_irq(s);
120 break; 139 break;
121 - case 0x1a00000: 140 + case MISC_DIAG:
122 MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); 141 MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
123 s->diag = val & 0xff; 142 s->diag = val & 0xff;
124 break; 143 break;
125 - case 0x1b00000: 144 + case MISC_MDM:
126 MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); 145 MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
127 s->mctrl = val & 0xff; 146 s->mctrl = val & 0xff;
128 break; 147 break;
129 - case 0xa000000: 148 + case MISC_PWR:
130 MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); 149 MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
131 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); 150 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
132 break; 151 break;
@@ -138,28 +157,28 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) @@ -138,28 +157,28 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
138 MiscState *s = opaque; 157 MiscState *s = opaque;
139 uint32_t ret = 0; 158 uint32_t ret = 0;
140 159
141 - switch (addr & 0xfff0000) {  
142 - case 0x1800000: 160 + switch (addr & MISC_MASK) {
  161 + case MISC_CFG:
143 ret = s->config; 162 ret = s->config;
144 MISC_DPRINTF("Read config %2.2x\n", ret); 163 MISC_DPRINTF("Read config %2.2x\n", ret);
145 break; 164 break;
146 - case 0x1900000: 165 + case MISC_AUX1:
147 ret = s->aux1; 166 ret = s->aux1;
148 MISC_DPRINTF("Read aux1 %2.2x\n", ret); 167 MISC_DPRINTF("Read aux1 %2.2x\n", ret);
149 break; 168 break;
150 - case 0x1910000: 169 + case MISC_AUX2:
151 ret = s->aux2; 170 ret = s->aux2;
152 MISC_DPRINTF("Read aux2 %2.2x\n", ret); 171 MISC_DPRINTF("Read aux2 %2.2x\n", ret);
153 break; 172 break;
154 - case 0x1a00000: 173 + case MISC_DIAG:
155 ret = s->diag; 174 ret = s->diag;
156 MISC_DPRINTF("Read diag %2.2x\n", ret); 175 MISC_DPRINTF("Read diag %2.2x\n", ret);
157 break; 176 break;
158 - case 0x1b00000: 177 + case MISC_MDM:
159 ret = s->mctrl; 178 ret = s->mctrl;
160 MISC_DPRINTF("Read modem control %2.2x\n", ret); 179 MISC_DPRINTF("Read modem control %2.2x\n", ret);
161 break; 180 break;
162 - case 0xa000000: 181 + case MISC_PWR:
163 MISC_DPRINTF("Read power management %2.2x\n", ret); 182 MISC_DPRINTF("Read power management %2.2x\n", ret);
164 break; 183 break;
165 } 184 }
@@ -207,8 +226,8 @@ static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, @@ -207,8 +226,8 @@ static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
207 val); 226 val);
208 switch (saddr) { 227 switch (saddr) {
209 case 0: 228 case 0:
210 - if (val & 1) {  
211 - s->sysctrl = 0x2; 229 + if (val & SYS_RESET) {
  230 + s->sysctrl = SYS_RESETSTAT;
212 qemu_system_reset_request(); 231 qemu_system_reset_request();
213 } 232 }
214 break; 233 break;
@@ -328,19 +347,19 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, @@ -328,19 +347,19 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
328 slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, 347 slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
329 slavio_misc_mem_write, s); 348 slavio_misc_mem_write, s);
330 // Slavio control 349 // Slavio control
331 - cpu_register_physical_memory(base + 0x1800000, MISC_SIZE, 350 + cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
332 slavio_misc_io_memory); 351 slavio_misc_io_memory);
333 // AUX 1 352 // AUX 1
334 - cpu_register_physical_memory(base + 0x1900000, MISC_SIZE, 353 + cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
335 slavio_misc_io_memory); 354 slavio_misc_io_memory);
336 // AUX 2 355 // AUX 2
337 - cpu_register_physical_memory(base + 0x1910000, MISC_SIZE, 356 + cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
338 slavio_misc_io_memory); 357 slavio_misc_io_memory);
339 // Diagnostics 358 // Diagnostics
340 - cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE, 359 + cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
341 slavio_misc_io_memory); 360 slavio_misc_io_memory);
342 // Modem control 361 // Modem control
343 - cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE, 362 + cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
344 slavio_misc_io_memory); 363 slavio_misc_io_memory);
345 // Power management 364 // Power management
346 cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory); 365 cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
@@ -349,7 +368,7 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, @@ -349,7 +368,7 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
349 slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read, 368 slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
350 slavio_led_mem_write, s); 369 slavio_led_mem_write, s);
351 /* ss600mp diag LEDs */ 370 /* ss600mp diag LEDs */
352 - cpu_register_physical_memory(base + 0x1600000, MISC_SIZE, 371 + cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
353 slavio_misc_io_memory); 372 slavio_misc_io_memory);
354 373
355 /* 32 bit registers */ 374 /* 32 bit registers */
@@ -357,7 +376,7 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base, @@ -357,7 +376,7 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
357 slavio_sysctrl_mem_write, 376 slavio_sysctrl_mem_write,
358 s); 377 s);
359 // System control 378 // System control
360 - cpu_register_physical_memory(base + 0x1f00000, SYSCTRL_SIZE, 379 + cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
361 slavio_misc_io_memory); 380 slavio_misc_io_memory);
362 381
363 s->irq = irq; 382 s->irq = irq;