Commit 6c78ea32e1f02216f45dee69a0c6ee0ca968fdac
1 parent
3b2d1e92
Convert udiv/sdiv
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2 changed files
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31 additions
and
19 deletions
target-sparc/op_helper.c
@@ -790,6 +790,29 @@ static inline uint32_t get_NZ_xcc(target_ulong dst) | @@ -790,6 +790,29 @@ static inline uint32_t get_NZ_xcc(target_ulong dst) | ||
790 | } | 790 | } |
791 | #endif | 791 | #endif |
792 | 792 | ||
793 | +static inline uint32_t get_V_div_icc(target_ulong src2) | ||
794 | +{ | ||
795 | + uint32_t ret = 0; | ||
796 | + | ||
797 | + if (src2 != 0) | ||
798 | + ret |= PSR_OVF; | ||
799 | + return ret; | ||
800 | +} | ||
801 | + | ||
802 | +static uint32_t compute_all_div(void) | ||
803 | +{ | ||
804 | + uint32_t ret; | ||
805 | + | ||
806 | + ret = get_NZ_icc(CC_DST); | ||
807 | + ret |= get_V_div_icc(CC_SRC2); | ||
808 | + return ret; | ||
809 | +} | ||
810 | + | ||
811 | +static uint32_t compute_C_div(void) | ||
812 | +{ | ||
813 | + return 0; | ||
814 | +} | ||
815 | + | ||
793 | static inline uint32_t get_C_add_icc(target_ulong dst, target_ulong src1) | 816 | static inline uint32_t get_C_add_icc(target_ulong dst, target_ulong src1) |
794 | { | 817 | { |
795 | uint32_t ret = 0; | 818 | uint32_t ret = 0; |
@@ -1108,6 +1131,7 @@ typedef struct CCTable { | @@ -1108,6 +1131,7 @@ typedef struct CCTable { | ||
1108 | static const CCTable icc_table[CC_OP_NB] = { | 1131 | static const CCTable icc_table[CC_OP_NB] = { |
1109 | /* CC_OP_DYNAMIC should never happen */ | 1132 | /* CC_OP_DYNAMIC should never happen */ |
1110 | [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, | 1133 | [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, |
1134 | + [CC_OP_DIV] = { compute_all_div, compute_C_div }, | ||
1111 | [CC_OP_ADD] = { compute_all_add, compute_C_add }, | 1135 | [CC_OP_ADD] = { compute_all_add, compute_C_add }, |
1112 | [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, | 1136 | [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, |
1113 | [CC_OP_TADD] = { compute_all_tadd, compute_C_tadd }, | 1137 | [CC_OP_TADD] = { compute_all_tadd, compute_C_tadd }, |
@@ -1123,6 +1147,7 @@ static const CCTable icc_table[CC_OP_NB] = { | @@ -1123,6 +1147,7 @@ static const CCTable icc_table[CC_OP_NB] = { | ||
1123 | static const CCTable xcc_table[CC_OP_NB] = { | 1147 | static const CCTable xcc_table[CC_OP_NB] = { |
1124 | /* CC_OP_DYNAMIC should never happen */ | 1148 | /* CC_OP_DYNAMIC should never happen */ |
1125 | [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, | 1149 | [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, |
1150 | + [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic }, | ||
1126 | [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, | 1151 | [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1127 | [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, | 1152 | [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, |
1128 | [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, | 1153 | [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
target-sparc/translate.c
@@ -701,19 +701,6 @@ static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) | @@ -701,19 +701,6 @@ static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) | ||
701 | } | 701 | } |
702 | #endif | 702 | #endif |
703 | 703 | ||
704 | -static inline void gen_op_div_cc(TCGv dst) | ||
705 | -{ | ||
706 | - int l1; | ||
707 | - | ||
708 | - tcg_gen_mov_tl(cpu_cc_dst, dst); | ||
709 | - gen_cc_clear_icc(); | ||
710 | - gen_cc_NZ_icc(cpu_cc_dst); | ||
711 | - l1 = gen_new_label(); | ||
712 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1); | ||
713 | - tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); | ||
714 | - gen_set_label(l1); | ||
715 | -} | ||
716 | - | ||
717 | // 1 | 704 | // 1 |
718 | static inline void gen_op_eval_ba(TCGv dst) | 705 | static inline void gen_op_eval_ba(TCGv dst) |
719 | { | 706 | { |
@@ -3151,18 +3138,18 @@ static void disas_sparc_insn(DisasContext * dc) | @@ -3151,18 +3138,18 @@ static void disas_sparc_insn(DisasContext * dc) | ||
3151 | CHECK_IU_FEATURE(dc, DIV); | 3138 | CHECK_IU_FEATURE(dc, DIV); |
3152 | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); | 3139 | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
3153 | if (xop & 0x10) { | 3140 | if (xop & 0x10) { |
3154 | - gen_op_div_cc(cpu_dst); | ||
3155 | - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); | ||
3156 | - dc->cc_op = CC_OP_FLAGS; | 3141 | + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3142 | + tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); | ||
3143 | + dc->cc_op = CC_OP_DIV; | ||
3157 | } | 3144 | } |
3158 | break; | 3145 | break; |
3159 | case 0xf: /* sdiv */ | 3146 | case 0xf: /* sdiv */ |
3160 | CHECK_IU_FEATURE(dc, DIV); | 3147 | CHECK_IU_FEATURE(dc, DIV); |
3161 | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); | 3148 | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
3162 | if (xop & 0x10) { | 3149 | if (xop & 0x10) { |
3163 | - gen_op_div_cc(cpu_dst); | ||
3164 | - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); | ||
3165 | - dc->cc_op = CC_OP_FLAGS; | 3150 | + tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3151 | + tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); | ||
3152 | + dc->cc_op = CC_OP_DIV; | ||
3166 | } | 3153 | } |
3167 | break; | 3154 | break; |
3168 | default: | 3155 | default: |