gwj / at91sam9263 · Commits

Commit 650bbb361eb5d815bbe9aa8f2c0aa57eae5592b8

Authored by balrog
1 parent 788abf8e

Implement neg_i32, clean-up. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 10 additions and 5 deletions
tcg/arm/tcg-target.c
  View file @650bbb3
@@ -64,7 +64,7 @@ const int tcg_target_call_oarg_regs[2] = { @@ -64,7 +64,7 @@ const int tcg_target_call_oarg_regs[2] = {
64 TCG_REG_R0, TCG_REG_R1 64 TCG_REG_R0, TCG_REG_R1
65 }; 65 };
66 66
67 -static void patch_reloc(uint8_t *code_ptr, int type, 67 +static void patch_reloc(uint8_t *code_ptr, int type,
68 tcg_target_long value, tcg_target_long addend) 68 tcg_target_long value, tcg_target_long addend)
69 { 69 {
70 switch (type) { 70 switch (type) {
@@ -913,7 +913,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond, @@ -913,7 +913,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
913 1, 0, addr_reg2, SHIFT_IMM_LSL(0)); 913 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
914 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index); 914 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
915 # endif 915 # endif
916 - tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] - 916 + tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
917 (tcg_target_long) s->code_ptr); 917 (tcg_target_long) s->code_ptr);
918 918
919 switch (opc) { 919 switch (opc) {
@@ -1178,10 +1178,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond, @@ -1178,10 +1178,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1178 #endif 1178 #endif
1179 } 1179 }
1180 1180
1181 -extern void exec_loop;  
1182 static uint8_t *tb_ret_addr; 1181 static uint8_t *tb_ret_addr;
1183 1182
1184 -static inline void tcg_out_op(TCGContext *s, int opc, 1183 +static inline void tcg_out_op(TCGContext *s, int opc,
1185 const TCGArg *args, const int *const_args) 1184 const TCGArg *args, const int *const_args)
1186 { 1185 {
1187 int c; 1186 int c;
@@ -1312,6 +1311,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, @@ -1312,6 +1311,9 @@ static inline void tcg_out_op(TCGContext *s, int opc,
1312 args[0], args[1], args[2], args[3], 1311 args[0], args[1], args[2], args[3],
1313 args[4], args[5], SHIFT_IMM_LSL(0)); 1312 args[4], args[5], SHIFT_IMM_LSL(0));
1314 break; 1313 break;
  1314 + case INDEX_op_neg_i32:
  1315 + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
  1316 + break;
1315 case INDEX_op_mul_i32: 1317 case INDEX_op_mul_i32:
1316 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); 1318 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1317 break; 1319 break;
@@ -1384,7 +1386,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, @@ -1384,7 +1386,7 @@ static inline void tcg_out_op(TCGContext *s, int opc,
1384 case INDEX_op_qemu_ld64: 1386 case INDEX_op_qemu_ld64:
1385 tcg_out_qemu_ld(s, COND_AL, args, 3); 1387 tcg_out_qemu_ld(s, COND_AL, args, 3);
1386 break; 1388 break;
1387 - 1389 +
1388 case INDEX_op_qemu_st8: 1390 case INDEX_op_qemu_st8:
1389 tcg_out_qemu_st(s, COND_AL, args, 0); 1391 tcg_out_qemu_st(s, COND_AL, args, 0);
1390 break; 1392 break;
@@ -1445,6 +1447,7 @@ static const TCGTargetOpDef arm_op_defs[] = { @@ -1445,6 +1447,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
1445 { INDEX_op_and_i32, { "r", "r", "r" } }, 1447 { INDEX_op_and_i32, { "r", "r", "r" } },
1446 { INDEX_op_or_i32, { "r", "r", "r" } }, 1448 { INDEX_op_or_i32, { "r", "r", "r" } },
1447 { INDEX_op_xor_i32, { "r", "r", "r" } }, 1449 { INDEX_op_xor_i32, { "r", "r", "r" } },
  1450 + { INDEX_op_neg_i32, { "r", "r" } },
1448 1451
1449 { INDEX_op_shl_i32, { "r", "r", "ri" } }, 1452 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1450 { INDEX_op_shr_i32, { "r", "r", "ri" } }, 1453 { INDEX_op_shr_i32, { "r", "r", "ri" } },
tcg/arm/tcg-target.h
  View file @650bbb3
@@ -31,6 +31,8 @@ @@ -31,6 +31,8 @@
31 #undef TCG_TARGET_HAS_bswap_i32 31 #undef TCG_TARGET_HAS_bswap_i32
32 #define TCG_TARGET_HAS_ext8s_i32 32 #define TCG_TARGET_HAS_ext8s_i32
33 #define TCG_TARGET_HAS_ext16s_i32 33 #define TCG_TARGET_HAS_ext16s_i32
  34 +#define TCG_TARGET_HAS_neg_i32
  35 +#undef TCG_TARGET_HAS_neg_i64
34 #undef TCG_TARGET_STACK_GROWSUP 36 #undef TCG_TARGET_STACK_GROWSUP
35 37
36 enum { 38 enum {