Commit 650bbb361eb5d815bbe9aa8f2c0aa57eae5592b8
1 parent
788abf8e
Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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10 additions
and
5 deletions
tcg/arm/tcg-target.c
| ... | ... | @@ -64,7 +64,7 @@ const int tcg_target_call_oarg_regs[2] = { |
| 64 | 64 | TCG_REG_R0, TCG_REG_R1 |
| 65 | 65 | }; |
| 66 | 66 | |
| 67 | -static void patch_reloc(uint8_t *code_ptr, int type, | |
| 67 | +static void patch_reloc(uint8_t *code_ptr, int type, | |
| 68 | 68 | tcg_target_long value, tcg_target_long addend) |
| 69 | 69 | { |
| 70 | 70 | switch (type) { |
| ... | ... | @@ -913,7 +913,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond, |
| 913 | 913 | 1, 0, addr_reg2, SHIFT_IMM_LSL(0)); |
| 914 | 914 | tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index); |
| 915 | 915 | # endif |
| 916 | - tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] - | |
| 916 | + tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] - | |
| 917 | 917 | (tcg_target_long) s->code_ptr); |
| 918 | 918 | |
| 919 | 919 | switch (opc) { |
| ... | ... | @@ -1178,10 +1178,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond, |
| 1178 | 1178 | #endif |
| 1179 | 1179 | } |
| 1180 | 1180 | |
| 1181 | -extern void exec_loop; | |
| 1182 | 1181 | static uint8_t *tb_ret_addr; |
| 1183 | 1182 | |
| 1184 | -static inline void tcg_out_op(TCGContext *s, int opc, | |
| 1183 | +static inline void tcg_out_op(TCGContext *s, int opc, | |
| 1185 | 1184 | const TCGArg *args, const int *const_args) |
| 1186 | 1185 | { |
| 1187 | 1186 | int c; |
| ... | ... | @@ -1312,6 +1311,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, |
| 1312 | 1311 | args[0], args[1], args[2], args[3], |
| 1313 | 1312 | args[4], args[5], SHIFT_IMM_LSL(0)); |
| 1314 | 1313 | break; |
| 1314 | + case INDEX_op_neg_i32: | |
| 1315 | + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); | |
| 1316 | + break; | |
| 1315 | 1317 | case INDEX_op_mul_i32: |
| 1316 | 1318 | tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); |
| 1317 | 1319 | break; |
| ... | ... | @@ -1384,7 +1386,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, |
| 1384 | 1386 | case INDEX_op_qemu_ld64: |
| 1385 | 1387 | tcg_out_qemu_ld(s, COND_AL, args, 3); |
| 1386 | 1388 | break; |
| 1387 | - | |
| 1389 | + | |
| 1388 | 1390 | case INDEX_op_qemu_st8: |
| 1389 | 1391 | tcg_out_qemu_st(s, COND_AL, args, 0); |
| 1390 | 1392 | break; |
| ... | ... | @@ -1445,6 +1447,7 @@ static const TCGTargetOpDef arm_op_defs[] = { |
| 1445 | 1447 | { INDEX_op_and_i32, { "r", "r", "r" } }, |
| 1446 | 1448 | { INDEX_op_or_i32, { "r", "r", "r" } }, |
| 1447 | 1449 | { INDEX_op_xor_i32, { "r", "r", "r" } }, |
| 1450 | + { INDEX_op_neg_i32, { "r", "r" } }, | |
| 1448 | 1451 | |
| 1449 | 1452 | { INDEX_op_shl_i32, { "r", "r", "ri" } }, |
| 1450 | 1453 | { INDEX_op_shr_i32, { "r", "r", "ri" } }, | ... | ... |
tcg/arm/tcg-target.h