gwj / at91sam9263 · Commits

Commit 578bb25230229307c0b6ff62ae03ac0fbda27b18

Authored by j_mayer
1 parent 056b05f8

More comments about unimplemented SPRs. 

Tag unused functions with unused attribute instead of using #ifdef (TODO)
  to ease tests: just have to enable the implementation in the cpu_defs table.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3306 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 110 additions and 56 deletions
target-ppc/translate_init.c
  View file @578bb25
... ... @@ -275,17 +275,16 @@ static void spr_write_sdr1 (void *opaque, int sprn)
275 275  
276 276 /* 64 bits PowerPC specific SPRs */
277 277 /* ASR */
278   -/* Currently unused */
279   -#if 0 && defined(TARGET_PPC64)
  278 +#if defined(TARGET_PPC64)
  279 +__attribute__ (( unused ))
280 280 static void spr_read_asr (void *opaque, int sprn)
281 281 {
282 282 gen_op_load_asr();
283 283 }
284 284  
  285 +__attribute__ (( unused ))
285 286 static void spr_write_asr (void *opaque, int sprn)
286 287 {
287   - DisasContext *ctx = opaque;
288   -
289 288 gen_op_store_asr();
290 289 }
291 290 #endif
... ... @@ -816,30 +815,37 @@ static void gen_spr_7xx (CPUPPCState *env)
816 815 SPR_NOACCESS, SPR_NOACCESS,
817 816 &spr_read_generic, SPR_NOACCESS,
818 817 0x00000000);
  818 + /* XXX : not implemented */
819 819 spr_register(env, SPR_UMMCR0, "UMMCR0",
820 820 &spr_read_ureg, SPR_NOACCESS,
821 821 &spr_read_ureg, SPR_NOACCESS,
822 822 0x00000000);
  823 + /* XXX : not implemented */
823 824 spr_register(env, SPR_UMMCR1, "UMMCR1",
824 825 &spr_read_ureg, SPR_NOACCESS,
825 826 &spr_read_ureg, SPR_NOACCESS,
826 827 0x00000000);
  828 + /* XXX : not implemented */
827 829 spr_register(env, SPR_UPMC1, "UPMC1",
828 830 &spr_read_ureg, SPR_NOACCESS,
829 831 &spr_read_ureg, SPR_NOACCESS,
830 832 0x00000000);
  833 + /* XXX : not implemented */
831 834 spr_register(env, SPR_UPMC2, "UPMC2",
832 835 &spr_read_ureg, SPR_NOACCESS,
833 836 &spr_read_ureg, SPR_NOACCESS,
834 837 0x00000000);
  838 + /* XXX : not implemented */
835 839 spr_register(env, SPR_UPMC3, "UPMC3",
836 840 &spr_read_ureg, SPR_NOACCESS,
837 841 &spr_read_ureg, SPR_NOACCESS,
838 842 0x00000000);
  843 + /* XXX : not implemented */
839 844 spr_register(env, SPR_UPMC4, "UPMC4",
840 845 &spr_read_ureg, SPR_NOACCESS,
841 846 &spr_read_ureg, SPR_NOACCESS,
842 847 0x00000000);
  848 + /* XXX : not implemented */
843 849 spr_register(env, SPR_USIAR, "USIAR",
844 850 &spr_read_ureg, SPR_NOACCESS,
845 851 &spr_read_ureg, SPR_NOACCESS,
... ... @@ -956,12 +962,14 @@ static void gen_spr_G2 (CPUPPCState *env)
956 962 {
957 963 /* Memory base address */
958 964 /* MBAR */
  965 + /* XXX : not implemented */
959 966 spr_register(env, SPR_MBAR, "MBAR",
960 967 SPR_NOACCESS, SPR_NOACCESS,
961 968 &spr_read_generic, &spr_write_generic,
962 969 0x00000000);
963 970 /* System version register */
964 971 /* SVR */
  972 + /* XXX : TODO: initialize it to an appropriate value */
965 973 spr_register(env, SPR_SVR, "SVR",
966 974 SPR_NOACCESS, SPR_NOACCESS,
967 975 &spr_read_generic, SPR_NOACCESS,
... ... @@ -1143,6 +1151,7 @@ static void gen_spr_74xx (CPUPPCState *env)
1143 1151 SPR_NOACCESS, SPR_NOACCESS,
1144 1152 &spr_read_generic, &spr_write_generic,
1145 1153 0x00000000);
  1154 + /* XXX : not implemented */
1146 1155 spr_register(env, SPR_UMMCR2, "UMMCR2",
1147 1156 &spr_read_ureg, SPR_NOACCESS,
1148 1157 &spr_read_ureg, SPR_NOACCESS,
... ... @@ -1152,10 +1161,12 @@ static void gen_spr_74xx (CPUPPCState *env)
1152 1161 SPR_NOACCESS, SPR_NOACCESS,
1153 1162 &spr_read_generic, &spr_write_generic,
1154 1163 0x00000000);
  1164 + /* XXX : not implemented */
1155 1165 spr_register(env, SPR_UBAMR, "UBAMR",
1156 1166 &spr_read_ureg, SPR_NOACCESS,
1157 1167 &spr_read_ureg, SPR_NOACCESS,
1158 1168 0x00000000);
  1169 + /* XXX : not implemented */
1159 1170 spr_register(env, SPR_MSSCR0, "MSSCR0",
1160 1171 SPR_NOACCESS, SPR_NOACCESS,
1161 1172 &spr_read_generic, &spr_write_generic,
... ... @@ -1178,7 +1189,6 @@ static void gen_spr_74xx (CPUPPCState *env)
1178 1189 0x00000000);
1179 1190 }
1180 1191  
1181   -#if defined (TODO)
1182 1192 static void gen_l3_ctrl (CPUPPCState *env)
1183 1193 {
1184 1194 /* L3CR */
... ... @@ -1188,56 +1198,64 @@ static void gen_l3_ctrl (CPUPPCState *env)
1188 1198 &spr_read_generic, &spr_write_generic,
1189 1199 0x00000000);
1190 1200 /* L3ITCR0 */
  1201 + /* XXX : not implemented */
1191 1202 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1192 1203 SPR_NOACCESS, SPR_NOACCESS,
1193 1204 &spr_read_generic, &spr_write_generic,
1194 1205 0x00000000);
1195 1206 /* L3ITCR1 */
  1207 + /* XXX : not implemented */
1196 1208 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1197 1209 SPR_NOACCESS, SPR_NOACCESS,
1198 1210 &spr_read_generic, &spr_write_generic,
1199 1211 0x00000000);
1200 1212 /* L3ITCR2 */
  1213 + /* XXX : not implemented */
1201 1214 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1202 1215 SPR_NOACCESS, SPR_NOACCESS,
1203 1216 &spr_read_generic, &spr_write_generic,
1204 1217 0x00000000);
1205 1218 /* L3ITCR3 */
  1219 + /* XXX : not implemented */
1206 1220 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1207 1221 SPR_NOACCESS, SPR_NOACCESS,
1208 1222 &spr_read_generic, &spr_write_generic,
1209 1223 0x00000000);
1210 1224 /* L3OHCR */
  1225 + /* XXX : not implemented */
1211 1226 spr_register(env, SPR_L3OHCR, "L3OHCR",
1212 1227 SPR_NOACCESS, SPR_NOACCESS,
1213 1228 &spr_read_generic, &spr_write_generic,
1214 1229 0x00000000);
1215 1230 /* L3PM */
  1231 + /* XXX : not implemented */
1216 1232 spr_register(env, SPR_L3PM, "L3PM",
1217 1233 SPR_NOACCESS, SPR_NOACCESS,
1218 1234 &spr_read_generic, &spr_write_generic,
1219 1235 0x00000000);
1220 1236 }
1221   -#endif /* TODO */
1222 1237  
1223   -#if defined (TODO)
1224   -static void gen_74xx_soft_tlb (CPUPPCState *env)
  1238 +static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1225 1239 {
1226   - /* XXX: TODO */
  1240 + env->nb_tlb = nb_tlbs;
  1241 + env->nb_ways = nb_ways;
  1242 + env->id_tlbs = 1;
  1243 + /* XXX : not implemented */
1227 1244 spr_register(env, SPR_PTEHI, "PTEHI",
1228 1245 SPR_NOACCESS, SPR_NOACCESS,
1229 1246 &spr_read_generic, &spr_write_generic,
1230 1247 0x00000000);
  1248 + /* XXX : not implemented */
1231 1249 spr_register(env, SPR_PTELO, "PTELO",
1232 1250 SPR_NOACCESS, SPR_NOACCESS,
1233 1251 &spr_read_generic, &spr_write_generic,
1234 1252 0x00000000);
  1253 + /* XXX : not implemented */
1235 1254 spr_register(env, SPR_TLBMISS, "TLBMISS",
1236 1255 SPR_NOACCESS, SPR_NOACCESS,
1237 1256 &spr_read_generic, &spr_write_generic,
1238 1257 0x00000000);
1239 1258 }
1240   -#endif /* TODO */
1241 1259  
1242 1260 /* PowerPC BookE SPR */
1243 1261 static void gen_spr_BookE (CPUPPCState *env)
... ... @@ -1491,78 +1509,92 @@ static void gen_spr_BookE (CPUPPCState *env)
1491 1509 }
1492 1510  
1493 1511 /* FSL storage control registers */
1494   -#if defined(TODO)
1495 1512 static void gen_spr_BookE_FSL (CPUPPCState *env)
1496 1513 {
1497 1514 /* TLB assist registers */
  1515 + /* XXX : not implemented */
1498 1516 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1499 1517 SPR_NOACCESS, SPR_NOACCESS,
1500 1518 &spr_read_generic, &spr_write_generic,
1501 1519 0x00000000);
  1520 + /* XXX : not implemented */
1502 1521 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1503 1522 SPR_NOACCESS, SPR_NOACCESS,
1504 1523 &spr_read_generic, &spr_write_generic,
1505 1524 0x00000000);
  1525 + /* XXX : not implemented */
1506 1526 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1507 1527 SPR_NOACCESS, SPR_NOACCESS,
1508 1528 &spr_read_generic, &spr_write_generic,
1509 1529 0x00000000);
  1530 + /* XXX : not implemented */
1510 1531 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1511 1532 SPR_NOACCESS, SPR_NOACCESS,
1512 1533 &spr_read_generic, &spr_write_generic,
1513 1534 0x00000000);
  1535 + /* XXX : not implemented */
1514 1536 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1515 1537 SPR_NOACCESS, SPR_NOACCESS,
1516 1538 &spr_read_generic, &spr_write_generic,
1517 1539 0x00000000);
  1540 + /* XXX : not implemented */
1518 1541 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1519 1542 SPR_NOACCESS, SPR_NOACCESS,
1520 1543 &spr_read_generic, &spr_write_generic,
1521 1544 0x00000000);
  1545 + /* XXX : not implemented */
1522 1546 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1523 1547 SPR_NOACCESS, SPR_NOACCESS,
1524 1548 &spr_read_generic, &spr_write_generic,
1525 1549 0x00000000);
1526 1550 if (env->nb_pids > 1) {
  1551 + /* XXX : not implemented */
1527 1552 spr_register(env, SPR_BOOKE_PID1, "PID1",
1528 1553 SPR_NOACCESS, SPR_NOACCESS,
1529 1554 &spr_read_generic, &spr_write_generic,
1530 1555 0x00000000);
1531 1556 }
1532 1557 if (env->nb_pids > 2) {
  1558 + /* XXX : not implemented */
1533 1559 spr_register(env, SPR_BOOKE_PID2, "PID2",
1534 1560 SPR_NOACCESS, SPR_NOACCESS,
1535 1561 &spr_read_generic, &spr_write_generic,
1536 1562 0x00000000);
1537 1563 }
  1564 + /* XXX : not implemented */
1538 1565 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1539 1566 SPR_NOACCESS, SPR_NOACCESS,
1540 1567 &spr_read_generic, SPR_NOACCESS,
1541 1568 0x00000000); /* TOFIX */
  1569 + /* XXX : not implemented */
1542 1570 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1543 1571 SPR_NOACCESS, SPR_NOACCESS,
1544 1572 &spr_read_generic, &spr_write_generic,
1545 1573 0x00000000); /* TOFIX */
1546 1574 switch (env->nb_ways) {
1547 1575 case 4:
  1576 + /* XXX : not implemented */
1548 1577 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1549 1578 SPR_NOACCESS, SPR_NOACCESS,
1550 1579 &spr_read_generic, SPR_NOACCESS,
1551 1580 0x00000000); /* TOFIX */
1552 1581 /* Fallthru */
1553 1582 case 3:
  1583 + /* XXX : not implemented */
1554 1584 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1555 1585 SPR_NOACCESS, SPR_NOACCESS,
1556 1586 &spr_read_generic, SPR_NOACCESS,
1557 1587 0x00000000); /* TOFIX */
1558 1588 /* Fallthru */
1559 1589 case 2:
  1590 + /* XXX : not implemented */
1560 1591 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1561 1592 SPR_NOACCESS, SPR_NOACCESS,
1562 1593 &spr_read_generic, SPR_NOACCESS,
1563 1594 0x00000000); /* TOFIX */
1564 1595 /* Fallthru */
1565 1596 case 1:
  1597 + /* XXX : not implemented */
1566 1598 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1567 1599 SPR_NOACCESS, SPR_NOACCESS,
1568 1600 &spr_read_generic, SPR_NOACCESS,
... ... @@ -1573,7 +1605,6 @@ static void gen_spr_BookE_FSL (CPUPPCState *env)
1573 1605 break;
1574 1606 }
1575 1607 }
1576   -#endif
1577 1608  
1578 1609 /* SPR specific to PowerPC 440 implementation */
1579 1610 static void gen_spr_440 (CPUPPCState *env)
... ... @@ -1730,7 +1761,7 @@ static void gen_spr_40x (CPUPPCState *env)
1730 1761 SPR_NOACCESS, SPR_NOACCESS,
1731 1762 &spr_read_generic, &spr_write_generic,
1732 1763 0x00000000);
1733   - /* XXX : not implemented */
  1764 + /* not emulated, as Qemu do not emulate caches */
1734 1765 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1735 1766 SPR_NOACCESS, SPR_NOACCESS,
1736 1767 &spr_read_generic, SPR_NOACCESS,
... ... @@ -1913,7 +1944,7 @@ static void gen_spr_401_403 (CPUPPCState *env)
1913 1944 SPR_NOACCESS, &spr_write_tbu,
1914 1945 0x00000000);
1915 1946 /* Debug */
1916   - /* XXX: not implemented */
  1947 + /* not emulated, as Qemu do not emulate caches */
1917 1948 spr_register(env, SPR_403_CDBCR, "CDBCR",
1918 1949 SPR_NOACCESS, SPR_NOACCESS,
1919 1950 &spr_read_generic, &spr_write_generic,
... ... @@ -1996,6 +2027,7 @@ static void gen_spr_403 (CPUPPCState *env)
1996 2027 SPR_NOACCESS, SPR_NOACCESS,
1997 2028 &spr_read_generic, &spr_write_generic,
1998 2029 0x00000000);
  2030 + /* XXX : not implemented */
1999 2031 spr_register(env, SPR_40x_DAC2, "DAC2",
2000 2032 SPR_NOACCESS, SPR_NOACCESS,
2001 2033 &spr_read_generic, &spr_write_generic,
... ... @@ -2005,6 +2037,7 @@ static void gen_spr_403 (CPUPPCState *env)
2005 2037 SPR_NOACCESS, SPR_NOACCESS,
2006 2038 &spr_read_generic, &spr_write_generic,
2007 2039 0x00000000);
  2040 + /* XXX : not implemented */
2008 2041 spr_register(env, SPR_40x_IAC2, "IAC2",
2009 2042 SPR_NOACCESS, SPR_NOACCESS,
2010 2043 &spr_read_generic, &spr_write_generic,
... ... @@ -2047,6 +2080,7 @@ static void gen_spr_403_mmu (CPUPPCState *env)
2047 2080 /* SPR specific to PowerPC compression coprocessor extension */
2048 2081 static void gen_spr_compress (CPUPPCState *env)
2049 2082 {
  2083 + /* XXX : not implemented */
2050 2084 spr_register(env, SPR_401_SKR, "SKR",
2051 2085 SPR_NOACCESS, SPR_NOACCESS,
2052 2086 &spr_read_generic, &spr_write_generic,
... ... @@ -2054,84 +2088,100 @@ static void gen_spr_compress (CPUPPCState *env)
2054 2088 }
2055 2089  
2056 2090 #if defined (TARGET_PPC64)
2057   -#if defined (TODO)
2058 2091 /* SPR specific to PowerPC 620 */
2059 2092 static void gen_spr_620 (CPUPPCState *env)
2060 2093 {
  2094 + /* XXX : not implemented */
2061 2095 spr_register(env, SPR_620_PMR0, "PMR0",
2062 2096 SPR_NOACCESS, SPR_NOACCESS,
2063 2097 &spr_read_generic, &spr_write_generic,
2064 2098 0x00000000);
  2099 + /* XXX : not implemented */
2065 2100 spr_register(env, SPR_620_PMR1, "PMR1",
2066 2101 SPR_NOACCESS, SPR_NOACCESS,
2067 2102 &spr_read_generic, &spr_write_generic,
2068 2103 0x00000000);
  2104 + /* XXX : not implemented */
2069 2105 spr_register(env, SPR_620_PMR2, "PMR2",
2070 2106 SPR_NOACCESS, SPR_NOACCESS,
2071 2107 &spr_read_generic, &spr_write_generic,
2072 2108 0x00000000);
  2109 + /* XXX : not implemented */
2073 2110 spr_register(env, SPR_620_PMR3, "PMR3",
2074 2111 SPR_NOACCESS, SPR_NOACCESS,
2075 2112 &spr_read_generic, &spr_write_generic,
2076 2113 0x00000000);
  2114 + /* XXX : not implemented */
2077 2115 spr_register(env, SPR_620_PMR4, "PMR4",
2078 2116 SPR_NOACCESS, SPR_NOACCESS,
2079 2117 &spr_read_generic, &spr_write_generic,
2080 2118 0x00000000);
  2119 + /* XXX : not implemented */
2081 2120 spr_register(env, SPR_620_PMR5, "PMR5",
2082 2121 SPR_NOACCESS, SPR_NOACCESS,
2083 2122 &spr_read_generic, &spr_write_generic,
2084 2123 0x00000000);
  2124 + /* XXX : not implemented */
2085 2125 spr_register(env, SPR_620_PMR6, "PMR6",
2086 2126 SPR_NOACCESS, SPR_NOACCESS,
2087 2127 &spr_read_generic, &spr_write_generic,
2088 2128 0x00000000);
  2129 + /* XXX : not implemented */
2089 2130 spr_register(env, SPR_620_PMR7, "PMR7",
2090 2131 SPR_NOACCESS, SPR_NOACCESS,
2091 2132 &spr_read_generic, &spr_write_generic,
2092 2133 0x00000000);
  2134 + /* XXX : not implemented */
2093 2135 spr_register(env, SPR_620_PMR8, "PMR8",
2094 2136 SPR_NOACCESS, SPR_NOACCESS,
2095 2137 &spr_read_generic, &spr_write_generic,
2096 2138 0x00000000);
  2139 + /* XXX : not implemented */
2097 2140 spr_register(env, SPR_620_PMR9, "PMR9",
2098 2141 SPR_NOACCESS, SPR_NOACCESS,
2099 2142 &spr_read_generic, &spr_write_generic,
2100 2143 0x00000000);
  2144 + /* XXX : not implemented */
2101 2145 spr_register(env, SPR_620_PMRA, "PMR10",
2102 2146 SPR_NOACCESS, SPR_NOACCESS,
2103 2147 &spr_read_generic, &spr_write_generic,
2104 2148 0x00000000);
  2149 + /* XXX : not implemented */
2105 2150 spr_register(env, SPR_620_PMRB, "PMR11",
2106 2151 SPR_NOACCESS, SPR_NOACCESS,
2107 2152 &spr_read_generic, &spr_write_generic,
2108 2153 0x00000000);
  2154 + /* XXX : not implemented */
2109 2155 spr_register(env, SPR_620_PMRC, "PMR12",
2110 2156 SPR_NOACCESS, SPR_NOACCESS,
2111 2157 &spr_read_generic, &spr_write_generic,
2112 2158 0x00000000);
  2159 + /* XXX : not implemented */
2113 2160 spr_register(env, SPR_620_PMRD, "PMR13",
2114 2161 SPR_NOACCESS, SPR_NOACCESS,
2115 2162 &spr_read_generic, &spr_write_generic,
2116 2163 0x00000000);
  2164 + /* XXX : not implemented */
2117 2165 spr_register(env, SPR_620_PMRE, "PMR14",
2118 2166 SPR_NOACCESS, SPR_NOACCESS,
2119 2167 &spr_read_generic, &spr_write_generic,
2120 2168 0x00000000);
  2169 + /* XXX : not implemented */
2121 2170 spr_register(env, SPR_620_PMRF, "PMR15",
2122 2171 SPR_NOACCESS, SPR_NOACCESS,
2123 2172 &spr_read_generic, &spr_write_generic,
2124 2173 0x00000000);
  2174 + /* XXX : not implemented */
2125 2175 spr_register(env, SPR_620_HID8, "HID8",
2126 2176 SPR_NOACCESS, SPR_NOACCESS,
2127 2177 &spr_read_generic, &spr_write_generic,
2128 2178 0x00000000);
  2179 + /* XXX : not implemented */
2129 2180 spr_register(env, SPR_620_HID9, "HID9",
2130 2181 SPR_NOACCESS, SPR_NOACCESS,
2131 2182 &spr_read_generic, &spr_write_generic,
2132 2183 0x00000000);
2133 2184 }
2134   -#endif
2135 2185 #endif /* defined (TARGET_PPC64) */
2136 2186  
2137 2187 // XXX: TODO
... ... @@ -2141,7 +2191,6 @@ static void gen_spr_620 (CPUPPCState *env)
2141 2191 * CTRL => SPR 152 (Power 2.04)
2142 2192 * SCOMC => SPR 276 (64 bits ?)
2143 2193 * SCOMD => SPR 277 (64 bits ?)
2144   - * ASR => SPR 280 (64 bits)
2145 2194 * TBU40 => SPR 286 (Power 2.04 hypv)
2146 2195 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2147 2196 * HSPRG1 => SPR 305 (Power 2.04 hypv)
... ... @@ -2157,8 +2206,6 @@ static void gen_spr_620 (CPUPPCState *env)
2157 2206 * LPCR => SPR 316 (970)
2158 2207 * LPIDR => SPR 317 (970)
2159 2208 * SPEFSCR => SPR 512 (Power 2.04 emb)
2160   - * ATBL => SPR 526 (Power 2.04 emb)
2161   - * ATBU => SPR 527 (Power 2.04 emb)
2162 2209 * EPR => SPR 702 (Power 2.04 emb)
2163 2210 * perf => 768-783 (Power 2.04)
2164 2211 * perf => 784-799 (Power 2.04)
... ... @@ -2349,7 +2396,7 @@ static void init_excp_604 (CPUPPCState *env)
2349 2396 #endif
2350 2397 }
2351 2398  
2352   -#if defined (TODO)
  2399 +#if defined(TARGET_PPC64)
2353 2400 static void init_excp_620 (CPUPPCState *env)
2354 2401 {
2355 2402 #if !defined(CONFIG_USER_ONLY)
... ... @@ -2370,7 +2417,7 @@ static void init_excp_620 (CPUPPCState *env)
2370 2417 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2371 2418 #endif
2372 2419 }
2373   -#endif /* defined (TODO) */
  2420 +#endif /* defined(TARGET_PPC64) */
2374 2421  
2375 2422 static void init_excp_7x0 (CPUPPCState *env)
2376 2423 {
... ... @@ -2436,7 +2483,6 @@ static void init_excp_7400 (CPUPPCState *env)
2436 2483 #endif
2437 2484 }
2438 2485  
2439   -#if defined (TODO)
2440 2486 static void init_excp_7450 (CPUPPCState *env)
2441 2487 {
2442 2488 #if !defined(CONFIG_USER_ONLY)
... ... @@ -2461,7 +2507,6 @@ static void init_excp_7450 (CPUPPCState *env)
2461 2507 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2462 2508 #endif
2463 2509 }
2464   -#endif /* defined (TODO) */
2465 2510  
2466 2511 #if defined (TARGET_PPC64)
2467 2512 static void init_excp_970 (CPUPPCState *env)
... ... @@ -2547,7 +2592,6 @@ static void init_proc_401x2 (CPUPPCState *env)
2547 2592 }
2548 2593  
2549 2594 /* PowerPC 401x3 */
2550   -#if defined(TODO)
2551 2595 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2552 2596 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2553 2597 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
... ... @@ -2559,6 +2603,7 @@ static void init_proc_401x2 (CPUPPCState *env)
2559 2603 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2560 2604 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2561 2605  
  2606 +__attribute__ (( unused ))
2562 2607 static void init_proc_401x3 (CPUPPCState *env)
2563 2608 {
2564 2609 gen_spr_40x(env);
... ... @@ -2570,7 +2615,6 @@ static void init_proc_401x3 (CPUPPCState *env)
2570 2615 /* Allocate hardware IRQ controller */
2571 2616 ppc40x_irq_init(env);
2572 2617 }
2573   -#endif /* TODO */
2574 2618  
2575 2619 /* IOP480 */
2576 2620 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
... ... @@ -2714,6 +2758,7 @@ static void init_proc_440EP (CPUPPCState *env)
2714 2758 gen_tbl(env);
2715 2759 gen_spr_BookE(env);
2716 2760 gen_spr_440(env);
  2761 + /* XXX : not implemented */
2717 2762 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2718 2763 SPR_NOACCESS, SPR_NOACCESS,
2719 2764 &spr_read_generic, &spr_write_generic,
... ... @@ -2726,6 +2771,7 @@ static void init_proc_440EP (CPUPPCState *env)
2726 2771 SPR_NOACCESS, SPR_NOACCESS,
2727 2772 &spr_read_generic, &spr_write_generic,
2728 2773 0x00000000);
  2774 + /* XXX : not implemented */
2729 2775 spr_register(env, SPR_440_CCR1, "CCR1",
2730 2776 SPR_NOACCESS, SPR_NOACCESS,
2731 2777 &spr_read_generic, &spr_write_generic,
... ... @@ -2764,7 +2810,6 @@ static void init_proc_440GP (CPUPPCState *env)
2764 2810 }
2765 2811  
2766 2812 /* PowerPC 440x4 */
2767   -#if defined(TODO)
2768 2813 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2769 2814 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2770 2815 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
... ... @@ -2775,6 +2820,7 @@ static void init_proc_440GP (CPUPPCState *env)
2775 2820 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2776 2821 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2777 2822  
  2823 +__attribute__ (( unused ))
2778 2824 static void init_proc_440x4 (CPUPPCState *env)
2779 2825 {
2780 2826 /* Time base */
... ... @@ -2788,7 +2834,6 @@ static void init_proc_440x4 (CPUPPCState *env)
2788 2834 init_excp_BookE(env);
2789 2835 /* XXX: TODO: allocate internal IRQ controller */
2790 2836 }
2791   -#endif /* TODO */
2792 2837  
2793 2838 /* PowerPC 440x5 */
2794 2839 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
... ... @@ -2807,6 +2852,7 @@ static void init_proc_440x5 (CPUPPCState *env)
2807 2852 gen_tbl(env);
2808 2853 gen_spr_BookE(env);
2809 2854 gen_spr_440(env);
  2855 + /* XXX : not implemented */
2810 2856 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2811 2857 SPR_NOACCESS, SPR_NOACCESS,
2812 2858 &spr_read_generic, &spr_write_generic,
... ... @@ -2819,6 +2865,7 @@ static void init_proc_440x5 (CPUPPCState *env)
2819 2865 SPR_NOACCESS, SPR_NOACCESS,
2820 2866 &spr_read_generic, &spr_write_generic,
2821 2867 0x00000000);
  2868 + /* XXX : not implemented */
2822 2869 spr_register(env, SPR_440_CCR1, "CCR1",
2823 2870 SPR_NOACCESS, SPR_NOACCESS,
2824 2871 &spr_read_generic, &spr_write_generic,
... ... @@ -2832,8 +2879,7 @@ static void init_proc_440x5 (CPUPPCState *env)
2832 2879 }
2833 2880  
2834 2881 /* PowerPC 460 (guessed) */
2835   -#if defined(TODO)
2836   -#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
  2882 +#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
2837 2883 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2838 2884 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2839 2885 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
... ... @@ -2843,12 +2889,14 @@ static void init_proc_440x5 (CPUPPCState *env)
2843 2889 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2844 2890 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
2845 2891  
  2892 +__attribute__ (( unused ))
2846 2893 static void init_proc_460 (CPUPPCState *env)
2847 2894 {
2848 2895 /* Time base */
2849 2896 gen_tbl(env);
2850 2897 gen_spr_BookE(env);
2851 2898 gen_spr_440(env);
  2899 + /* XXX : not implemented */
2852 2900 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2853 2901 SPR_NOACCESS, SPR_NOACCESS,
2854 2902 &spr_read_generic, &spr_write_generic,
... ... @@ -2861,10 +2909,12 @@ static void init_proc_460 (CPUPPCState *env)
2861 2909 SPR_NOACCESS, SPR_NOACCESS,
2862 2910 &spr_read_generic, &spr_write_generic,
2863 2911 0x00000000);
  2912 + /* XXX : not implemented */
2864 2913 spr_register(env, SPR_440_CCR1, "CCR1",
2865 2914 SPR_NOACCESS, SPR_NOACCESS,
2866 2915 &spr_read_generic, &spr_write_generic,
2867 2916 0x00000000);
  2917 + /* XXX : not implemented */
2868 2918 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2869 2919 &spr_read_generic, &spr_write_generic,
2870 2920 &spr_read_generic, &spr_write_generic,
... ... @@ -2876,10 +2926,8 @@ static void init_proc_460 (CPUPPCState *env)
2876 2926 init_excp_BookE(env);
2877 2927 /* XXX: TODO: allocate internal IRQ controller */
2878 2928 }
2879   -#endif /* TODO */
2880 2929  
2881 2930 /* PowerPC 460F (guessed) */
2882   -#if defined(TODO)
2883 2931 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2884 2932 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2885 2933 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
... ... @@ -2893,12 +2941,14 @@ static void init_proc_460 (CPUPPCState *env)
2893 2941 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
2894 2942 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
2895 2943  
  2944 +__attribute__ (( unused ))
2896 2945 static void init_proc_460F (CPUPPCState *env)
2897 2946 {
2898 2947 /* Time base */
2899 2948 gen_tbl(env);
2900 2949 gen_spr_BookE(env);
2901 2950 gen_spr_440(env);
  2951 + /* XXX : not implemented */
2902 2952 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2903 2953 SPR_NOACCESS, SPR_NOACCESS,
2904 2954 &spr_read_generic, &spr_write_generic,
... ... @@ -2911,10 +2961,12 @@ static void init_proc_460F (CPUPPCState *env)
2911 2961 SPR_NOACCESS, SPR_NOACCESS,
2912 2962 &spr_read_generic, &spr_write_generic,
2913 2963 0x00000000);
  2964 + /* XXX : not implemented */
2914 2965 spr_register(env, SPR_440_CCR1, "CCR1",
2915 2966 SPR_NOACCESS, SPR_NOACCESS,
2916 2967 &spr_read_generic, &spr_write_generic,
2917 2968 0x00000000);
  2969 + /* XXX : not implemented */
2918 2970 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2919 2971 &spr_read_generic, &spr_write_generic,
2920 2972 &spr_read_generic, &spr_write_generic,
... ... @@ -2926,10 +2978,8 @@ static void init_proc_460F (CPUPPCState *env)
2926 2978 init_excp_BookE(env);
2927 2979 /* XXX: TODO: allocate internal IRQ controller */
2928 2980 }
2929   -#endif /* TODO */
2930 2981  
2931 2982 /* Generic BookE PowerPC */
2932   -#if defined(TODO)
2933 2983 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
2934 2984 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2935 2985 PPC_CACHE_DCBA | \
... ... @@ -2943,22 +2993,17 @@ static void init_proc_460F (CPUPPCState *env)
2943 2993 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
2944 2994 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
2945 2995  
  2996 +__attribute__ (( unused ))
2946 2997 static void init_proc_BookE (CPUPPCState *env)
2947 2998 {
2948 2999 init_excp_BookE(env);
2949 3000 }
2950   -#endif /* TODO */
2951 3001  
2952 3002 /* e200 core */
2953   -#if defined(TODO)
2954   -#endif /* TODO */
2955 3003  
2956 3004 /* e300 core */
2957   -#if defined(TODO)
2958   -#endif /* TODO */
2959 3005  
2960 3006 /* e500 core */
2961   -#if defined(TODO)
2962 3007 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
2963 3008 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2964 3009 PPC_CACHE_DCBA | \
... ... @@ -2968,6 +3013,7 @@ static void init_proc_BookE (CPUPPCState *env)
2968 3013 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
2969 3014 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
2970 3015  
  3016 +__attribute__ (( unused ))
2971 3017 static void init_proc_e500 (CPUPPCState *env)
2972 3018 {
2973 3019 /* Time base */
... ... @@ -2981,11 +3027,8 @@ static void init_proc_e500 (CPUPPCState *env)
2981 3027 init_excp_BookE(env);
2982 3028 /* XXX: TODO: allocate internal IRQ controller */
2983 3029 }
2984   -#endif /* TODO */
2985 3030  
2986 3031 /* e600 core */
2987   -#if defined(TODO)
2988   -#endif /* TODO */
2989 3032  
2990 3033 /* Non-embedded PowerPC */
2991 3034 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
... ... @@ -3461,7 +3504,6 @@ static void init_proc_7410 (CPUPPCState *env)
3461 3504 }
3462 3505  
3463 3506 /* PowerPC 7440 (aka G4) */
3464   -#if defined (TODO)
3465 3507 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3466 3508 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3467 3509 PPC_ALTIVEC)
... ... @@ -3471,6 +3513,7 @@ static void init_proc_7410 (CPUPPCState *env)
3471 3513 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3472 3514 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3473 3515  
  3516 +__attribute__ (( unused ))
3474 3517 static void init_proc_7440 (CPUPPCState *env)
3475 3518 {
3476 3519 gen_spr_ne_601(env);
... ... @@ -3492,6 +3535,7 @@ static void init_proc_7440 (CPUPPCState *env)
3492 3535 &spr_read_generic, &spr_write_generic,
3493 3536 0x00000000);
3494 3537 /* MSSSR0 */
  3538 + /* XXX : not implemented */
3495 3539 spr_register(env, SPR_MSSSR0, "MSSSR0",
3496 3540 SPR_NOACCESS, SPR_NOACCESS,
3497 3541 &spr_read_generic, &spr_write_generic,
... ... @@ -3502,28 +3546,29 @@ static void init_proc_7440 (CPUPPCState *env)
3502 3546 SPR_NOACCESS, SPR_NOACCESS,
3503 3547 &spr_read_generic, &spr_write_generic,
3504 3548 0x00000000);
  3549 + /* XXX : not implemented */
3505 3550 spr_register(env, SPR_UPMC5, "UPMC5",
3506 3551 &spr_read_ureg, SPR_NOACCESS,
3507 3552 &spr_read_ureg, SPR_NOACCESS,
3508 3553 0x00000000);
  3554 + /* XXX : not implemented */
3509 3555 spr_register(env, SPR_PMC6, "PMC6",
3510 3556 SPR_NOACCESS, SPR_NOACCESS,
3511 3557 &spr_read_generic, &spr_write_generic,
3512 3558 0x00000000);
  3559 + /* XXX : not implemented */
3513 3560 spr_register(env, SPR_UPMC6, "UPMC6",
3514 3561 &spr_read_ureg, SPR_NOACCESS,
3515 3562 &spr_read_ureg, SPR_NOACCESS,
3516 3563 0x00000000);
3517 3564 /* Memory management */
3518 3565 gen_low_BATs(env);
3519   - gen_74xx_soft_tlb(env);
  3566 + gen_74xx_soft_tlb(env, 128, 2);
3520 3567 /* Allocate hardware IRQ controller */
3521 3568 ppc6xx_irq_init(env);
3522 3569 }
3523   -#endif /* TODO */
3524 3570  
3525 3571 /* PowerPC 7450 (aka G4) */
3526   -#if defined (TODO)
3527 3572 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3528 3573 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3529 3574 PPC_ALTIVEC)
... ... @@ -3533,6 +3578,7 @@ static void init_proc_7440 (CPUPPCState *env)
3533 3578 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3534 3579 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3535 3580  
  3581 +__attribute__ (( unused ))
3536 3582 static void init_proc_7450 (CPUPPCState *env)
3537 3583 {
3538 3584 gen_spr_ne_601(env);
... ... @@ -3556,6 +3602,7 @@ static void init_proc_7450 (CPUPPCState *env)
3556 3602 &spr_read_generic, &spr_write_generic,
3557 3603 0x00000000);
3558 3604 /* MSSSR0 */
  3605 + /* XXX : not implemented */
3559 3606 spr_register(env, SPR_MSSSR0, "MSSSR0",
3560 3607 SPR_NOACCESS, SPR_NOACCESS,
3561 3608 &spr_read_generic, &spr_write_generic,
... ... @@ -3566,29 +3613,30 @@ static void init_proc_7450 (CPUPPCState *env)
3566 3613 SPR_NOACCESS, SPR_NOACCESS,
3567 3614 &spr_read_generic, &spr_write_generic,
3568 3615 0x00000000);
  3616 + /* XXX : not implemented */
3569 3617 spr_register(env, SPR_UPMC5, "UPMC5",
3570 3618 &spr_read_ureg, SPR_NOACCESS,
3571 3619 &spr_read_ureg, SPR_NOACCESS,
3572 3620 0x00000000);
  3621 + /* XXX : not implemented */
3573 3622 spr_register(env, SPR_PMC6, "PMC6",
3574 3623 SPR_NOACCESS, SPR_NOACCESS,
3575 3624 &spr_read_generic, &spr_write_generic,
3576 3625 0x00000000);
  3626 + /* XXX : not implemented */
3577 3627 spr_register(env, SPR_UPMC6, "UPMC6",
3578 3628 &spr_read_ureg, SPR_NOACCESS,
3579 3629 &spr_read_ureg, SPR_NOACCESS,
3580 3630 0x00000000);
3581 3631 /* Memory management */
3582 3632 gen_low_BATs(env);
3583   - gen_74xx_soft_tlb(env);
  3633 + gen_74xx_soft_tlb(env, 128, 2);
3584 3634 init_excp_7450(env);
3585 3635 /* Allocate hardware IRQ controller */
3586 3636 ppc6xx_irq_init(env);
3587 3637 }
3588   -#endif /* TODO */
3589 3638  
3590 3639 /* PowerPC 7445 (aka G4) */
3591   -#if defined (TODO)
3592 3640 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3593 3641 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3594 3642 PPC_ALTIVEC)
... ... @@ -3598,6 +3646,7 @@ static void init_proc_7450 (CPUPPCState *env)
3598 3646 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3599 3647 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3600 3648  
  3649 +__attribute__ (( unused ))
3601 3650 static void init_proc_7445 (CPUPPCState *env)
3602 3651 {
3603 3652 gen_spr_ne_601(env);
... ... @@ -3619,6 +3668,7 @@ static void init_proc_7445 (CPUPPCState *env)
3619 3668 &spr_read_generic, &spr_write_generic,
3620 3669 0x00000000);
3621 3670 /* MSSSR0 */
  3671 + /* XXX : not implemented */
3622 3672 spr_register(env, SPR_MSSSR0, "MSSSR0",
3623 3673 SPR_NOACCESS, SPR_NOACCESS,
3624 3674 &spr_read_generic, &spr_write_generic,
... ... @@ -3629,14 +3679,17 @@ static void init_proc_7445 (CPUPPCState *env)
3629 3679 SPR_NOACCESS, SPR_NOACCESS,
3630 3680 &spr_read_generic, &spr_write_generic,
3631 3681 0x00000000);
  3682 + /* XXX : not implemented */
3632 3683 spr_register(env, SPR_UPMC5, "UPMC5",
3633 3684 &spr_read_ureg, SPR_NOACCESS,
3634 3685 &spr_read_ureg, SPR_NOACCESS,
3635 3686 0x00000000);
  3687 + /* XXX : not implemented */
3636 3688 spr_register(env, SPR_PMC6, "PMC6",
3637 3689 SPR_NOACCESS, SPR_NOACCESS,
3638 3690 &spr_read_generic, &spr_write_generic,
3639 3691 0x00000000);
  3692 + /* XXX : not implemented */
3640 3693 spr_register(env, SPR_UPMC6, "UPMC6",
3641 3694 &spr_read_ureg, SPR_NOACCESS,
3642 3695 &spr_read_ureg, SPR_NOACCESS,
... ... @@ -3677,15 +3730,13 @@ static void init_proc_7445 (CPUPPCState *env)
3677 3730 /* Memory management */
3678 3731 gen_low_BATs(env);
3679 3732 gen_high_BATs(env);
3680   - gen_74xx_soft_tlb(env);
  3733 + gen_74xx_soft_tlb(env, 128, 2);
3681 3734 init_excp_7450(env);
3682 3735 /* Allocate hardware IRQ controller */
3683 3736 ppc6xx_irq_init(env);
3684 3737 }
3685   -#endif /* TODO */
3686 3738  
3687 3739 /* PowerPC 7455 (aka G4) */
3688   -#if defined (TODO)
3689 3740 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3690 3741 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3691 3742 PPC_ALTIVEC)
... ... @@ -3695,6 +3746,7 @@ static void init_proc_7445 (CPUPPCState *env)
3695 3746 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3696 3747 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3697 3748  
  3749 +__attribute__ (( unused ))
3698 3750 static void init_proc_7455 (CPUPPCState *env)
3699 3751 {
3700 3752 gen_spr_ne_601(env);
... ... @@ -3718,6 +3770,7 @@ static void init_proc_7455 (CPUPPCState *env)
3718 3770 &spr_read_generic, &spr_write_generic,
3719 3771 0x00000000);
3720 3772 /* MSSSR0 */
  3773 + /* XXX : not implemented */
3721 3774 spr_register(env, SPR_MSSSR0, "MSSSR0",
3722 3775 SPR_NOACCESS, SPR_NOACCESS,
3723 3776 &spr_read_generic, &spr_write_generic,
... ... @@ -3728,14 +3781,17 @@ static void init_proc_7455 (CPUPPCState *env)
3728 3781 SPR_NOACCESS, SPR_NOACCESS,
3729 3782 &spr_read_generic, &spr_write_generic,
3730 3783 0x00000000);
  3784 + /* XXX : not implemented */
3731 3785 spr_register(env, SPR_UPMC5, "UPMC5",
3732 3786 &spr_read_ureg, SPR_NOACCESS,
3733 3787 &spr_read_ureg, SPR_NOACCESS,
3734 3788 0x00000000);
  3789 + /* XXX : not implemented */
3735 3790 spr_register(env, SPR_PMC6, "PMC6",
3736 3791 SPR_NOACCESS, SPR_NOACCESS,
3737 3792 &spr_read_generic, &spr_write_generic,
3738 3793 0x00000000);
  3794 + /* XXX : not implemented */
3739 3795 spr_register(env, SPR_UPMC6, "UPMC6",
3740 3796 &spr_read_ureg, SPR_NOACCESS,
3741 3797 &spr_read_ureg, SPR_NOACCESS,
... ... @@ -3776,12 +3832,11 @@ static void init_proc_7455 (CPUPPCState *env)
3776 3832 /* Memory management */
3777 3833 gen_low_BATs(env);
3778 3834 gen_high_BATs(env);
3779   - gen_74xx_soft_tlb(env);
  3835 + gen_74xx_soft_tlb(env, 128, 2);
3780 3836 init_excp_7450(env);
3781 3837 /* Allocate hardware IRQ controller */
3782 3838 ppc6xx_irq_init(env);
3783 3839 }
3784   -#endif /* TODO */
3785 3840  
3786 3841 #if defined (TARGET_PPC64)
3787 3842 /* PowerPC 970 */
... ... @@ -3914,7 +3969,6 @@ static void init_proc_970GX (CPUPPCState *env)
3914 3969 }
3915 3970  
3916 3971 /* PowerPC 620 */
3917   -#if defined (TODO)
3918 3972 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3919 3973 PPC_64B | PPC_SLBI)
3920 3974 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
... ... @@ -3923,6 +3977,7 @@ static void init_proc_970GX (CPUPPCState *env)
3923 3977 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
3924 3978 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
3925 3979  
  3980 +__attribute__ (( unused ))
3926 3981 static void init_proc_620 (CPUPPCState *env)
3927 3982 {
3928 3983 gen_spr_ne_601(env);
... ... @@ -3941,7 +3996,6 @@ static void init_proc_620 (CPUPPCState *env)
3941 3996 init_excp_620(env);
3942 3997 /* XXX: TODO: initialize internal interrupt controller */
3943 3998 }
3944   -#endif /* TODO */
3945 3999 #endif /* defined (TARGET_PPC64) */
3946 4000  
3947 4001 /* Default 32 bits PowerPC target will be 604 */
... ...