gwj / at91sam9263 · Commits

Commit 5747c0733dd7ebbaa7a719d5cb1cd22565cb0cb0

Authored by pbrook
1 parent 02ce600c

Fix int/float inconsistencies. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 34 additions and 36 deletions
target-mips/fop_template.c
  View file @5747c07
@@ -24,14 +24,14 @@ @@ -24,14 +24,14 @@
24 #define OP_WLOAD_FREG(treg, tregname, FREG) \ 24 #define OP_WLOAD_FREG(treg, tregname, FREG) \
25 void glue(glue(op_load_fpr_,tregname), FREG) (void) \ 25 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
26 { \ 26 { \
27 - treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX]; \ 27 + treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX]; \
28 FORCE_RET(); \ 28 FORCE_RET(); \
29 } 29 }
30 30
31 #define OP_WSTORE_FREG(treg, tregname, FREG) \ 31 #define OP_WSTORE_FREG(treg, tregname, FREG) \
32 void glue(glue(op_store_fpr_,tregname), FREG) (void) \ 32 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
33 { \ 33 { \
34 - env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg; \ 34 + env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg; \
35 FORCE_RET(); \ 35 FORCE_RET(); \
36 } 36 }
37 37
@@ -50,10 +50,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG) @@ -50,10 +50,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
50 void glue(glue(op_load_fpr_,tregname), FREG) (void) \ 50 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
51 { \ 51 { \
52 if (env->hflags & MIPS_HFLAG_F64) \ 52 if (env->hflags & MIPS_HFLAG_F64) \
53 - treg = env->fpu->fpr[FREG].fd; \ 53 + treg = env->fpu->fpr[FREG].d; \
54 else \ 54 else \
55 - treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \  
56 - env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \ 55 + treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \
  56 + env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \
57 FORCE_RET(); \ 57 FORCE_RET(); \
58 } 58 }
59 59
@@ -61,10 +61,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG) @@ -61,10 +61,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
61 void glue(glue(op_store_fpr_,tregname), FREG) (void) \ 61 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
62 { \ 62 { \
63 if (env->hflags & MIPS_HFLAG_F64) \ 63 if (env->hflags & MIPS_HFLAG_F64) \
64 - env->fpu->fpr[FREG].fd = treg; \ 64 + env->fpu->fpr[FREG].d = treg; \
65 else { \ 65 else { \
66 - env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \  
67 - env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg; \ 66 + env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \
  67 + env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg; \
68 } \ 68 } \
69 FORCE_RET(); \ 69 FORCE_RET(); \
70 } 70 }
@@ -81,14 +81,14 @@ OP_DSTORE_FREG(DT2, DT2_fpr, FREG) @@ -81,14 +81,14 @@ OP_DSTORE_FREG(DT2, DT2_fpr, FREG)
81 #define OP_PSLOAD_FREG(treg, tregname, FREG) \ 81 #define OP_PSLOAD_FREG(treg, tregname, FREG) \
82 void glue(glue(op_load_fpr_,tregname), FREG) (void) \ 82 void glue(glue(op_load_fpr_,tregname), FREG) (void) \
83 { \ 83 { \
84 - treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX]; \ 84 + treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX]; \
85 FORCE_RET(); \ 85 FORCE_RET(); \
86 } 86 }
87 87
88 #define OP_PSSTORE_FREG(treg, tregname, FREG) \ 88 #define OP_PSSTORE_FREG(treg, tregname, FREG) \
89 void glue(glue(op_store_fpr_,tregname), FREG) (void) \ 89 void glue(glue(op_store_fpr_,tregname), FREG) (void) \
90 { \ 90 { \
91 - env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg; \ 91 + env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg; \
92 FORCE_RET(); \ 92 FORCE_RET(); \
93 } 93 }
94 94
target-mips/op.c
  View file @5747c07
@@ -2682,7 +2682,7 @@ FLOAT_OP(n ## name1 ## name2, d) \ @@ -2682,7 +2682,7 @@ FLOAT_OP(n ## name1 ## name2, d) \
2682 { \ 2682 { \
2683 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ 2683 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2684 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ 2684 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2685 - FDT2 ^= 1ULL << 63; \ 2685 + FDT2 = float64_chs(FDT2); \
2686 DEBUG_FPU_STATE(); \ 2686 DEBUG_FPU_STATE(); \
2687 FORCE_RET(); \ 2687 FORCE_RET(); \
2688 } \ 2688 } \
@@ -2690,7 +2690,7 @@ FLOAT_OP(n ## name1 ## name2, s) \ @@ -2690,7 +2690,7 @@ FLOAT_OP(n ## name1 ## name2, s) \
2690 { \ 2690 { \
2691 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ 2691 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2692 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ 2692 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2693 - FST2 ^= 1 << 31; \ 2693 + FST2 = float32_chs(FST2); \
2694 DEBUG_FPU_STATE(); \ 2694 DEBUG_FPU_STATE(); \
2695 FORCE_RET(); \ 2695 FORCE_RET(); \
2696 } \ 2696 } \
@@ -2700,8 +2700,8 @@ FLOAT_OP(n ## name1 ## name2, ps) \ @@ -2700,8 +2700,8 @@ FLOAT_OP(n ## name1 ## name2, ps) \
2700 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ 2700 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2701 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ 2701 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2702 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ 2702 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2703 - FST2 ^= 1 << 31; \  
2704 - FSTH2 ^= 1 << 31; \ 2703 + FST2 = float32_chs(FST2); \
  2704 + FSTH2 = float32_chs(FSTH2); \
2705 DEBUG_FPU_STATE(); \ 2705 DEBUG_FPU_STATE(); \
2706 FORCE_RET(); \ 2706 FORCE_RET(); \
2707 } 2707 }
target-mips/op_helper.c
  View file @5747c07
@@ -626,8 +626,6 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, @@ -626,8 +626,6 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
626 626
627 /* Complex FPU operations which may need stack space. */ 627 /* Complex FPU operations which may need stack space. */
628 628
629 -#define FLOAT_SIGN32 (1 << 31)  
630 -#define FLOAT_SIGN64 (1ULL << 63)  
631 #define FLOAT_ONE32 (0x3f8 << 20) 629 #define FLOAT_ONE32 (0x3f8 << 20)
632 #define FLOAT_ONE64 (0x3ffULL << 52) 630 #define FLOAT_ONE64 (0x3ffULL << 52)
633 #define FLOAT_TWO32 (1 << 30) 631 #define FLOAT_TWO32 (1 << 30)
@@ -1054,7 +1052,7 @@ FLOAT_OP(name, d) \ @@ -1054,7 +1052,7 @@ FLOAT_OP(name, d) \
1054 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ 1052 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1055 update_fcr31(); \ 1053 update_fcr31(); \
1056 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \ 1054 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1057 - FDT2 = FLOAT_QNAN64; \ 1055 + DT2 = FLOAT_QNAN64; \
1058 } \ 1056 } \
1059 FLOAT_OP(name, s) \ 1057 FLOAT_OP(name, s) \
1060 { \ 1058 { \
@@ -1062,7 +1060,7 @@ FLOAT_OP(name, s) \ @@ -1062,7 +1060,7 @@ FLOAT_OP(name, s) \
1062 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ 1060 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1063 update_fcr31(); \ 1061 update_fcr31(); \
1064 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \ 1062 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1065 - FST2 = FLOAT_QNAN32; \ 1063 + WT2 = FLOAT_QNAN32; \
1066 } \ 1064 } \
1067 FLOAT_OP(name, ps) \ 1065 FLOAT_OP(name, ps) \
1068 { \ 1066 { \
@@ -1071,8 +1069,8 @@ FLOAT_OP(name, ps) \ @@ -1071,8 +1069,8 @@ FLOAT_OP(name, ps) \
1071 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ 1069 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1072 update_fcr31(); \ 1070 update_fcr31(); \
1073 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \ 1071 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1074 - FST2 = FLOAT_QNAN32; \  
1075 - FSTH2 = FLOAT_QNAN32; \ 1072 + WT2 = FLOAT_QNAN32; \
  1073 + WTH2 = FLOAT_QNAN32; \
1076 } \ 1074 } \
1077 } 1075 }
1078 FLOAT_BINOP(add) 1076 FLOAT_BINOP(add)
@@ -1086,14 +1084,14 @@ FLOAT_OP(recip2, d) @@ -1086,14 +1084,14 @@ FLOAT_OP(recip2, d)
1086 { 1084 {
1087 set_float_exception_flags(0, &env->fpu->fp_status); 1085 set_float_exception_flags(0, &env->fpu->fp_status);
1088 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); 1086 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1089 - FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64; 1087 + FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
1090 update_fcr31(); 1088 update_fcr31();
1091 } 1089 }
1092 FLOAT_OP(recip2, s) 1090 FLOAT_OP(recip2, s)
1093 { 1091 {
1094 set_float_exception_flags(0, &env->fpu->fp_status); 1092 set_float_exception_flags(0, &env->fpu->fp_status);
1095 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); 1093 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1096 - FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; 1094 + FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1097 update_fcr31(); 1095 update_fcr31();
1098 } 1096 }
1099 FLOAT_OP(recip2, ps) 1097 FLOAT_OP(recip2, ps)
@@ -1101,8 +1099,8 @@ FLOAT_OP(recip2, ps) @@ -1101,8 +1099,8 @@ FLOAT_OP(recip2, ps)
1101 set_float_exception_flags(0, &env->fpu->fp_status); 1099 set_float_exception_flags(0, &env->fpu->fp_status);
1102 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); 1100 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1103 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); 1101 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1104 - FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;  
1105 - FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; 1102 + FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
  1103 + FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
1106 update_fcr31(); 1104 update_fcr31();
1107 } 1105 }
1108 1106
@@ -1111,7 +1109,7 @@ FLOAT_OP(rsqrt2, d) @@ -1111,7 +1109,7 @@ FLOAT_OP(rsqrt2, d)
1111 set_float_exception_flags(0, &env->fpu->fp_status); 1109 set_float_exception_flags(0, &env->fpu->fp_status);
1112 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); 1110 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1113 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status); 1111 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1114 - FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64; 1112 + FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
1115 update_fcr31(); 1113 update_fcr31();
1116 } 1114 }
1117 FLOAT_OP(rsqrt2, s) 1115 FLOAT_OP(rsqrt2, s)
@@ -1119,7 +1117,7 @@ FLOAT_OP(rsqrt2, s) @@ -1119,7 +1117,7 @@ FLOAT_OP(rsqrt2, s)
1119 set_float_exception_flags(0, &env->fpu->fp_status); 1117 set_float_exception_flags(0, &env->fpu->fp_status);
1120 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); 1118 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1121 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); 1119 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1122 - FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; 1120 + FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1123 update_fcr31(); 1121 update_fcr31();
1124 } 1122 }
1125 FLOAT_OP(rsqrt2, ps) 1123 FLOAT_OP(rsqrt2, ps)
@@ -1129,8 +1127,8 @@ FLOAT_OP(rsqrt2, ps) @@ -1129,8 +1127,8 @@ FLOAT_OP(rsqrt2, ps)
1129 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); 1127 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1130 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); 1128 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1131 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status); 1129 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1132 - FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;  
1133 - FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; 1130 + FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
  1131 + FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
1134 update_fcr31(); 1132 update_fcr31();
1135 } 1133 }
1136 1134
@@ -1164,8 +1162,8 @@ void do_cmp_d_ ## op (long cc) \ @@ -1164,8 +1162,8 @@ void do_cmp_d_ ## op (long cc) \
1164 void do_cmpabs_d_ ## op (long cc) \ 1162 void do_cmpabs_d_ ## op (long cc) \
1165 { \ 1163 { \
1166 int c; \ 1164 int c; \
1167 - FDT0 &= ~FLOAT_SIGN64; \  
1168 - FDT1 &= ~FLOAT_SIGN64; \ 1165 + FDT0 = float64_chs(FDT0); \
  1166 + FDT1 = float64_chs(FDT1); \
1169 c = cond; \ 1167 c = cond; \
1170 update_fcr31(); \ 1168 update_fcr31(); \
1171 if (c) \ 1169 if (c) \
@@ -1222,8 +1220,8 @@ void do_cmp_s_ ## op (long cc) \ @@ -1222,8 +1220,8 @@ void do_cmp_s_ ## op (long cc) \
1222 void do_cmpabs_s_ ## op (long cc) \ 1220 void do_cmpabs_s_ ## op (long cc) \
1223 { \ 1221 { \
1224 int c; \ 1222 int c; \
1225 - FST0 &= ~FLOAT_SIGN32; \  
1226 - FST1 &= ~FLOAT_SIGN32; \ 1223 + FST0 = float32_abs(FST0); \
  1224 + FST1 = float32_abs(FST1); \
1227 c = cond; \ 1225 c = cond; \
1228 update_fcr31(); \ 1226 update_fcr31(); \
1229 if (c) \ 1227 if (c) \
@@ -1285,10 +1283,10 @@ void do_cmp_ps_ ## op (long cc) \ @@ -1285,10 +1283,10 @@ void do_cmp_ps_ ## op (long cc) \
1285 void do_cmpabs_ps_ ## op (long cc) \ 1283 void do_cmpabs_ps_ ## op (long cc) \
1286 { \ 1284 { \
1287 int cl, ch; \ 1285 int cl, ch; \
1288 - FST0 &= ~FLOAT_SIGN32; \  
1289 - FSTH0 &= ~FLOAT_SIGN32; \  
1290 - FST1 &= ~FLOAT_SIGN32; \  
1291 - FSTH1 &= ~FLOAT_SIGN32; \ 1286 + FST0 = float32_abs(FST0); \
  1287 + FSTH0 = float32_abs(FSTH0); \
  1288 + FST1 = float32_abs(FST1); \
  1289 + FSTH1 = float32_abs(FSTH1); \
1292 cl = condl; \ 1290 cl = condl; \
1293 ch = condh; \ 1291 ch = condh; \
1294 update_fcr31(); \ 1292 update_fcr31(); \