Commit 56ec06bb8ea5467f09b0f351e98816a2876111e7

Authored by blueswir1
1 parent 3f47aa8c

Convert andn, orn and xnor to TCG


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4030 c046a42c-6fe2-441c-8c8c-71466251a162
target-sparc/op.c
@@ -554,21 +554,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void) @@ -554,21 +554,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
554 FORCE_RET(); 554 FORCE_RET();
555 } 555 }
556 556
557 -void OPPROTO op_andn_T1_T0(void)  
558 -{  
559 - T0 &= ~T1;  
560 -}  
561 -  
562 -void OPPROTO op_orn_T1_T0(void)  
563 -{  
564 - T0 |= ~T1;  
565 -}  
566 -  
567 -void OPPROTO op_xnor_T1_T0(void)  
568 -{  
569 - T0 ^= ~T1;  
570 -}  
571 -  
572 void OPPROTO op_umul_T1_T0(void) 557 void OPPROTO op_umul_T1_T0(void)
573 { 558 {
574 uint64_t res; 559 uint64_t res;
target-sparc/translate.c
@@ -2613,17 +2613,20 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2613,17 +2613,20 @@ static void disas_sparc_insn(DisasContext * dc)
2613 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2613 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2614 break; 2614 break;
2615 case 0x5: 2615 case 0x5:
2616 - gen_op_andn_T1_T0(); 2616 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  2617 + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2617 if (xop & 0x10) 2618 if (xop & 0x10)
2618 gen_op_logic_T0_cc(); 2619 gen_op_logic_T0_cc();
2619 break; 2620 break;
2620 case 0x6: 2621 case 0x6:
2621 - gen_op_orn_T1_T0(); 2622 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  2623 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2622 if (xop & 0x10) 2624 if (xop & 0x10)
2623 gen_op_logic_T0_cc(); 2625 gen_op_logic_T0_cc();
2624 break; 2626 break;
2625 case 0x7: 2627 case 0x7:
2626 - gen_op_xnor_T1_T0(); 2628 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  2629 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2627 if (xop & 0x10) 2630 if (xop & 0x10)
2628 gen_op_logic_T0_cc(); 2631 gen_op_logic_T0_cc();
2629 break; 2632 break;