gwj / at91sam9263 · Commits

Commit 56ec06bb8ea5467f09b0f351e98816a2876111e7

Authored by blueswir1
1 parent 3f47aa8c

Convert andn, orn and xnor to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4030 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 6 additions and 18 deletions
target-sparc/op.c
  View file @56ec06b
... ... @@ -554,21 +554,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void)
554 554 FORCE_RET();
555 555 }
556 556  
557   -void OPPROTO op_andn_T1_T0(void)
558   -{
559   - T0 &= ~T1;
560   -}
561   -
562   -void OPPROTO op_orn_T1_T0(void)
563   -{
564   - T0 |= ~T1;
565   -}
566   -
567   -void OPPROTO op_xnor_T1_T0(void)
568   -{
569   - T0 ^= ~T1;
570   -}
571   -
572 557 void OPPROTO op_umul_T1_T0(void)
573 558 {
574 559 uint64_t res;
... ...
target-sparc/translate.c
  View file @56ec06b
... ... @@ -2613,17 +2613,20 @@ static void disas_sparc_insn(DisasContext * dc)
2613 2613 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2614 2614 break;
2615 2615 case 0x5:
2616   - gen_op_andn_T1_T0();
  2616 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  2617 + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2617 2618 if (xop & 0x10)
2618 2619 gen_op_logic_T0_cc();
2619 2620 break;
2620 2621 case 0x6:
2621   - gen_op_orn_T1_T0();
  2622 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  2623 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2622 2624 if (xop & 0x10)
2623 2625 gen_op_logic_T0_cc();
2624 2626 break;
2625 2627 case 0x7:
2626   - gen_op_xnor_T1_T0();
  2628 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
  2629 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2627 2630 if (xop & 0x10)
2628 2631 gen_op_logic_T0_cc();
2629 2632 break;
... ...