Commit 52cc07d04774676c69e3998cdb5d10c8f5286072
1 parent
e0353fe2
Change Sparc uses of pic_set_irq to pic_set_irq_new
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2572 c046a42c-6fe2-441c-8c8c-71466251a162
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6 changed files
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45 additions
and
35 deletions
hw/slavio_intctl.c
| ... | ... | @@ -277,7 +277,7 @@ static void slavio_check_interrupts(void *opaque) |
| 277 | 277 | * "irq" here is the bit number in the system interrupt register to |
| 278 | 278 | * separate serial and keyboard interrupts sharing a level. |
| 279 | 279 | */ |
| 280 | -void slavio_pic_set_irq(void *opaque, int irq, int level) | |
| 280 | +void pic_set_irq_new(void *opaque, int irq, int level) | |
| 281 | 281 | { |
| 282 | 282 | SLAVIO_INTCTLState *s = opaque; |
| 283 | 283 | |
| ... | ... | @@ -299,13 +299,13 @@ void slavio_pic_set_irq(void *opaque, int irq, int level) |
| 299 | 299 | } |
| 300 | 300 | } |
| 301 | 301 | |
| 302 | -void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu) | |
| 302 | +void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu) | |
| 303 | 303 | { |
| 304 | 304 | SLAVIO_INTCTLState *s = opaque; |
| 305 | 305 | |
| 306 | 306 | DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level); |
| 307 | 307 | if (cpu == (unsigned int)-1) { |
| 308 | - slavio_pic_set_irq(opaque, irq, level); | |
| 308 | + pic_set_irq_new(opaque, irq, level); | |
| 309 | 309 | return; |
| 310 | 310 | } |
| 311 | 311 | if (irq < 32) { | ... | ... |
hw/slavio_misc.c
| ... | ... | @@ -36,6 +36,9 @@ |
| 36 | 36 | #ifdef DEBUG_MISC |
| 37 | 37 | #define MISC_DPRINTF(fmt, args...) \ |
| 38 | 38 | do { printf("MISC: " fmt , ##args); } while (0) |
| 39 | +#define pic_set_irq_new(intctl, irq, level) \ | |
| 40 | + do { printf("MISC: set_irq(%d): %d\n", (irq), (level)); \ | |
| 41 | + pic_set_irq_new((intctl), (irq),(level));} while (0) | |
| 39 | 42 | #else |
| 40 | 43 | #define MISC_DPRINTF(fmt, args...) |
| 41 | 44 | #endif |
| ... | ... | @@ -45,6 +48,7 @@ typedef struct MiscState { |
| 45 | 48 | uint8_t config; |
| 46 | 49 | uint8_t aux1, aux2; |
| 47 | 50 | uint8_t diag, mctrl, sysctrl; |
| 51 | + void *intctl; | |
| 48 | 52 | } MiscState; |
| 49 | 53 | |
| 50 | 54 | #define MISC_MAXADDR 1 |
| ... | ... | @@ -54,9 +58,9 @@ static void slavio_misc_update_irq(void *opaque) |
| 54 | 58 | MiscState *s = opaque; |
| 55 | 59 | |
| 56 | 60 | if ((s->aux2 & 0x4) && (s->config & 0x8)) { |
| 57 | - pic_set_irq(s->irq, 1); | |
| 61 | + pic_set_irq_new(s->intctl, s->irq, 1); | |
| 58 | 62 | } else { |
| 59 | - pic_set_irq(s->irq, 0); | |
| 63 | + pic_set_irq_new(s->intctl, s->irq, 0); | |
| 60 | 64 | } |
| 61 | 65 | } |
| 62 | 66 | |
| ... | ... | @@ -207,7 +211,7 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
| 207 | 211 | return 0; |
| 208 | 212 | } |
| 209 | 213 | |
| 210 | -void *slavio_misc_init(uint32_t base, int irq) | |
| 214 | +void *slavio_misc_init(uint32_t base, int irq, void *intctl) | |
| 211 | 215 | { |
| 212 | 216 | int slavio_misc_io_memory; |
| 213 | 217 | MiscState *s; |
| ... | ... | @@ -233,6 +237,7 @@ void *slavio_misc_init(uint32_t base, int irq) |
| 233 | 237 | cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory); |
| 234 | 238 | |
| 235 | 239 | s->irq = irq; |
| 240 | + s->intctl = intctl; | |
| 236 | 241 | |
| 237 | 242 | register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s); |
| 238 | 243 | qemu_register_reset(slavio_misc_reset, s); | ... | ... |
hw/slavio_serial.c
| ... | ... | @@ -52,8 +52,9 @@ |
| 52 | 52 | #ifdef DEBUG_SERIAL |
| 53 | 53 | #define SER_DPRINTF(fmt, args...) \ |
| 54 | 54 | do { printf("SER: " fmt , ##args); } while (0) |
| 55 | -#define pic_set_irq(irq, level) \ | |
| 56 | -do { printf("SER: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0) | |
| 55 | +#define pic_set_irq_new(intctl, irq, level) \ | |
| 56 | + do { printf("SER: set_irq(%d): %d\n", (irq), (level)); \ | |
| 57 | + pic_set_irq_new((intctl), (irq),(level));} while (0) | |
| 57 | 58 | #else |
| 58 | 59 | #define SER_DPRINTF(fmt, args...) |
| 59 | 60 | #endif |
| ... | ... | @@ -97,6 +98,7 @@ typedef struct ChannelState { |
| 97 | 98 | uint8_t rx, tx, wregs[16], rregs[16]; |
| 98 | 99 | SERIOQueue queue; |
| 99 | 100 | CharDriverState *chr; |
| 101 | + void *intctl; | |
| 100 | 102 | } ChannelState; |
| 101 | 103 | |
| 102 | 104 | struct SerialState { |
| ... | ... | @@ -164,7 +166,7 @@ static void slavio_serial_update_irq(ChannelState *s) |
| 164 | 166 | irq = slavio_serial_update_irq_chn(s); |
| 165 | 167 | irq |= slavio_serial_update_irq_chn(s->otherchn); |
| 166 | 168 | |
| 167 | - pic_set_irq(s->irq, irq); | |
| 169 | + pic_set_irq_new(s->intctl, s->irq, irq); | |
| 168 | 170 | } |
| 169 | 171 | |
| 170 | 172 | static void slavio_serial_reset_chn(ChannelState *s) |
| ... | ... | @@ -545,7 +547,8 @@ static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id) |
| 545 | 547 | |
| 546 | 548 | } |
| 547 | 549 | |
| 548 | -SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2) | |
| 550 | +SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, | |
| 551 | + CharDriverState *chr2, void *intctl) | |
| 549 | 552 | { |
| 550 | 553 | int slavio_serial_io_memory, i; |
| 551 | 554 | SerialState *s; |
| ... | ... | @@ -564,6 +567,7 @@ SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDr |
| 564 | 567 | s->chn[i].irq = irq; |
| 565 | 568 | s->chn[i].chn = 1 - i; |
| 566 | 569 | s->chn[i].type = ser; |
| 570 | + s->chn[i].intctl = intctl; | |
| 567 | 571 | if (s->chn[i].chr) { |
| 568 | 572 | qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, |
| 569 | 573 | serial_receive1, serial_event, &s->chn[i]); |
| ... | ... | @@ -661,7 +665,7 @@ static void sunmouse_event(void *opaque, |
| 661 | 665 | put_queue(s, 0); |
| 662 | 666 | } |
| 663 | 667 | |
| 664 | -void slavio_serial_ms_kbd_init(int base, int irq) | |
| 668 | +void slavio_serial_ms_kbd_init(int base, int irq, void *intctl) | |
| 665 | 669 | { |
| 666 | 670 | int slavio_serial_io_memory, i; |
| 667 | 671 | SerialState *s; |
| ... | ... | @@ -673,6 +677,7 @@ void slavio_serial_ms_kbd_init(int base, int irq) |
| 673 | 677 | s->chn[i].irq = irq; |
| 674 | 678 | s->chn[i].chn = 1 - i; |
| 675 | 679 | s->chn[i].chr = NULL; |
| 680 | + s->chn[i].intctl = intctl; | |
| 676 | 681 | } |
| 677 | 682 | s->chn[0].otherchn = &s->chn[1]; |
| 678 | 683 | s->chn[1].otherchn = &s->chn[0]; | ... | ... |
hw/slavio_timer.c
| ... | ... | @@ -28,6 +28,9 @@ |
| 28 | 28 | #ifdef DEBUG_TIMER |
| 29 | 29 | #define DPRINTF(fmt, args...) \ |
| 30 | 30 | do { printf("TIMER: " fmt , ##args); } while (0) |
| 31 | +#define pic_set_irq_new(intctl, irq, level) \ | |
| 32 | + do { printf("TIMER: set_irq(%d): %d\n", (irq), (level)); \ | |
| 33 | + pic_set_irq_new((intctl), (irq),(level));} while (0) | |
| 31 | 34 | #else |
| 32 | 35 | #define DPRINTF(fmt, args...) |
| 33 | 36 | #endif |
| ... | ... | @@ -57,6 +60,7 @@ typedef struct SLAVIO_TIMERState { |
| 57 | 60 | int reached, stopped; |
| 58 | 61 | int mode; // 0 = processor, 1 = user, 2 = system |
| 59 | 62 | unsigned int cpu; |
| 63 | + void *intctl; | |
| 60 | 64 | } SLAVIO_TIMERState; |
| 61 | 65 | |
| 62 | 66 | #define TIMER_MAXADDR 0x1f |
| ... | ... | @@ -103,7 +107,7 @@ static void slavio_timer_get_out(SLAVIO_TIMERState *s) |
| 103 | 107 | DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode); |
| 104 | 108 | |
| 105 | 109 | if (s->mode != 1) |
| 106 | - pic_set_irq_cpu(s->irq, out, s->cpu); | |
| 110 | + pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu); | |
| 107 | 111 | } |
| 108 | 112 | |
| 109 | 113 | // timer callback |
| ... | ... | @@ -130,7 +134,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
| 130 | 134 | // part of counter (user mode) |
| 131 | 135 | if (s->mode != 1) { |
| 132 | 136 | // clear irq |
| 133 | - pic_set_irq_cpu(s->irq, 0, s->cpu); | |
| 137 | + pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu); | |
| 134 | 138 | s->reached = 0; |
| 135 | 139 | return s->limit; |
| 136 | 140 | } |
| ... | ... | @@ -265,7 +269,8 @@ static void slavio_timer_reset(void *opaque) |
| 265 | 269 | slavio_timer_get_out(s); |
| 266 | 270 | } |
| 267 | 271 | |
| 268 | -void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu) | |
| 272 | +void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu, | |
| 273 | + void *intctl) | |
| 269 | 274 | { |
| 270 | 275 | int slavio_timer_io_memory; |
| 271 | 276 | SLAVIO_TIMERState *s; |
| ... | ... | @@ -277,6 +282,7 @@ void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu) |
| 277 | 282 | s->mode = mode; |
| 278 | 283 | s->cpu = cpu; |
| 279 | 284 | s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s); |
| 285 | + s->intctl = intctl; | |
| 280 | 286 | |
| 281 | 287 | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read, |
| 282 | 288 | slavio_timer_mem_write, s); | ... | ... |
hw/sun4m.c
| ... | ... | @@ -184,17 +184,7 @@ void irq_info() |
| 184 | 184 | |
| 185 | 185 | void pic_set_irq(int irq, int level) |
| 186 | 186 | { |
| 187 | - slavio_pic_set_irq(slavio_intctl, irq, level); | |
| 188 | -} | |
| 189 | - | |
| 190 | -void pic_set_irq_new(void *opaque, int irq, int level) | |
| 191 | -{ | |
| 192 | - pic_set_irq(irq, level); | |
| 193 | -} | |
| 194 | - | |
| 195 | -void pic_set_irq_cpu(int irq, int level, unsigned int cpu) | |
| 196 | -{ | |
| 197 | - slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu); | |
| 187 | + pic_set_irq_new(slavio_intctl, irq, level); | |
| 198 | 188 | } |
| 199 | 189 | |
| 200 | 190 | static void *slavio_misc; |
| ... | ... | @@ -261,15 +251,16 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, |
| 261 | 251 | nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8); |
| 262 | 252 | for (i = 0; i < MAX_CPUS; i++) { |
| 263 | 253 | slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE, |
| 264 | - hwdef->clock_irq, 0, i); | |
| 254 | + hwdef->clock_irq, 0, i, slavio_intctl); | |
| 265 | 255 | } |
| 266 | 256 | slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2, |
| 267 | - (unsigned int)-1); | |
| 268 | - slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq); | |
| 257 | + (unsigned int)-1, slavio_intctl); | |
| 258 | + slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq, | |
| 259 | + slavio_intctl); | |
| 269 | 260 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
| 270 | 261 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device |
| 271 | 262 | slavio_serial_init(hwdef->serial_base, hwdef->ser_irq, |
| 272 | - serial_hds[1], serial_hds[0]); | |
| 263 | + serial_hds[1], serial_hds[0], slavio_intctl); | |
| 273 | 264 | fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table); |
| 274 | 265 | main_esp = esp_init(bs_table, hwdef->esp_base, dma); |
| 275 | 266 | |
| ... | ... | @@ -279,7 +270,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size, |
| 279 | 270 | } |
| 280 | 271 | } |
| 281 | 272 | |
| 282 | - slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq); | |
| 273 | + slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq, | |
| 274 | + slavio_intctl); | |
| 283 | 275 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
| 284 | 276 | sparc32_dma_set_reset_data(dma, main_esp, main_lance); |
| 285 | 277 | } | ... | ... |
vl.h
| ... | ... | @@ -1144,7 +1144,6 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
| 1144 | 1144 | |
| 1145 | 1145 | /* sun4m.c */ |
| 1146 | 1146 | extern QEMUMachine ss5_machine, ss10_machine; |
| 1147 | -void pic_set_irq_cpu(int irq, int level, unsigned int cpu); | |
| 1148 | 1147 | |
| 1149 | 1148 | /* iommu.c */ |
| 1150 | 1149 | void *iommu_init(uint32_t addr); |
| ... | ... | @@ -1169,6 +1168,7 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, |
| 1169 | 1168 | unsigned long vram_offset, int vram_size, int width, int height); |
| 1170 | 1169 | |
| 1171 | 1170 | /* slavio_intctl.c */ |
| 1171 | +void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu); | |
| 1172 | 1172 | void *slavio_intctl_init(uint32_t addr, uint32_t addrg, |
| 1173 | 1173 | const uint32_t *intbit_to_level); |
| 1174 | 1174 | void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env); |
| ... | ... | @@ -1185,14 +1185,16 @@ int load_aout(const char *filename, uint8_t *addr); |
| 1185 | 1185 | int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
| 1186 | 1186 | |
| 1187 | 1187 | /* slavio_timer.c */ |
| 1188 | -void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu); | |
| 1188 | +void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu, | |
| 1189 | + void *intctl); | |
| 1189 | 1190 | |
| 1190 | 1191 | /* slavio_serial.c */ |
| 1191 | -SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2); | |
| 1192 | -void slavio_serial_ms_kbd_init(int base, int irq); | |
| 1192 | +SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, | |
| 1193 | + CharDriverState *chr2, void *intctl); | |
| 1194 | +void slavio_serial_ms_kbd_init(int base, int irq, void *intctl); | |
| 1193 | 1195 | |
| 1194 | 1196 | /* slavio_misc.c */ |
| 1195 | -void *slavio_misc_init(uint32_t base, int irq); | |
| 1197 | +void *slavio_misc_init(uint32_t base, int irq, void *intctl); | |
| 1196 | 1198 | void slavio_set_power_fail(void *opaque, int power_failing); |
| 1197 | 1199 | |
| 1198 | 1200 | /* esp.c */ | ... | ... |