gwj / at91sam9263 · Commits

Commit 4cc633c38bb785bc9e586fa26b9a9e22bb41200c

Authored by balrog
1 parent aaf2d97d

Patch holes in ARM translation (Laurent Desnogues). 

 - gen_set_CF_bit31:  use the right value to set carry flag
 - shifter_out_im:  remove a spurious semi-colon
 - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN
   size 2 case
 - sbfx, ubfx are v6t2 instructions

The correct cps user mode behaviour is unclear so it's left out from the
commit until ARM decides it.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5908 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 4 additions and 2 deletions
target-arm/translate.c
  View file @4cc633c
... ... @@ -415,7 +415,7 @@ static void gen_set_CF_bit31(TCGv var)
415 415 {
416 416 TCGv tmp = new_tmp();
417 417 tcg_gen_shri_i32(tmp, var, 31);
418   - gen_set_CF(var);
  418 + gen_set_CF(tmp);
419 419 dead_tmp(tmp);
420 420 }
421 421  
... ... @@ -490,7 +490,7 @@ static void shifter_out_im(TCGv var, int shift)
490 490 tcg_gen_andi_i32(tmp, var, 1);
491 491 } else {
492 492 tcg_gen_shri_i32(tmp, var, shift);
493   - if (shift != 31);
  493 + if (shift != 31)
494 494 tcg_gen_andi_i32(tmp, tmp, 1);
495 495 }
496 496 gen_set_CF(tmp);
... ... @@ -4618,6 +4618,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4618 4618 imm = (uint32_t)shift;
4619 4619 tmp2 = tcg_const_i32(imm);
4620 4620 TCGV_UNUSED_I64(tmp64);
  4621 + break;
4621 4622 case 3:
4622 4623 tmp64 = tcg_const_i64(shift);
4623 4624 TCGV_UNUSED(tmp2);
... ... @@ -6583,6 +6584,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6583 6584 break;
6584 6585 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
6585 6586 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
  6587 + ARCH(6T2);
6586 6588 tmp = load_reg(s, rm);
6587 6589 shift = (insn >> 7) & 0x1f;
6588 6590 i = ((insn >> 16) & 0x1f) + 1;
... ...