gwj / at91sam9263 · Commits

Commit aaf2d97dcbc4f43f086bcf356a2e31b7dbd6b775

Authored by balrog
1 parent 13643323

ARM: cosmetics (Laurent Desnogues). 

  - remove macros that are not used
  - remove disass structure is_mem field which value is never used
  - correct a typo in a comment.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5907 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 1 additions and 29 deletions
target-arm/translate.c
  View file @aaf2d97
... ... @@ -57,7 +57,6 @@ typedef struct DisasContext {
57 57 struct TranslationBlock *tb;
58 58 int singlestep_enabled;
59 59 int thumb;
60   - int is_mem;
61 60 #if !defined(CONFIG_USER_ONLY)
62 61 int user;
63 62 #endif
... ... @@ -195,7 +194,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
195 194  
196 195 /* Basic operations. */
197 196 #define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1])
198   -#define gen_op_movl_T1_T0() tcg_gen_mov_i32(cpu_T[1], cpu_T[0])
199 197 #define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im)
200 198 #define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im)
201 199  
... ... @@ -219,11 +217,8 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
219 217 #define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]);
220 218 #define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]);
221 219  
222   -#define gen_op_shll_T0_im(im) tcg_gen_shli_i32(cpu_T[0], cpu_T[0], im)
223 220 #define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im)
224 221 #define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im)
225   -#define gen_op_sarl_T1_im(im) tcg_gen_sari_i32(cpu_T[1], cpu_T[1], im)
226   -#define gen_op_rorl_T1_im(im) tcg_gen_rori_i32(cpu_T[1], cpu_T[1], im)
227 222  
228 223 /* Value extensions. */
229 224 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
... ... @@ -382,7 +377,6 @@ static void gen_imull(TCGv a, TCGv b)
382 377 tcg_gen_shri_i64(tmp1, tmp1, 32);
383 378 tcg_gen_trunc_i64_i32(b, tmp1);
384 379 }
385   -#define gen_op_imull_T0_T1() gen_imull(cpu_T[0], cpu_T[1])
386 380  
387 381 /* Swap low and high halfwords. */
388 382 static void gen_swap_half(TCGv var)
... ... @@ -817,17 +811,6 @@ static inline void gen_bx_T0(DisasContext *s)
817 811 gen_bx(s, tmp);
818 812 }
819 813  
820   -#if defined(CONFIG_USER_ONLY)
821   -#define gen_ldst(name, s) gen_op_##name##_raw()
822   -#else
823   -#define gen_ldst(name, s) do { \
824   - s->is_mem = 1; \
825   - if (IS_USER(s)) \
826   - gen_op_##name##_user(); \
827   - else \
828   - gen_op_##name##_kernel(); \
829   - } while (0)
830   -#endif
831 814 static inline TCGv gen_ld8s(TCGv addr, int index)
832 815 {
833 816 TCGv tmp = new_tmp();
... ... @@ -995,15 +978,6 @@ static inline void gen_vfp_##name(int dp) \
995 978 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
996 979 }
997 980  
998   -#define VFP_OP1(name) \
999   -static inline void gen_vfp_##name(int dp, int arg) \
1000   -{ \
1001   - if (dp) \
1002   - gen_op_vfp_##name##d(arg); \
1003   - else \
1004   - gen_op_vfp_##name##s(arg); \
1005   -}
1006   -
1007 981 VFP_OP2(add)
1008 982 VFP_OP2(sub)
1009 983 VFP_OP2(mul)
... ... @@ -6649,7 +6623,6 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6649 6623 gen_add_data_offset(s, insn, tmp2);
6650 6624 if (insn & (1 << 20)) {
6651 6625 /* load */
6652   - s->is_mem = 1;
6653 6626 if (insn & (1 << 22)) {
6654 6627 tmp = gen_ld8u(tmp2, i);
6655 6628 } else {
... ... @@ -8625,7 +8598,6 @@ static inline void gen_intermediate_code_internal(CPUState *env,
8625 8598 dc->thumb = env->thumb;
8626 8599 dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
8627 8600 dc->condexec_cond = env->condexec_bits >> 4;
8628   - dc->is_mem = 0;
8629 8601 #if !defined(CONFIG_USER_ONLY)
8630 8602 if (IS_M(env)) {
8631 8603 dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
... ... @@ -8729,7 +8701,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
8729 8701 gen_set_label(dc->condlabel);
8730 8702 dc->condjmp = 0;
8731 8703 }
8732   - /* Translation stops when a conditional branch is enoutered.
  8704 + /* Translation stops when a conditional branch is encountered.
8733 8705 * Otherwise the subsequent code could get translated several times.
8734 8706 * Also stop translation when a page boundary is reached. This
8735 8707 * ensures prefetch aborts occur at the right place. */
... ...