gwj / at91sam9263 · Commits

Commit 4911012d267519d104a3123783c9b86bddc59f39

Authored by blueswir1
1 parent 6ce0ca12

Implement mtfsf.L encoding 

Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 6 additions and 2 deletions
target-ppc/translate.c
  View file @4911012
... ... @@ -2420,9 +2420,10 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2420 2420 }
2421 2421  
2422 2422 /* mtfsf */
2423   -GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
  2423 +GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
2424 2424 {
2425 2425 TCGv_i32 t0;
  2426 + int L = ctx->opcode & 0x02000000;
2426 2427  
2427 2428 if (unlikely(!ctx->fpu_enabled)) {
2428 2429 gen_exception(ctx, POWERPC_EXCP_FPU);
... ... @@ -2431,7 +2432,10 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2431 2432 /* NIP cannot be restored if the memory exception comes from an helper */
2432 2433 gen_update_nip(ctx, ctx->nip - 4);
2433 2434 gen_reset_fpstatus();
2434   - t0 = tcg_const_i32(FM(ctx->opcode));
  2435 + if (L)
  2436 + t0 = tcg_const_i32(0xff);
  2437 + else
  2438 + t0 = tcg_const_i32(FM(ctx->opcode));
2435 2439 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2436 2440 tcg_temp_free_i32(t0);
2437 2441 if (unlikely(Rc(ctx->opcode) != 0)) {
... ...