gwj / at91sam9263 · Commits

Commit 6ce0ca1204c0536d071f86ac1309c5b6fd99c351

Authored by blueswir1
1 parent 4e98d8cf

Enable 64bit mode on interrupts 

Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 5 additions and 1 deletions
target-ppc/helper.c
  View file @6ce0ca1
... ... @@ -2612,7 +2612,7 @@ static always_inline void powerpc_excp (CPUState *env,
2612 2612 new_msr |= (target_ulong)1 << MSR_CM;
2613 2613 }
2614 2614 } else {
2615   - if (!msr_isf) {
  2615 + if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
2616 2616 new_msr &= ~((target_ulong)1 << MSR_SF);
2617 2617 vector = (uint32_t)vector;
2618 2618 } else {
... ... @@ -2793,6 +2793,10 @@ void cpu_ppc_reset (void *opaque)
2793 2793 ppc_tlb_invalidate_all(env);
2794 2794 #endif
2795 2795 env->msr = msr & env->msr_mask;
  2796 +#if defined(TARGET_PPC64)
  2797 + if (env->mmu_model & POWERPC_MMU_64)
  2798 + env->msr |= (1ULL << MSR_SF);
  2799 +#endif
2796 2800 hreg_compute_hflags(env);
2797 2801 env->reserve = (target_ulong)-1ULL;
2798 2802 /* Be sure no exception or interrupt is pending */
... ...