gwj / at91sam9263 · Commits

Commit 44e7757c2afc4087b7253d227a7cbcfa52955dad

Authored by blueswir1
1 parent ff07ec83

Convert other float and VIS ops to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4091 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 799 additions and 777 deletions
target-sparc/helper.h
  View file @44e7757
... ... @@ -84,3 +84,99 @@ void TCG_HELPER_PROTO helper_fcmpeq_fcc3(void);
84 84 #endif
85 85 #endif
86 86 void TCG_HELPER_PROTO raise_exception(int tt);
  87 +#define F_HELPER_0_0(name) void TCG_HELPER_PROTO helper_f ## name(void)
  88 +#if defined(CONFIG_USER_ONLY)
  89 +#define F_HELPER_SDQ_0_0(name) \
  90 + F_HELPER_0_0(name ## s); \
  91 + F_HELPER_0_0(name ## d); \
  92 + F_HELPER_0_0(name ## q)
  93 +#else
  94 +#define F_HELPER_SDQ_0_0(name) \
  95 + F_HELPER_0_0(name ## s); \
  96 + F_HELPER_0_0(name ## d);
  97 +#endif
  98 +
  99 +F_HELPER_SDQ_0_0(add);
  100 +F_HELPER_SDQ_0_0(sub);
  101 +F_HELPER_SDQ_0_0(mul);
  102 +F_HELPER_SDQ_0_0(div);
  103 +
  104 +F_HELPER_0_0(smuld);
  105 +F_HELPER_0_0(dmulq);
  106 +
  107 +F_HELPER_SDQ_0_0(neg);
  108 +F_HELPER_SDQ_0_0(ito);
  109 +#ifdef TARGET_SPARC64
  110 +F_HELPER_SDQ_0_0(xto);
  111 +#endif
  112 +F_HELPER_0_0(dtos);
  113 +F_HELPER_0_0(stod);
  114 +#if defined(CONFIG_USER_ONLY)
  115 +F_HELPER_0_0(qtos);
  116 +F_HELPER_0_0(stoq);
  117 +F_HELPER_0_0(qtod);
  118 +F_HELPER_0_0(dtoq);
  119 +#endif
  120 +F_HELPER_0_0(stoi);
  121 +F_HELPER_0_0(dtoi);
  122 +#if defined(CONFIG_USER_ONLY)
  123 +F_HELPER_0_0(qtoi);
  124 +#endif
  125 +#ifdef TARGET_SPARC64
  126 +F_HELPER_0_0(stox);
  127 +F_HELPER_0_0(dtox);
  128 +#if defined(CONFIG_USER_ONLY)
  129 +F_HELPER_0_0(qtox);
  130 +#endif
  131 +F_HELPER_0_0(aligndata);
  132 +void TCG_HELPER_PROTO helper_movl_FT0_0(void);
  133 +void TCG_HELPER_PROTO helper_movl_DT0_0(void);
  134 +void TCG_HELPER_PROTO helper_movl_FT0_1(void);
  135 +void TCG_HELPER_PROTO helper_movl_DT0_1(void);
  136 +F_HELPER_0_0(not);
  137 +F_HELPER_0_0(nots);
  138 +F_HELPER_0_0(nor);
  139 +F_HELPER_0_0(nors);
  140 +F_HELPER_0_0(or);
  141 +F_HELPER_0_0(ors);
  142 +F_HELPER_0_0(xor);
  143 +F_HELPER_0_0(xors);
  144 +F_HELPER_0_0(and);
  145 +F_HELPER_0_0(ands);
  146 +F_HELPER_0_0(ornot);
  147 +F_HELPER_0_0(ornots);
  148 +F_HELPER_0_0(andnot);
  149 +F_HELPER_0_0(andnots);
  150 +F_HELPER_0_0(nand);
  151 +F_HELPER_0_0(nands);
  152 +F_HELPER_0_0(xnor);
  153 +F_HELPER_0_0(xnors);
  154 +F_HELPER_0_0(pmerge);
  155 +F_HELPER_0_0(mul8x16);
  156 +F_HELPER_0_0(mul8x16al);
  157 +F_HELPER_0_0(mul8x16au);
  158 +F_HELPER_0_0(mul8sux16);
  159 +F_HELPER_0_0(mul8ulx16);
  160 +F_HELPER_0_0(muld8sux16);
  161 +F_HELPER_0_0(muld8ulx16);
  162 +F_HELPER_0_0(expand);
  163 +#define VIS_HELPER(name) \
  164 + F_HELPER_0_0(name##16); \
  165 + F_HELPER_0_0(name##16s); \
  166 + F_HELPER_0_0(name##32); \
  167 + F_HELPER_0_0(name##32s)
  168 +
  169 +VIS_HELPER(padd);
  170 +VIS_HELPER(psub);
  171 +#define VIS_CMPHELPER(name) \
  172 + F_HELPER_0_0(name##16); \
  173 + F_HELPER_0_0(name##32)
  174 +VIS_CMPHELPER(cmpgt);
  175 +VIS_CMPHELPER(cmpeq);
  176 +VIS_CMPHELPER(cmple);
  177 +VIS_CMPHELPER(cmpne);
  178 +#endif
  179 +#undef F_HELPER_0_0
  180 +#undef F_HELPER_SDQ_0_0
  181 +#undef VIS_HELPER
  182 +#undef VIS_CMPHELPER
... ...
target-sparc/op.c
  View file @44e7757
... ... @@ -107,216 +107,7 @@ void OPPROTO op_jmp_label(void)
107 107 GOTO_LABEL_PARAM(1);
108 108 }
109 109  
110   -#define F_OP(name, p) void OPPROTO op_f##name##p(void)
111   -
112   -#if defined(CONFIG_USER_ONLY)
113   -#define F_BINOP(name) \
114   - F_OP(name, s) \
115   - { \
116   - FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
117   - } \
118   - F_OP(name, d) \
119   - { \
120   - DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
121   - } \
122   - F_OP(name, q) \
123   - { \
124   - QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
125   - }
126   -#else
127   -#define F_BINOP(name) \
128   - F_OP(name, s) \
129   - { \
130   - FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
131   - } \
132   - F_OP(name, d) \
133   - { \
134   - DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
135   - }
136   -#endif
137   -
138   -F_BINOP(add);
139   -F_BINOP(sub);
140   -F_BINOP(mul);
141   -F_BINOP(div);
142   -#undef F_BINOP
143   -
144   -void OPPROTO op_fsmuld(void)
145   -{
146   - DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
147   - float32_to_float64(FT1, &env->fp_status),
148   - &env->fp_status);
149   -}
150   -
151   -#if defined(CONFIG_USER_ONLY)
152   -void OPPROTO op_fdmulq(void)
153   -{
154   - QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
155   - float64_to_float128(DT1, &env->fp_status),
156   - &env->fp_status);
157   -}
158   -#endif
159   -
160   -#if defined(CONFIG_USER_ONLY)
161   -#define F_HELPER(name) \
162   - F_OP(name, s) \
163   - { \
164   - do_f##name##s(); \
165   - } \
166   - F_OP(name, d) \
167   - { \
168   - do_f##name##d(); \
169   - } \
170   - F_OP(name, q) \
171   - { \
172   - do_f##name##q(); \
173   - }
174   -#else
175   -#define F_HELPER(name) \
176   - F_OP(name, s) \
177   - { \
178   - do_f##name##s(); \
179   - } \
180   - F_OP(name, d) \
181   - { \
182   - do_f##name##d(); \
183   - }
184   -#endif
185   -
186   -F_OP(neg, s)
187   -{
188   - FT0 = float32_chs(FT1);
189   -}
190   -
191   -#ifdef TARGET_SPARC64
192   -F_OP(neg, d)
193   -{
194   - DT0 = float64_chs(DT1);
195   -}
196   -
197   -#if defined(CONFIG_USER_ONLY)
198   -F_OP(neg, q)
199   -{
200   - QT0 = float128_chs(QT1);
201   -}
202   -
203   -#endif
204   -
205   -#endif
206   -
207   -/* Integer to float conversion. */
208   -#ifdef USE_INT_TO_FLOAT_HELPERS
209   -F_HELPER(ito);
210   -#ifdef TARGET_SPARC64
211   -F_HELPER(xto);
212   -#endif
213   -#else
214   -F_OP(ito, s)
215   -{
216   - FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
217   -}
218   -
219   -F_OP(ito, d)
220   -{
221   - DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
222   -}
223   -
224   -#if defined(CONFIG_USER_ONLY)
225   -F_OP(ito, q)
226   -{
227   - QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
228   -}
229   -#endif
230   -
231 110 #ifdef TARGET_SPARC64
232   -F_OP(xto, s)
233   -{
234   - FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
235   -}
236   -
237   -F_OP(xto, d)
238   -{
239   - DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
240   -}
241   -#if defined(CONFIG_USER_ONLY)
242   -F_OP(xto, q)
243   -{
244   - QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
245   -}
246   -#endif
247   -#endif
248   -#endif
249   -#undef F_HELPER
250   -
251   -/* floating point conversion */
252   -void OPPROTO op_fdtos(void)
253   -{
254   - FT0 = float64_to_float32(DT1, &env->fp_status);
255   -}
256   -
257   -void OPPROTO op_fstod(void)
258   -{
259   - DT0 = float32_to_float64(FT1, &env->fp_status);
260   -}
261   -
262   -#if defined(CONFIG_USER_ONLY)
263   -void OPPROTO op_fqtos(void)
264   -{
265   - FT0 = float128_to_float32(QT1, &env->fp_status);
266   -}
267   -
268   -void OPPROTO op_fstoq(void)
269   -{
270   - QT0 = float32_to_float128(FT1, &env->fp_status);
271   -}
272   -
273   -void OPPROTO op_fqtod(void)
274   -{
275   - DT0 = float128_to_float64(QT1, &env->fp_status);
276   -}
277   -
278   -void OPPROTO op_fdtoq(void)
279   -{
280   - QT0 = float64_to_float128(DT1, &env->fp_status);
281   -}
282   -#endif
283   -
284   -/* Float to integer conversion. */
285   -void OPPROTO op_fstoi(void)
286   -{
287   - *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
288   -}
289   -
290   -void OPPROTO op_fdtoi(void)
291   -{
292   - *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
293   -}
294   -
295   -#if defined(CONFIG_USER_ONLY)
296   -void OPPROTO op_fqtoi(void)
297   -{
298   - *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
299   -}
300   -#endif
301   -
302   -#ifdef TARGET_SPARC64
303   -void OPPROTO op_fstox(void)
304   -{
305   - *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
306   -}
307   -
308   -void OPPROTO op_fdtox(void)
309   -{
310   - *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
311   -}
312   -
313   -#if defined(CONFIG_USER_ONLY)
314   -void OPPROTO op_fqtox(void)
315   -{
316   - *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
317   -}
318   -#endif
319   -
320 111 void OPPROTO op_flushw(void)
321 112 {
322 113 if (env->cansave != NWINDOWS - 2) {
... ... @@ -349,451 +140,6 @@ void OPPROTO op_restored(void)
349 140 }
350 141 #endif
351 142  
352   -#ifdef TARGET_SPARC64
353   -void OPPROTO op_faligndata()
354   -{
355   - uint64_t tmp;
356   -
357   - tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
358   - tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
359   - *((uint64_t *)&DT0) = tmp;
360   -}
361   -
362   -void OPPROTO op_movl_FT0_0(void)
363   -{
364   - *((uint32_t *)&FT0) = 0;
365   -}
366   -
367   -void OPPROTO op_movl_DT0_0(void)
368   -{
369   - *((uint64_t *)&DT0) = 0;
370   -}
371   -
372   -void OPPROTO op_movl_FT0_1(void)
373   -{
374   - *((uint32_t *)&FT0) = 0xffffffff;
375   -}
376   -
377   -void OPPROTO op_movl_DT0_1(void)
378   -{
379   - *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
380   -}
381   -
382   -void OPPROTO op_fnot(void)
383   -{
384   - *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
385   -}
386   -
387   -void OPPROTO op_fnots(void)
388   -{
389   - *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
390   -}
391   -
392   -void OPPROTO op_fnor(void)
393   -{
394   - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
395   -}
396   -
397   -void OPPROTO op_fnors(void)
398   -{
399   - *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
400   -}
401   -
402   -void OPPROTO op_for(void)
403   -{
404   - *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
405   -}
406   -
407   -void OPPROTO op_fors(void)
408   -{
409   - *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
410   -}
411   -
412   -void OPPROTO op_fxor(void)
413   -{
414   - *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
415   -}
416   -
417   -void OPPROTO op_fxors(void)
418   -{
419   - *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
420   -}
421   -
422   -void OPPROTO op_fand(void)
423   -{
424   - *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
425   -}
426   -
427   -void OPPROTO op_fands(void)
428   -{
429   - *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
430   -}
431   -
432   -void OPPROTO op_fornot(void)
433   -{
434   - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
435   -}
436   -
437   -void OPPROTO op_fornots(void)
438   -{
439   - *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
440   -}
441   -
442   -void OPPROTO op_fandnot(void)
443   -{
444   - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
445   -}
446   -
447   -void OPPROTO op_fandnots(void)
448   -{
449   - *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
450   -}
451   -
452   -void OPPROTO op_fnand(void)
453   -{
454   - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
455   -}
456   -
457   -void OPPROTO op_fnands(void)
458   -{
459   - *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
460   -}
461   -
462   -void OPPROTO op_fxnor(void)
463   -{
464   - *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
465   -}
466   -
467   -void OPPROTO op_fxnors(void)
468   -{
469   - *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
470   -}
471   -
472   -#ifdef WORDS_BIGENDIAN
473   -#define VIS_B64(n) b[7 - (n)]
474   -#define VIS_W64(n) w[3 - (n)]
475   -#define VIS_SW64(n) sw[3 - (n)]
476   -#define VIS_L64(n) l[1 - (n)]
477   -#define VIS_B32(n) b[3 - (n)]
478   -#define VIS_W32(n) w[1 - (n)]
479   -#else
480   -#define VIS_B64(n) b[n]
481   -#define VIS_W64(n) w[n]
482   -#define VIS_SW64(n) sw[n]
483   -#define VIS_L64(n) l[n]
484   -#define VIS_B32(n) b[n]
485   -#define VIS_W32(n) w[n]
486   -#endif
487   -
488   -typedef union {
489   - uint8_t b[8];
490   - uint16_t w[4];
491   - int16_t sw[4];
492   - uint32_t l[2];
493   - float64 d;
494   -} vis64;
495   -
496   -typedef union {
497   - uint8_t b[4];
498   - uint16_t w[2];
499   - uint32_t l;
500   - float32 f;
501   -} vis32;
502   -
503   -void OPPROTO op_fpmerge(void)
504   -{
505   - vis64 s, d;
506   -
507   - s.d = DT0;
508   - d.d = DT1;
509   -
510   - // Reverse calculation order to handle overlap
511   - d.VIS_B64(7) = s.VIS_B64(3);
512   - d.VIS_B64(6) = d.VIS_B64(3);
513   - d.VIS_B64(5) = s.VIS_B64(2);
514   - d.VIS_B64(4) = d.VIS_B64(2);
515   - d.VIS_B64(3) = s.VIS_B64(1);
516   - d.VIS_B64(2) = d.VIS_B64(1);
517   - d.VIS_B64(1) = s.VIS_B64(0);
518   - //d.VIS_B64(0) = d.VIS_B64(0);
519   -
520   - DT0 = d.d;
521   -}
522   -
523   -void OPPROTO op_fmul8x16(void)
524   -{
525   - vis64 s, d;
526   - uint32_t tmp;
527   -
528   - s.d = DT0;
529   - d.d = DT1;
530   -
531   -#define PMUL(r) \
532   - tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
533   - if ((tmp & 0xff) > 0x7f) \
534   - tmp += 0x100; \
535   - d.VIS_W64(r) = tmp >> 8;
536   -
537   - PMUL(0);
538   - PMUL(1);
539   - PMUL(2);
540   - PMUL(3);
541   -#undef PMUL
542   -
543   - DT0 = d.d;
544   -}
545   -
546   -void OPPROTO op_fmul8x16al(void)
547   -{
548   - vis64 s, d;
549   - uint32_t tmp;
550   -
551   - s.d = DT0;
552   - d.d = DT1;
553   -
554   -#define PMUL(r) \
555   - tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
556   - if ((tmp & 0xff) > 0x7f) \
557   - tmp += 0x100; \
558   - d.VIS_W64(r) = tmp >> 8;
559   -
560   - PMUL(0);
561   - PMUL(1);
562   - PMUL(2);
563   - PMUL(3);
564   -#undef PMUL
565   -
566   - DT0 = d.d;
567   -}
568   -
569   -void OPPROTO op_fmul8x16au(void)
570   -{
571   - vis64 s, d;
572   - uint32_t tmp;
573   -
574   - s.d = DT0;
575   - d.d = DT1;
576   -
577   -#define PMUL(r) \
578   - tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
579   - if ((tmp & 0xff) > 0x7f) \
580   - tmp += 0x100; \
581   - d.VIS_W64(r) = tmp >> 8;
582   -
583   - PMUL(0);
584   - PMUL(1);
585   - PMUL(2);
586   - PMUL(3);
587   -#undef PMUL
588   -
589   - DT0 = d.d;
590   -}
591   -
592   -void OPPROTO op_fmul8sux16(void)
593   -{
594   - vis64 s, d;
595   - uint32_t tmp;
596   -
597   - s.d = DT0;
598   - d.d = DT1;
599   -
600   -#define PMUL(r) \
601   - tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
602   - if ((tmp & 0xff) > 0x7f) \
603   - tmp += 0x100; \
604   - d.VIS_W64(r) = tmp >> 8;
605   -
606   - PMUL(0);
607   - PMUL(1);
608   - PMUL(2);
609   - PMUL(3);
610   -#undef PMUL
611   -
612   - DT0 = d.d;
613   -}
614   -
615   -void OPPROTO op_fmul8ulx16(void)
616   -{
617   - vis64 s, d;
618   - uint32_t tmp;
619   -
620   - s.d = DT0;
621   - d.d = DT1;
622   -
623   -#define PMUL(r) \
624   - tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
625   - if ((tmp & 0xff) > 0x7f) \
626   - tmp += 0x100; \
627   - d.VIS_W64(r) = tmp >> 8;
628   -
629   - PMUL(0);
630   - PMUL(1);
631   - PMUL(2);
632   - PMUL(3);
633   -#undef PMUL
634   -
635   - DT0 = d.d;
636   -}
637   -
638   -void OPPROTO op_fmuld8sux16(void)
639   -{
640   - vis64 s, d;
641   - uint32_t tmp;
642   -
643   - s.d = DT0;
644   - d.d = DT1;
645   -
646   -#define PMUL(r) \
647   - tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
648   - if ((tmp & 0xff) > 0x7f) \
649   - tmp += 0x100; \
650   - d.VIS_L64(r) = tmp;
651   -
652   - // Reverse calculation order to handle overlap
653   - PMUL(1);
654   - PMUL(0);
655   -#undef PMUL
656   -
657   - DT0 = d.d;
658   -}
659   -
660   -void OPPROTO op_fmuld8ulx16(void)
661   -{
662   - vis64 s, d;
663   - uint32_t tmp;
664   -
665   - s.d = DT0;
666   - d.d = DT1;
667   -
668   -#define PMUL(r) \
669   - tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
670   - if ((tmp & 0xff) > 0x7f) \
671   - tmp += 0x100; \
672   - d.VIS_L64(r) = tmp;
673   -
674   - // Reverse calculation order to handle overlap
675   - PMUL(1);
676   - PMUL(0);
677   -#undef PMUL
678   -
679   - DT0 = d.d;
680   -}
681   -
682   -void OPPROTO op_fexpand(void)
683   -{
684   - vis32 s;
685   - vis64 d;
686   -
687   - s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
688   - d.d = DT1;
689   - d.VIS_L64(0) = s.VIS_W32(0) << 4;
690   - d.VIS_L64(1) = s.VIS_W32(1) << 4;
691   - d.VIS_L64(2) = s.VIS_W32(2) << 4;
692   - d.VIS_L64(3) = s.VIS_W32(3) << 4;
693   -
694   - DT0 = d.d;
695   -}
696   -
697   -#define VIS_OP(name, F) \
698   - void OPPROTO name##16(void) \
699   - { \
700   - vis64 s, d; \
701   - \
702   - s.d = DT0; \
703   - d.d = DT1; \
704   - \
705   - d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
706   - d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
707   - d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
708   - d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
709   - \
710   - DT0 = d.d; \
711   - } \
712   - \
713   - void OPPROTO name##16s(void) \
714   - { \
715   - vis32 s, d; \
716   - \
717   - s.f = FT0; \
718   - d.f = FT1; \
719   - \
720   - d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
721   - d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
722   - \
723   - FT0 = d.f; \
724   - } \
725   - \
726   - void OPPROTO name##32(void) \
727   - { \
728   - vis64 s, d; \
729   - \
730   - s.d = DT0; \
731   - d.d = DT1; \
732   - \
733   - d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
734   - d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
735   - \
736   - DT0 = d.d; \
737   - } \
738   - \
739   - void OPPROTO name##32s(void) \
740   - { \
741   - vis32 s, d; \
742   - \
743   - s.f = FT0; \
744   - d.f = FT1; \
745   - \
746   - d.l = F(d.l, s.l); \
747   - \
748   - FT0 = d.f; \
749   - }
750   -
751   -#define FADD(a, b) ((a) + (b))
752   -#define FSUB(a, b) ((a) - (b))
753   -VIS_OP(op_fpadd, FADD)
754   -VIS_OP(op_fpsub, FSUB)
755   -
756   -#define VIS_CMPOP(name, F) \
757   - void OPPROTO name##16(void) \
758   - { \
759   - vis64 s, d; \
760   - \
761   - s.d = DT0; \
762   - d.d = DT1; \
763   - \
764   - d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
765   - d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
766   - d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
767   - d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
768   - \
769   - DT0 = d.d; \
770   - } \
771   - \
772   - void OPPROTO name##32(void) \
773   - { \
774   - vis64 s, d; \
775   - \
776   - s.d = DT0; \
777   - d.d = DT1; \
778   - \
779   - d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
780   - d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
781   - \
782   - DT0 = d.d; \
783   - }
784   -
785   -#define FCMPGT(a, b) ((a) > (b))
786   -#define FCMPEQ(a, b) ((a) == (b))
787   -#define FCMPLE(a, b) ((a) <= (b))
788   -#define FCMPNE(a, b) ((a) != (b))
789   -
790   -VIS_CMPOP(op_fcmpgt, FCMPGT)
791   -VIS_CMPOP(op_fcmpeq, FCMPEQ)
792   -VIS_CMPOP(op_fcmple, FCMPLE)
793   -VIS_CMPOP(op_fcmpne, FCMPNE)
794   -
795   -#endif
796   -
797 143 #define CHECK_ALIGN_OP(align) \
798 144 void OPPROTO op_check_align_T0_ ## align (void) \
799 145 { \
... ...
target-sparc/op_helper.c
  View file @44e7757
... ... @@ -50,78 +50,658 @@ void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
50 50 }
51 51 }
52 52  
53   -void helper_check_ieee_exceptions(void)
  53 +#define F_HELPER(name, p) void helper_f##name##p(void)
  54 +
  55 +#if defined(CONFIG_USER_ONLY)
  56 +#define F_BINOP(name) \
  57 + F_HELPER(name, s) \
  58 + { \
  59 + FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
  60 + } \
  61 + F_HELPER(name, d) \
  62 + { \
  63 + DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
  64 + } \
  65 + F_HELPER(name, q) \
  66 + { \
  67 + QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
  68 + }
  69 +#else
  70 +#define F_BINOP(name) \
  71 + F_HELPER(name, s) \
  72 + { \
  73 + FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
  74 + } \
  75 + F_HELPER(name, d) \
  76 + { \
  77 + DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
  78 + }
  79 +#endif
  80 +
  81 +F_BINOP(add);
  82 +F_BINOP(sub);
  83 +F_BINOP(mul);
  84 +F_BINOP(div);
  85 +#undef F_BINOP
  86 +
  87 +void helper_fsmuld(void)
54 88 {
55   - target_ulong status;
  89 + DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
  90 + float32_to_float64(FT1, &env->fp_status),
  91 + &env->fp_status);
  92 +}
56 93  
57   - status = get_float_exception_flags(&env->fp_status);
58   - if (status) {
59   - /* Copy IEEE 754 flags into FSR */
60   - if (status & float_flag_invalid)
61   - env->fsr |= FSR_NVC;
62   - if (status & float_flag_overflow)
63   - env->fsr |= FSR_OFC;
64   - if (status & float_flag_underflow)
65   - env->fsr |= FSR_UFC;
66   - if (status & float_flag_divbyzero)
67   - env->fsr |= FSR_DZC;
68   - if (status & float_flag_inexact)
69   - env->fsr |= FSR_NXC;
  94 +#if defined(CONFIG_USER_ONLY)
  95 +void helper_fdmulq(void)
  96 +{
  97 + QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
  98 + float64_to_float128(DT1, &env->fp_status),
  99 + &env->fp_status);
  100 +}
  101 +#endif
70 102  
71   - if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
72   - /* Unmasked exception, generate a trap */
73   - env->fsr |= FSR_FTT_IEEE_EXCP;
74   - raise_exception(TT_FP_EXCP);
75   - } else {
76   - /* Accumulate exceptions */
77   - env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
78   - }
79   - }
  103 +F_HELPER(neg, s)
  104 +{
  105 + FT0 = float32_chs(FT1);
80 106 }
81 107  
82   -void helper_clear_float_exceptions(void)
  108 +#ifdef TARGET_SPARC64
  109 +F_HELPER(neg, d)
83 110 {
84   - set_float_exception_flags(0, &env->fp_status);
  111 + DT0 = float64_chs(DT1);
85 112 }
86 113  
87   -#ifdef USE_INT_TO_FLOAT_HELPERS
88   -void do_fitos(void)
  114 +#if defined(CONFIG_USER_ONLY)
  115 +F_HELPER(neg, q)
  116 +{
  117 + QT0 = float128_chs(QT1);
  118 +}
  119 +#endif
  120 +#endif
  121 +
  122 +/* Integer to float conversion. */
  123 +F_HELPER(ito, s)
89 124 {
90 125 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
91 126 }
92 127  
93   -void do_fitod(void)
  128 +F_HELPER(ito, d)
94 129 {
95 130 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
96 131 }
97 132  
98 133 #if defined(CONFIG_USER_ONLY)
99   -void do_fitoq(void)
  134 +F_HELPER(ito, q)
100 135 {
101 136 QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
102 137 }
103 138 #endif
104 139  
105 140 #ifdef TARGET_SPARC64
106   -void do_fxtos(void)
  141 +F_HELPER(xto, s)
107 142 {
108 143 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
109 144 }
110 145  
111   -void do_fxtod(void)
  146 +F_HELPER(xto, d)
112 147 {
113 148 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
114 149 }
  150 +#if defined(CONFIG_USER_ONLY)
  151 +F_HELPER(xto, q)
  152 +{
  153 + QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
  154 +}
  155 +#endif
  156 +#endif
  157 +#undef F_HELPER
  158 +
  159 +/* floating point conversion */
  160 +void helper_fdtos(void)
  161 +{
  162 + FT0 = float64_to_float32(DT1, &env->fp_status);
  163 +}
  164 +
  165 +void helper_fstod(void)
  166 +{
  167 + DT0 = float32_to_float64(FT1, &env->fp_status);
  168 +}
  169 +
  170 +#if defined(CONFIG_USER_ONLY)
  171 +void helper_fqtos(void)
  172 +{
  173 + FT0 = float128_to_float32(QT1, &env->fp_status);
  174 +}
  175 +
  176 +void helper_fstoq(void)
  177 +{
  178 + QT0 = float32_to_float128(FT1, &env->fp_status);
  179 +}
  180 +
  181 +void helper_fqtod(void)
  182 +{
  183 + DT0 = float128_to_float64(QT1, &env->fp_status);
  184 +}
  185 +
  186 +void helper_fdtoq(void)
  187 +{
  188 + QT0 = float64_to_float128(DT1, &env->fp_status);
  189 +}
  190 +#endif
  191 +
  192 +/* Float to integer conversion. */
  193 +void helper_fstoi(void)
  194 +{
  195 + *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
  196 +}
  197 +
  198 +void helper_fdtoi(void)
  199 +{
  200 + *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
  201 +}
115 202  
116 203 #if defined(CONFIG_USER_ONLY)
117   -void do_fxtoq(void)
  204 +void helper_fqtoi(void)
118 205 {
119   - QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status);
  206 + *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
120 207 }
121 208 #endif
  209 +
  210 +#ifdef TARGET_SPARC64
  211 +void helper_fstox(void)
  212 +{
  213 + *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
  214 +}
  215 +
  216 +void helper_fdtox(void)
  217 +{
  218 + *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
  219 +}
  220 +
  221 +#if defined(CONFIG_USER_ONLY)
  222 +void helper_fqtox(void)
  223 +{
  224 + *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
  225 +}
  226 +#endif
  227 +
  228 +void helper_faligndata(void)
  229 +{
  230 + uint64_t tmp;
  231 +
  232 + tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
  233 + tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
  234 + *((uint64_t *)&DT0) = tmp;
  235 +}
  236 +
  237 +void helper_movl_FT0_0(void)
  238 +{
  239 + *((uint32_t *)&FT0) = 0;
  240 +}
  241 +
  242 +void helper_movl_DT0_0(void)
  243 +{
  244 + *((uint64_t *)&DT0) = 0;
  245 +}
  246 +
  247 +void helper_movl_FT0_1(void)
  248 +{
  249 + *((uint32_t *)&FT0) = 0xffffffff;
  250 +}
  251 +
  252 +void helper_movl_DT0_1(void)
  253 +{
  254 + *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
  255 +}
  256 +
  257 +void helper_fnot(void)
  258 +{
  259 + *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
  260 +}
  261 +
  262 +void helper_fnots(void)
  263 +{
  264 + *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
  265 +}
  266 +
  267 +void helper_fnor(void)
  268 +{
  269 + *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
  270 +}
  271 +
  272 +void helper_fnors(void)
  273 +{
  274 + *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
  275 +}
  276 +
  277 +void helper_for(void)
  278 +{
  279 + *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
  280 +}
  281 +
  282 +void helper_fors(void)
  283 +{
  284 + *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
  285 +}
  286 +
  287 +void helper_fxor(void)
  288 +{
  289 + *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
  290 +}
  291 +
  292 +void helper_fxors(void)
  293 +{
  294 + *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
  295 +}
  296 +
  297 +void helper_fand(void)
  298 +{
  299 + *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
  300 +}
  301 +
  302 +void helper_fands(void)
  303 +{
  304 + *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
  305 +}
  306 +
  307 +void helper_fornot(void)
  308 +{
  309 + *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
  310 +}
  311 +
  312 +void helper_fornots(void)
  313 +{
  314 + *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
  315 +}
  316 +
  317 +void helper_fandnot(void)
  318 +{
  319 + *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
  320 +}
  321 +
  322 +void helper_fandnots(void)
  323 +{
  324 + *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
  325 +}
  326 +
  327 +void helper_fnand(void)
  328 +{
  329 + *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
  330 +}
  331 +
  332 +void helper_fnands(void)
  333 +{
  334 + *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
  335 +}
  336 +
  337 +void helper_fxnor(void)
  338 +{
  339 + *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
  340 +}
  341 +
  342 +void helper_fxnors(void)
  343 +{
  344 + *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
  345 +}
  346 +
  347 +#ifdef WORDS_BIGENDIAN
  348 +#define VIS_B64(n) b[7 - (n)]
  349 +#define VIS_W64(n) w[3 - (n)]
  350 +#define VIS_SW64(n) sw[3 - (n)]
  351 +#define VIS_L64(n) l[1 - (n)]
  352 +#define VIS_B32(n) b[3 - (n)]
  353 +#define VIS_W32(n) w[1 - (n)]
  354 +#else
  355 +#define VIS_B64(n) b[n]
  356 +#define VIS_W64(n) w[n]
  357 +#define VIS_SW64(n) sw[n]
  358 +#define VIS_L64(n) l[n]
  359 +#define VIS_B32(n) b[n]
  360 +#define VIS_W32(n) w[n]
122 361 #endif
  362 +
  363 +typedef union {
  364 + uint8_t b[8];
  365 + uint16_t w[4];
  366 + int16_t sw[4];
  367 + uint32_t l[2];
  368 + float64 d;
  369 +} vis64;
  370 +
  371 +typedef union {
  372 + uint8_t b[4];
  373 + uint16_t w[2];
  374 + uint32_t l;
  375 + float32 f;
  376 +} vis32;
  377 +
  378 +void helper_fpmerge(void)
  379 +{
  380 + vis64 s, d;
  381 +
  382 + s.d = DT0;
  383 + d.d = DT1;
  384 +
  385 + // Reverse calculation order to handle overlap
  386 + d.VIS_B64(7) = s.VIS_B64(3);
  387 + d.VIS_B64(6) = d.VIS_B64(3);
  388 + d.VIS_B64(5) = s.VIS_B64(2);
  389 + d.VIS_B64(4) = d.VIS_B64(2);
  390 + d.VIS_B64(3) = s.VIS_B64(1);
  391 + d.VIS_B64(2) = d.VIS_B64(1);
  392 + d.VIS_B64(1) = s.VIS_B64(0);
  393 + //d.VIS_B64(0) = d.VIS_B64(0);
  394 +
  395 + DT0 = d.d;
  396 +}
  397 +
  398 +void helper_fmul8x16(void)
  399 +{
  400 + vis64 s, d;
  401 + uint32_t tmp;
  402 +
  403 + s.d = DT0;
  404 + d.d = DT1;
  405 +
  406 +#define PMUL(r) \
  407 + tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
  408 + if ((tmp & 0xff) > 0x7f) \
  409 + tmp += 0x100; \
  410 + d.VIS_W64(r) = tmp >> 8;
  411 +
  412 + PMUL(0);
  413 + PMUL(1);
  414 + PMUL(2);
  415 + PMUL(3);
  416 +#undef PMUL
  417 +
  418 + DT0 = d.d;
  419 +}
  420 +
  421 +void helper_fmul8x16al(void)
  422 +{
  423 + vis64 s, d;
  424 + uint32_t tmp;
  425 +
  426 + s.d = DT0;
  427 + d.d = DT1;
  428 +
  429 +#define PMUL(r) \
  430 + tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
  431 + if ((tmp & 0xff) > 0x7f) \
  432 + tmp += 0x100; \
  433 + d.VIS_W64(r) = tmp >> 8;
  434 +
  435 + PMUL(0);
  436 + PMUL(1);
  437 + PMUL(2);
  438 + PMUL(3);
  439 +#undef PMUL
  440 +
  441 + DT0 = d.d;
  442 +}
  443 +
  444 +void helper_fmul8x16au(void)
  445 +{
  446 + vis64 s, d;
  447 + uint32_t tmp;
  448 +
  449 + s.d = DT0;
  450 + d.d = DT1;
  451 +
  452 +#define PMUL(r) \
  453 + tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
  454 + if ((tmp & 0xff) > 0x7f) \
  455 + tmp += 0x100; \
  456 + d.VIS_W64(r) = tmp >> 8;
  457 +
  458 + PMUL(0);
  459 + PMUL(1);
  460 + PMUL(2);
  461 + PMUL(3);
  462 +#undef PMUL
  463 +
  464 + DT0 = d.d;
  465 +}
  466 +
  467 +void helper_fmul8sux16(void)
  468 +{
  469 + vis64 s, d;
  470 + uint32_t tmp;
  471 +
  472 + s.d = DT0;
  473 + d.d = DT1;
  474 +
  475 +#define PMUL(r) \
  476 + tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
  477 + if ((tmp & 0xff) > 0x7f) \
  478 + tmp += 0x100; \
  479 + d.VIS_W64(r) = tmp >> 8;
  480 +
  481 + PMUL(0);
  482 + PMUL(1);
  483 + PMUL(2);
  484 + PMUL(3);
  485 +#undef PMUL
  486 +
  487 + DT0 = d.d;
  488 +}
  489 +
  490 +void helper_fmul8ulx16(void)
  491 +{
  492 + vis64 s, d;
  493 + uint32_t tmp;
  494 +
  495 + s.d = DT0;
  496 + d.d = DT1;
  497 +
  498 +#define PMUL(r) \
  499 + tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
  500 + if ((tmp & 0xff) > 0x7f) \
  501 + tmp += 0x100; \
  502 + d.VIS_W64(r) = tmp >> 8;
  503 +
  504 + PMUL(0);
  505 + PMUL(1);
  506 + PMUL(2);
  507 + PMUL(3);
  508 +#undef PMUL
  509 +
  510 + DT0 = d.d;
  511 +}
  512 +
  513 +void helper_fmuld8sux16(void)
  514 +{
  515 + vis64 s, d;
  516 + uint32_t tmp;
  517 +
  518 + s.d = DT0;
  519 + d.d = DT1;
  520 +
  521 +#define PMUL(r) \
  522 + tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
  523 + if ((tmp & 0xff) > 0x7f) \
  524 + tmp += 0x100; \
  525 + d.VIS_L64(r) = tmp;
  526 +
  527 + // Reverse calculation order to handle overlap
  528 + PMUL(1);
  529 + PMUL(0);
  530 +#undef PMUL
  531 +
  532 + DT0 = d.d;
  533 +}
  534 +
  535 +void helper_fmuld8ulx16(void)
  536 +{
  537 + vis64 s, d;
  538 + uint32_t tmp;
  539 +
  540 + s.d = DT0;
  541 + d.d = DT1;
  542 +
  543 +#define PMUL(r) \
  544 + tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
  545 + if ((tmp & 0xff) > 0x7f) \
  546 + tmp += 0x100; \
  547 + d.VIS_L64(r) = tmp;
  548 +
  549 + // Reverse calculation order to handle overlap
  550 + PMUL(1);
  551 + PMUL(0);
  552 +#undef PMUL
  553 +
  554 + DT0 = d.d;
  555 +}
  556 +
  557 +void helper_fexpand(void)
  558 +{
  559 + vis32 s;
  560 + vis64 d;
  561 +
  562 + s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
  563 + d.d = DT1;
  564 + d.VIS_L64(0) = s.VIS_W32(0) << 4;
  565 + d.VIS_L64(1) = s.VIS_W32(1) << 4;
  566 + d.VIS_L64(2) = s.VIS_W32(2) << 4;
  567 + d.VIS_L64(3) = s.VIS_W32(3) << 4;
  568 +
  569 + DT0 = d.d;
  570 +}
  571 +
  572 +#define VIS_HELPER(name, F) \
  573 + void name##16(void) \
  574 + { \
  575 + vis64 s, d; \
  576 + \
  577 + s.d = DT0; \
  578 + d.d = DT1; \
  579 + \
  580 + d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
  581 + d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
  582 + d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
  583 + d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
  584 + \
  585 + DT0 = d.d; \
  586 + } \
  587 + \
  588 + void name##16s(void) \
  589 + { \
  590 + vis32 s, d; \
  591 + \
  592 + s.f = FT0; \
  593 + d.f = FT1; \
  594 + \
  595 + d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
  596 + d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
  597 + \
  598 + FT0 = d.f; \
  599 + } \
  600 + \
  601 + void name##32(void) \
  602 + { \
  603 + vis64 s, d; \
  604 + \
  605 + s.d = DT0; \
  606 + d.d = DT1; \
  607 + \
  608 + d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
  609 + d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
  610 + \
  611 + DT0 = d.d; \
  612 + } \
  613 + \
  614 + void name##32s(void) \
  615 + { \
  616 + vis32 s, d; \
  617 + \
  618 + s.f = FT0; \
  619 + d.f = FT1; \
  620 + \
  621 + d.l = F(d.l, s.l); \
  622 + \
  623 + FT0 = d.f; \
  624 + }
  625 +
  626 +#define FADD(a, b) ((a) + (b))
  627 +#define FSUB(a, b) ((a) - (b))
  628 +VIS_HELPER(helper_fpadd, FADD)
  629 +VIS_HELPER(helper_fpsub, FSUB)
  630 +
  631 +#define VIS_CMPHELPER(name, F) \
  632 + void name##16(void) \
  633 + { \
  634 + vis64 s, d; \
  635 + \
  636 + s.d = DT0; \
  637 + d.d = DT1; \
  638 + \
  639 + d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
  640 + d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
  641 + d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
  642 + d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
  643 + \
  644 + DT0 = d.d; \
  645 + } \
  646 + \
  647 + void name##32(void) \
  648 + { \
  649 + vis64 s, d; \
  650 + \
  651 + s.d = DT0; \
  652 + d.d = DT1; \
  653 + \
  654 + d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
  655 + d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
  656 + \
  657 + DT0 = d.d; \
  658 + }
  659 +
  660 +#define FCMPGT(a, b) ((a) > (b))
  661 +#define FCMPEQ(a, b) ((a) == (b))
  662 +#define FCMPLE(a, b) ((a) <= (b))
  663 +#define FCMPNE(a, b) ((a) != (b))
  664 +
  665 +VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
  666 +VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
  667 +VIS_CMPHELPER(helper_fcmple, FCMPLE)
  668 +VIS_CMPHELPER(helper_fcmpne, FCMPNE)
123 669 #endif
124 670  
  671 +void helper_check_ieee_exceptions(void)
  672 +{
  673 + target_ulong status;
  674 +
  675 + status = get_float_exception_flags(&env->fp_status);
  676 + if (status) {
  677 + /* Copy IEEE 754 flags into FSR */
  678 + if (status & float_flag_invalid)
  679 + env->fsr |= FSR_NVC;
  680 + if (status & float_flag_overflow)
  681 + env->fsr |= FSR_OFC;
  682 + if (status & float_flag_underflow)
  683 + env->fsr |= FSR_UFC;
  684 + if (status & float_flag_divbyzero)
  685 + env->fsr |= FSR_DZC;
  686 + if (status & float_flag_inexact)
  687 + env->fsr |= FSR_NXC;
  688 +
  689 + if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
  690 + /* Unmasked exception, generate a trap */
  691 + env->fsr |= FSR_FTT_IEEE_EXCP;
  692 + raise_exception(TT_FP_EXCP);
  693 + } else {
  694 + /* Accumulate exceptions */
  695 + env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
  696 + }
  697 + }
  698 +}
  699 +
  700 +void helper_clear_float_exceptions(void)
  701 +{
  702 + set_float_exception_flags(0, &env->fp_status);
  703 +}
  704 +
125 705 void helper_fabss(void)
126 706 {
127 707 FT0 = float32_abs(FT1);
... ...
target-sparc/translate.c
  View file @44e7757
... ... @@ -2303,7 +2303,7 @@ static void disas_sparc_insn(DisasContext * dc)
2303 2303 break;
2304 2304 case 0x5: /* fnegs */
2305 2305 gen_op_load_fpr_FT1(rs2);
2306   - gen_op_fnegs();
  2306 + tcg_gen_helper_0_0(helper_fnegs);
2307 2307 gen_op_store_FT0_fpr(rd);
2308 2308 break;
2309 2309 case 0x9: /* fabss */
... ... @@ -2340,7 +2340,7 @@ static void disas_sparc_insn(DisasContext * dc)
2340 2340 gen_op_load_fpr_FT0(rs1);
2341 2341 gen_op_load_fpr_FT1(rs2);
2342 2342 gen_clear_float_exceptions();
2343   - gen_op_fadds();
  2343 + tcg_gen_helper_0_0(helper_fadds);
2344 2344 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2345 2345 gen_op_store_FT0_fpr(rd);
2346 2346 break;
... ... @@ -2348,7 +2348,7 @@ static void disas_sparc_insn(DisasContext * dc)
2348 2348 gen_op_load_fpr_DT0(DFPREG(rs1));
2349 2349 gen_op_load_fpr_DT1(DFPREG(rs2));
2350 2350 gen_clear_float_exceptions();
2351   - gen_op_faddd();
  2351 + tcg_gen_helper_0_0(helper_faddd);
2352 2352 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2353 2353 gen_op_store_DT0_fpr(DFPREG(rd));
2354 2354 break;
... ... @@ -2357,7 +2357,7 @@ static void disas_sparc_insn(DisasContext * dc)
2357 2357 gen_op_load_fpr_QT0(QFPREG(rs1));
2358 2358 gen_op_load_fpr_QT1(QFPREG(rs2));
2359 2359 gen_clear_float_exceptions();
2360   - gen_op_faddq();
  2360 + tcg_gen_helper_0_0(helper_faddq);
2361 2361 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2362 2362 gen_op_store_QT0_fpr(QFPREG(rd));
2363 2363 break;
... ... @@ -2368,7 +2368,7 @@ static void disas_sparc_insn(DisasContext * dc)
2368 2368 gen_op_load_fpr_FT0(rs1);
2369 2369 gen_op_load_fpr_FT1(rs2);
2370 2370 gen_clear_float_exceptions();
2371   - gen_op_fsubs();
  2371 + tcg_gen_helper_0_0(helper_fsubs);
2372 2372 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2373 2373 gen_op_store_FT0_fpr(rd);
2374 2374 break;
... ... @@ -2376,7 +2376,7 @@ static void disas_sparc_insn(DisasContext * dc)
2376 2376 gen_op_load_fpr_DT0(DFPREG(rs1));
2377 2377 gen_op_load_fpr_DT1(DFPREG(rs2));
2378 2378 gen_clear_float_exceptions();
2379   - gen_op_fsubd();
  2379 + tcg_gen_helper_0_0(helper_fsubd);
2380 2380 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2381 2381 gen_op_store_DT0_fpr(DFPREG(rd));
2382 2382 break;
... ... @@ -2385,7 +2385,7 @@ static void disas_sparc_insn(DisasContext * dc)
2385 2385 gen_op_load_fpr_QT0(QFPREG(rs1));
2386 2386 gen_op_load_fpr_QT1(QFPREG(rs2));
2387 2387 gen_clear_float_exceptions();
2388   - gen_op_fsubq();
  2388 + tcg_gen_helper_0_0(helper_fsubq);
2389 2389 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2390 2390 gen_op_store_QT0_fpr(QFPREG(rd));
2391 2391 break;
... ... @@ -2396,7 +2396,7 @@ static void disas_sparc_insn(DisasContext * dc)
2396 2396 gen_op_load_fpr_FT0(rs1);
2397 2397 gen_op_load_fpr_FT1(rs2);
2398 2398 gen_clear_float_exceptions();
2399   - gen_op_fmuls();
  2399 + tcg_gen_helper_0_0(helper_fmuls);
2400 2400 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2401 2401 gen_op_store_FT0_fpr(rd);
2402 2402 break;
... ... @@ -2404,7 +2404,7 @@ static void disas_sparc_insn(DisasContext * dc)
2404 2404 gen_op_load_fpr_DT0(DFPREG(rs1));
2405 2405 gen_op_load_fpr_DT1(DFPREG(rs2));
2406 2406 gen_clear_float_exceptions();
2407   - gen_op_fmuld();
  2407 + tcg_gen_helper_0_0(helper_fmuld);
2408 2408 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2409 2409 gen_op_store_DT0_fpr(DFPREG(rd));
2410 2410 break;
... ... @@ -2413,7 +2413,7 @@ static void disas_sparc_insn(DisasContext * dc)
2413 2413 gen_op_load_fpr_QT0(QFPREG(rs1));
2414 2414 gen_op_load_fpr_QT1(QFPREG(rs2));
2415 2415 gen_clear_float_exceptions();
2416   - gen_op_fmulq();
  2416 + tcg_gen_helper_0_0(helper_fmulq);
2417 2417 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2418 2418 gen_op_store_QT0_fpr(QFPREG(rd));
2419 2419 break;
... ... @@ -2424,7 +2424,7 @@ static void disas_sparc_insn(DisasContext * dc)
2424 2424 gen_op_load_fpr_FT0(rs1);
2425 2425 gen_op_load_fpr_FT1(rs2);
2426 2426 gen_clear_float_exceptions();
2427   - gen_op_fdivs();
  2427 + tcg_gen_helper_0_0(helper_fdivs);
2428 2428 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2429 2429 gen_op_store_FT0_fpr(rd);
2430 2430 break;
... ... @@ -2432,7 +2432,7 @@ static void disas_sparc_insn(DisasContext * dc)
2432 2432 gen_op_load_fpr_DT0(DFPREG(rs1));
2433 2433 gen_op_load_fpr_DT1(DFPREG(rs2));
2434 2434 gen_clear_float_exceptions();
2435   - gen_op_fdivd();
  2435 + tcg_gen_helper_0_0(helper_fdivd);
2436 2436 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2437 2437 gen_op_store_DT0_fpr(DFPREG(rd));
2438 2438 break;
... ... @@ -2441,7 +2441,7 @@ static void disas_sparc_insn(DisasContext * dc)
2441 2441 gen_op_load_fpr_QT0(QFPREG(rs1));
2442 2442 gen_op_load_fpr_QT1(QFPREG(rs2));
2443 2443 gen_clear_float_exceptions();
2444   - gen_op_fdivq();
  2444 + tcg_gen_helper_0_0(helper_fdivq);
2445 2445 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2446 2446 gen_op_store_QT0_fpr(QFPREG(rd));
2447 2447 break;
... ... @@ -2452,7 +2452,7 @@ static void disas_sparc_insn(DisasContext * dc)
2452 2452 gen_op_load_fpr_FT0(rs1);
2453 2453 gen_op_load_fpr_FT1(rs2);
2454 2454 gen_clear_float_exceptions();
2455   - gen_op_fsmuld();
  2455 + tcg_gen_helper_0_0(helper_fsmuld);
2456 2456 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2457 2457 gen_op_store_DT0_fpr(DFPREG(rd));
2458 2458 break;
... ... @@ -2461,7 +2461,7 @@ static void disas_sparc_insn(DisasContext * dc)
2461 2461 gen_op_load_fpr_DT0(DFPREG(rs1));
2462 2462 gen_op_load_fpr_DT1(DFPREG(rs2));
2463 2463 gen_clear_float_exceptions();
2464   - gen_op_fdmulq();
  2464 + tcg_gen_helper_0_0(helper_fdmulq);
2465 2465 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2466 2466 gen_op_store_QT0_fpr(QFPREG(rd));
2467 2467 break;
... ... @@ -2471,14 +2471,14 @@ static void disas_sparc_insn(DisasContext * dc)
2471 2471 case 0xc4:
2472 2472 gen_op_load_fpr_FT1(rs2);
2473 2473 gen_clear_float_exceptions();
2474   - gen_op_fitos();
  2474 + tcg_gen_helper_0_0(helper_fitos);
2475 2475 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2476 2476 gen_op_store_FT0_fpr(rd);
2477 2477 break;
2478 2478 case 0xc6:
2479 2479 gen_op_load_fpr_DT1(DFPREG(rs2));
2480 2480 gen_clear_float_exceptions();
2481   - gen_op_fdtos();
  2481 + tcg_gen_helper_0_0(helper_fdtos);
2482 2482 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2483 2483 gen_op_store_FT0_fpr(rd);
2484 2484 break;
... ... @@ -2486,7 +2486,7 @@ static void disas_sparc_insn(DisasContext * dc)
2486 2486 #if defined(CONFIG_USER_ONLY)
2487 2487 gen_op_load_fpr_QT1(QFPREG(rs2));
2488 2488 gen_clear_float_exceptions();
2489   - gen_op_fqtos();
  2489 + tcg_gen_helper_0_0(helper_fqtos);
2490 2490 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2491 2491 gen_op_store_FT0_fpr(rd);
2492 2492 break;
... ... @@ -2495,19 +2495,19 @@ static void disas_sparc_insn(DisasContext * dc)
2495 2495 #endif
2496 2496 case 0xc8:
2497 2497 gen_op_load_fpr_FT1(rs2);
2498   - gen_op_fitod();
  2498 + tcg_gen_helper_0_0(helper_fitod);
2499 2499 gen_op_store_DT0_fpr(DFPREG(rd));
2500 2500 break;
2501 2501 case 0xc9:
2502 2502 gen_op_load_fpr_FT1(rs2);
2503   - gen_op_fstod();
  2503 + tcg_gen_helper_0_0(helper_fstod);
2504 2504 gen_op_store_DT0_fpr(DFPREG(rd));
2505 2505 break;
2506 2506 case 0xcb: /* fqtod */
2507 2507 #if defined(CONFIG_USER_ONLY)
2508 2508 gen_op_load_fpr_QT1(QFPREG(rs2));
2509 2509 gen_clear_float_exceptions();
2510   - gen_op_fqtod();
  2510 + tcg_gen_helper_0_0(helper_fqtod);
2511 2511 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2512 2512 gen_op_store_DT0_fpr(DFPREG(rd));
2513 2513 break;
... ... @@ -2517,7 +2517,7 @@ static void disas_sparc_insn(DisasContext * dc)
2517 2517 case 0xcc: /* fitoq */
2518 2518 #if defined(CONFIG_USER_ONLY)
2519 2519 gen_op_load_fpr_FT1(rs2);
2520   - gen_op_fitoq();
  2520 + tcg_gen_helper_0_0(helper_fitoq);
2521 2521 gen_op_store_QT0_fpr(QFPREG(rd));
2522 2522 break;
2523 2523 #else
... ... @@ -2526,7 +2526,7 @@ static void disas_sparc_insn(DisasContext * dc)
2526 2526 case 0xcd: /* fstoq */
2527 2527 #if defined(CONFIG_USER_ONLY)
2528 2528 gen_op_load_fpr_FT1(rs2);
2529   - gen_op_fstoq();
  2529 + tcg_gen_helper_0_0(helper_fstoq);
2530 2530 gen_op_store_QT0_fpr(QFPREG(rd));
2531 2531 break;
2532 2532 #else
... ... @@ -2535,7 +2535,7 @@ static void disas_sparc_insn(DisasContext * dc)
2535 2535 case 0xce: /* fdtoq */
2536 2536 #if defined(CONFIG_USER_ONLY)
2537 2537 gen_op_load_fpr_DT1(DFPREG(rs2));
2538   - gen_op_fdtoq();
  2538 + tcg_gen_helper_0_0(helper_fdtoq);
2539 2539 gen_op_store_QT0_fpr(QFPREG(rd));
2540 2540 break;
2541 2541 #else
... ... @@ -2544,14 +2544,14 @@ static void disas_sparc_insn(DisasContext * dc)
2544 2544 case 0xd1:
2545 2545 gen_op_load_fpr_FT1(rs2);
2546 2546 gen_clear_float_exceptions();
2547   - gen_op_fstoi();
  2547 + tcg_gen_helper_0_0(helper_fstoi);
2548 2548 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2549 2549 gen_op_store_FT0_fpr(rd);
2550 2550 break;
2551 2551 case 0xd2:
2552 2552 gen_op_load_fpr_DT1(DFPREG(rs2));
2553 2553 gen_clear_float_exceptions();
2554   - gen_op_fdtoi();
  2554 + tcg_gen_helper_0_0(helper_fdtoi);
2555 2555 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2556 2556 gen_op_store_FT0_fpr(rd);
2557 2557 break;
... ... @@ -2559,7 +2559,7 @@ static void disas_sparc_insn(DisasContext * dc)
2559 2559 #if defined(CONFIG_USER_ONLY)
2560 2560 gen_op_load_fpr_QT1(QFPREG(rs2));
2561 2561 gen_clear_float_exceptions();
2562   - gen_op_fqtoi();
  2562 + tcg_gen_helper_0_0(helper_fqtoi);
2563 2563 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2564 2564 gen_op_store_FT0_fpr(rd);
2565 2565 break;
... ... @@ -2581,13 +2581,13 @@ static void disas_sparc_insn(DisasContext * dc)
2581 2581 #endif
2582 2582 case 0x6: /* V9 fnegd */
2583 2583 gen_op_load_fpr_DT1(DFPREG(rs2));
2584   - gen_op_fnegd();
  2584 + tcg_gen_helper_0_0(helper_fnegd);
2585 2585 gen_op_store_DT0_fpr(DFPREG(rd));
2586 2586 break;
2587 2587 case 0x7: /* V9 fnegq */
2588 2588 #if defined(CONFIG_USER_ONLY)
2589 2589 gen_op_load_fpr_QT1(QFPREG(rs2));
2590   - gen_op_fnegq();
  2590 + tcg_gen_helper_0_0(helper_fnegq);
2591 2591 gen_op_store_QT0_fpr(QFPREG(rd));
2592 2592 break;
2593 2593 #else
... ... @@ -2610,14 +2610,14 @@ static void disas_sparc_insn(DisasContext * dc)
2610 2610 case 0x81: /* V9 fstox */
2611 2611 gen_op_load_fpr_FT1(rs2);
2612 2612 gen_clear_float_exceptions();
2613   - gen_op_fstox();
  2613 + tcg_gen_helper_0_0(helper_fstox);
2614 2614 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615 2615 gen_op_store_DT0_fpr(DFPREG(rd));
2616 2616 break;
2617 2617 case 0x82: /* V9 fdtox */
2618 2618 gen_op_load_fpr_DT1(DFPREG(rs2));
2619 2619 gen_clear_float_exceptions();
2620   - gen_op_fdtox();
  2620 + tcg_gen_helper_0_0(helper_fdtox);
2621 2621 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2622 2622 gen_op_store_DT0_fpr(DFPREG(rd));
2623 2623 break;
... ... @@ -2625,7 +2625,7 @@ static void disas_sparc_insn(DisasContext * dc)
2625 2625 #if defined(CONFIG_USER_ONLY)
2626 2626 gen_op_load_fpr_QT1(QFPREG(rs2));
2627 2627 gen_clear_float_exceptions();
2628   - gen_op_fqtox();
  2628 + tcg_gen_helper_0_0(helper_fqtox);
2629 2629 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2630 2630 gen_op_store_DT0_fpr(DFPREG(rd));
2631 2631 break;
... ... @@ -2635,14 +2635,14 @@ static void disas_sparc_insn(DisasContext * dc)
2635 2635 case 0x84: /* V9 fxtos */
2636 2636 gen_op_load_fpr_DT1(DFPREG(rs2));
2637 2637 gen_clear_float_exceptions();
2638   - gen_op_fxtos();
  2638 + tcg_gen_helper_0_0(helper_fxtos);
2639 2639 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2640 2640 gen_op_store_FT0_fpr(rd);
2641 2641 break;
2642 2642 case 0x88: /* V9 fxtod */
2643 2643 gen_op_load_fpr_DT1(DFPREG(rs2));
2644 2644 gen_clear_float_exceptions();
2645   - gen_op_fxtod();
  2645 + tcg_gen_helper_0_0(helper_fxtod);
2646 2646 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2647 2647 gen_op_store_DT0_fpr(DFPREG(rd));
2648 2648 break;
... ... @@ -2650,7 +2650,7 @@ static void disas_sparc_insn(DisasContext * dc)
2650 2650 #if defined(CONFIG_USER_ONLY)
2651 2651 gen_op_load_fpr_DT1(DFPREG(rs2));
2652 2652 gen_clear_float_exceptions();
2653   - gen_op_fxtoq();
  2653 + tcg_gen_helper_0_0(helper_fxtoq);
2654 2654 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2655 2655 gen_op_store_QT0_fpr(QFPREG(rd));
2656 2656 break;
... ... @@ -3585,91 +3585,91 @@ static void disas_sparc_insn(DisasContext * dc)
3585 3585 case 0x020: /* VIS I fcmple16 */
3586 3586 gen_op_load_fpr_DT0(DFPREG(rs1));
3587 3587 gen_op_load_fpr_DT1(DFPREG(rs2));
3588   - gen_op_fcmple16();
  3588 + tcg_gen_helper_0_0(helper_fcmple16);
3589 3589 gen_op_store_DT0_fpr(DFPREG(rd));
3590 3590 break;
3591 3591 case 0x022: /* VIS I fcmpne16 */
3592 3592 gen_op_load_fpr_DT0(DFPREG(rs1));
3593 3593 gen_op_load_fpr_DT1(DFPREG(rs2));
3594   - gen_op_fcmpne16();
  3594 + tcg_gen_helper_0_0(helper_fcmpne16);
3595 3595 gen_op_store_DT0_fpr(DFPREG(rd));
3596 3596 break;
3597 3597 case 0x024: /* VIS I fcmple32 */
3598 3598 gen_op_load_fpr_DT0(DFPREG(rs1));
3599 3599 gen_op_load_fpr_DT1(DFPREG(rs2));
3600   - gen_op_fcmple32();
  3600 + tcg_gen_helper_0_0(helper_fcmple32);
3601 3601 gen_op_store_DT0_fpr(DFPREG(rd));
3602 3602 break;
3603 3603 case 0x026: /* VIS I fcmpne32 */
3604 3604 gen_op_load_fpr_DT0(DFPREG(rs1));
3605 3605 gen_op_load_fpr_DT1(DFPREG(rs2));
3606   - gen_op_fcmpne32();
  3606 + tcg_gen_helper_0_0(helper_fcmpne32);
3607 3607 gen_op_store_DT0_fpr(DFPREG(rd));
3608 3608 break;
3609 3609 case 0x028: /* VIS I fcmpgt16 */
3610 3610 gen_op_load_fpr_DT0(DFPREG(rs1));
3611 3611 gen_op_load_fpr_DT1(DFPREG(rs2));
3612   - gen_op_fcmpgt16();
  3612 + tcg_gen_helper_0_0(helper_fcmpgt16);
3613 3613 gen_op_store_DT0_fpr(DFPREG(rd));
3614 3614 break;
3615 3615 case 0x02a: /* VIS I fcmpeq16 */
3616 3616 gen_op_load_fpr_DT0(DFPREG(rs1));
3617 3617 gen_op_load_fpr_DT1(DFPREG(rs2));
3618   - gen_op_fcmpeq16();
  3618 + tcg_gen_helper_0_0(helper_fcmpeq16);
3619 3619 gen_op_store_DT0_fpr(DFPREG(rd));
3620 3620 break;
3621 3621 case 0x02c: /* VIS I fcmpgt32 */
3622 3622 gen_op_load_fpr_DT0(DFPREG(rs1));
3623 3623 gen_op_load_fpr_DT1(DFPREG(rs2));
3624   - gen_op_fcmpgt32();
  3624 + tcg_gen_helper_0_0(helper_fcmpgt32);
3625 3625 gen_op_store_DT0_fpr(DFPREG(rd));
3626 3626 break;
3627 3627 case 0x02e: /* VIS I fcmpeq32 */
3628 3628 gen_op_load_fpr_DT0(DFPREG(rs1));
3629 3629 gen_op_load_fpr_DT1(DFPREG(rs2));
3630   - gen_op_fcmpeq32();
  3630 + tcg_gen_helper_0_0(helper_fcmpeq32);
3631 3631 gen_op_store_DT0_fpr(DFPREG(rd));
3632 3632 break;
3633 3633 case 0x031: /* VIS I fmul8x16 */
3634 3634 gen_op_load_fpr_DT0(DFPREG(rs1));
3635 3635 gen_op_load_fpr_DT1(DFPREG(rs2));
3636   - gen_op_fmul8x16();
  3636 + tcg_gen_helper_0_0(helper_fmul8x16);
3637 3637 gen_op_store_DT0_fpr(DFPREG(rd));
3638 3638 break;
3639 3639 case 0x033: /* VIS I fmul8x16au */
3640 3640 gen_op_load_fpr_DT0(DFPREG(rs1));
3641 3641 gen_op_load_fpr_DT1(DFPREG(rs2));
3642   - gen_op_fmul8x16au();
  3642 + tcg_gen_helper_0_0(helper_fmul8x16au);
3643 3643 gen_op_store_DT0_fpr(DFPREG(rd));
3644 3644 break;
3645 3645 case 0x035: /* VIS I fmul8x16al */
3646 3646 gen_op_load_fpr_DT0(DFPREG(rs1));
3647 3647 gen_op_load_fpr_DT1(DFPREG(rs2));
3648   - gen_op_fmul8x16al();
  3648 + tcg_gen_helper_0_0(helper_fmul8x16al);
3649 3649 gen_op_store_DT0_fpr(DFPREG(rd));
3650 3650 break;
3651 3651 case 0x036: /* VIS I fmul8sux16 */
3652 3652 gen_op_load_fpr_DT0(DFPREG(rs1));
3653 3653 gen_op_load_fpr_DT1(DFPREG(rs2));
3654   - gen_op_fmul8sux16();
  3654 + tcg_gen_helper_0_0(helper_fmul8sux16);
3655 3655 gen_op_store_DT0_fpr(DFPREG(rd));
3656 3656 break;
3657 3657 case 0x037: /* VIS I fmul8ulx16 */
3658 3658 gen_op_load_fpr_DT0(DFPREG(rs1));
3659 3659 gen_op_load_fpr_DT1(DFPREG(rs2));
3660   - gen_op_fmul8ulx16();
  3660 + tcg_gen_helper_0_0(helper_fmul8ulx16);
3661 3661 gen_op_store_DT0_fpr(DFPREG(rd));
3662 3662 break;
3663 3663 case 0x038: /* VIS I fmuld8sux16 */
3664 3664 gen_op_load_fpr_DT0(DFPREG(rs1));
3665 3665 gen_op_load_fpr_DT1(DFPREG(rs2));
3666   - gen_op_fmuld8sux16();
  3666 + tcg_gen_helper_0_0(helper_fmuld8sux16);
3667 3667 gen_op_store_DT0_fpr(DFPREG(rd));
3668 3668 break;
3669 3669 case 0x039: /* VIS I fmuld8ulx16 */
3670 3670 gen_op_load_fpr_DT0(DFPREG(rs1));
3671 3671 gen_op_load_fpr_DT1(DFPREG(rs2));
3672   - gen_op_fmuld8ulx16();
  3672 + tcg_gen_helper_0_0(helper_fmuld8ulx16);
3673 3673 gen_op_store_DT0_fpr(DFPREG(rd));
3674 3674 break;
3675 3675 case 0x03a: /* VIS I fpack32 */
... ... @@ -3681,13 +3681,13 @@ static void disas_sparc_insn(DisasContext * dc)
3681 3681 case 0x048: /* VIS I faligndata */
3682 3682 gen_op_load_fpr_DT0(DFPREG(rs1));
3683 3683 gen_op_load_fpr_DT1(DFPREG(rs2));
3684   - gen_op_faligndata();
  3684 + tcg_gen_helper_0_0(helper_faligndata);
3685 3685 gen_op_store_DT0_fpr(DFPREG(rd));
3686 3686 break;
3687 3687 case 0x04b: /* VIS I fpmerge */
3688 3688 gen_op_load_fpr_DT0(DFPREG(rs1));
3689 3689 gen_op_load_fpr_DT1(DFPREG(rs2));
3690   - gen_op_fpmerge();
  3690 + tcg_gen_helper_0_0(helper_fpmerge);
3691 3691 gen_op_store_DT0_fpr(DFPREG(rd));
3692 3692 break;
3693 3693 case 0x04c: /* VIS II bshuffle */
... ... @@ -3696,167 +3696,167 @@ static void disas_sparc_insn(DisasContext * dc)
3696 3696 case 0x04d: /* VIS I fexpand */
3697 3697 gen_op_load_fpr_DT0(DFPREG(rs1));
3698 3698 gen_op_load_fpr_DT1(DFPREG(rs2));
3699   - gen_op_fexpand();
  3699 + tcg_gen_helper_0_0(helper_fexpand);
3700 3700 gen_op_store_DT0_fpr(DFPREG(rd));
3701 3701 break;
3702 3702 case 0x050: /* VIS I fpadd16 */
3703 3703 gen_op_load_fpr_DT0(DFPREG(rs1));
3704 3704 gen_op_load_fpr_DT1(DFPREG(rs2));
3705   - gen_op_fpadd16();
  3705 + tcg_gen_helper_0_0(helper_fpadd16);
3706 3706 gen_op_store_DT0_fpr(DFPREG(rd));
3707 3707 break;
3708 3708 case 0x051: /* VIS I fpadd16s */
3709 3709 gen_op_load_fpr_FT0(rs1);
3710 3710 gen_op_load_fpr_FT1(rs2);
3711   - gen_op_fpadd16s();
  3711 + tcg_gen_helper_0_0(helper_fpadd16s);
3712 3712 gen_op_store_FT0_fpr(rd);
3713 3713 break;
3714 3714 case 0x052: /* VIS I fpadd32 */
3715 3715 gen_op_load_fpr_DT0(DFPREG(rs1));
3716 3716 gen_op_load_fpr_DT1(DFPREG(rs2));
3717   - gen_op_fpadd32();
  3717 + tcg_gen_helper_0_0(helper_fpadd32);
3718 3718 gen_op_store_DT0_fpr(DFPREG(rd));
3719 3719 break;
3720 3720 case 0x053: /* VIS I fpadd32s */
3721 3721 gen_op_load_fpr_FT0(rs1);
3722 3722 gen_op_load_fpr_FT1(rs2);
3723   - gen_op_fpadd32s();
  3723 + tcg_gen_helper_0_0(helper_fpadd32s);
3724 3724 gen_op_store_FT0_fpr(rd);
3725 3725 break;
3726 3726 case 0x054: /* VIS I fpsub16 */
3727 3727 gen_op_load_fpr_DT0(DFPREG(rs1));
3728 3728 gen_op_load_fpr_DT1(DFPREG(rs2));
3729   - gen_op_fpsub16();
  3729 + tcg_gen_helper_0_0(helper_fpsub16);
3730 3730 gen_op_store_DT0_fpr(DFPREG(rd));
3731 3731 break;
3732 3732 case 0x055: /* VIS I fpsub16s */
3733 3733 gen_op_load_fpr_FT0(rs1);
3734 3734 gen_op_load_fpr_FT1(rs2);
3735   - gen_op_fpsub16s();
  3735 + tcg_gen_helper_0_0(helper_fpsub16s);
3736 3736 gen_op_store_FT0_fpr(rd);
3737 3737 break;
3738 3738 case 0x056: /* VIS I fpsub32 */
3739 3739 gen_op_load_fpr_DT0(DFPREG(rs1));
3740 3740 gen_op_load_fpr_DT1(DFPREG(rs2));
3741   - gen_op_fpadd32();
  3741 + tcg_gen_helper_0_0(helper_fpadd32);
3742 3742 gen_op_store_DT0_fpr(DFPREG(rd));
3743 3743 break;
3744 3744 case 0x057: /* VIS I fpsub32s */
3745 3745 gen_op_load_fpr_FT0(rs1);
3746 3746 gen_op_load_fpr_FT1(rs2);
3747   - gen_op_fpsub32s();
  3747 + tcg_gen_helper_0_0(helper_fpsub32s);
3748 3748 gen_op_store_FT0_fpr(rd);
3749 3749 break;
3750 3750 case 0x060: /* VIS I fzero */
3751   - gen_op_movl_DT0_0();
  3751 + tcg_gen_helper_0_0(helper_movl_DT0_0);
3752 3752 gen_op_store_DT0_fpr(DFPREG(rd));
3753 3753 break;
3754 3754 case 0x061: /* VIS I fzeros */
3755   - gen_op_movl_FT0_0();
  3755 + tcg_gen_helper_0_0(helper_movl_FT0_0);
3756 3756 gen_op_store_FT0_fpr(rd);
3757 3757 break;
3758 3758 case 0x062: /* VIS I fnor */
3759 3759 gen_op_load_fpr_DT0(DFPREG(rs1));
3760 3760 gen_op_load_fpr_DT1(DFPREG(rs2));
3761   - gen_op_fnor();
  3761 + tcg_gen_helper_0_0(helper_fnor);
3762 3762 gen_op_store_DT0_fpr(DFPREG(rd));
3763 3763 break;
3764 3764 case 0x063: /* VIS I fnors */
3765 3765 gen_op_load_fpr_FT0(rs1);
3766 3766 gen_op_load_fpr_FT1(rs2);
3767   - gen_op_fnors();
  3767 + tcg_gen_helper_0_0(helper_fnors);
3768 3768 gen_op_store_FT0_fpr(rd);
3769 3769 break;
3770 3770 case 0x064: /* VIS I fandnot2 */
3771 3771 gen_op_load_fpr_DT1(DFPREG(rs1));
3772 3772 gen_op_load_fpr_DT0(DFPREG(rs2));
3773   - gen_op_fandnot();
  3773 + tcg_gen_helper_0_0(helper_fandnot);
3774 3774 gen_op_store_DT0_fpr(DFPREG(rd));
3775 3775 break;
3776 3776 case 0x065: /* VIS I fandnot2s */
3777 3777 gen_op_load_fpr_FT1(rs1);
3778 3778 gen_op_load_fpr_FT0(rs2);
3779   - gen_op_fandnots();
  3779 + tcg_gen_helper_0_0(helper_fandnots);
3780 3780 gen_op_store_FT0_fpr(rd);
3781 3781 break;
3782 3782 case 0x066: /* VIS I fnot2 */
3783 3783 gen_op_load_fpr_DT1(DFPREG(rs2));
3784   - gen_op_fnot();
  3784 + tcg_gen_helper_0_0(helper_fnot);
3785 3785 gen_op_store_DT0_fpr(DFPREG(rd));
3786 3786 break;
3787 3787 case 0x067: /* VIS I fnot2s */
3788 3788 gen_op_load_fpr_FT1(rs2);
3789   - gen_op_fnot();
  3789 + tcg_gen_helper_0_0(helper_fnot);
3790 3790 gen_op_store_FT0_fpr(rd);
3791 3791 break;
3792 3792 case 0x068: /* VIS I fandnot1 */
3793 3793 gen_op_load_fpr_DT0(DFPREG(rs1));
3794 3794 gen_op_load_fpr_DT1(DFPREG(rs2));
3795   - gen_op_fandnot();
  3795 + tcg_gen_helper_0_0(helper_fandnot);
3796 3796 gen_op_store_DT0_fpr(DFPREG(rd));
3797 3797 break;
3798 3798 case 0x069: /* VIS I fandnot1s */
3799 3799 gen_op_load_fpr_FT0(rs1);
3800 3800 gen_op_load_fpr_FT1(rs2);
3801   - gen_op_fandnots();
  3801 + tcg_gen_helper_0_0(helper_fandnots);
3802 3802 gen_op_store_FT0_fpr(rd);
3803 3803 break;
3804 3804 case 0x06a: /* VIS I fnot1 */
3805 3805 gen_op_load_fpr_DT1(DFPREG(rs1));
3806   - gen_op_fnot();
  3806 + tcg_gen_helper_0_0(helper_fnot);
3807 3807 gen_op_store_DT0_fpr(DFPREG(rd));
3808 3808 break;
3809 3809 case 0x06b: /* VIS I fnot1s */
3810 3810 gen_op_load_fpr_FT1(rs1);
3811   - gen_op_fnot();
  3811 + tcg_gen_helper_0_0(helper_fnot);
3812 3812 gen_op_store_FT0_fpr(rd);
3813 3813 break;
3814 3814 case 0x06c: /* VIS I fxor */
3815 3815 gen_op_load_fpr_DT0(DFPREG(rs1));
3816 3816 gen_op_load_fpr_DT1(DFPREG(rs2));
3817   - gen_op_fxor();
  3817 + tcg_gen_helper_0_0(helper_fxor);
3818 3818 gen_op_store_DT0_fpr(DFPREG(rd));
3819 3819 break;
3820 3820 case 0x06d: /* VIS I fxors */
3821 3821 gen_op_load_fpr_FT0(rs1);
3822 3822 gen_op_load_fpr_FT1(rs2);
3823   - gen_op_fxors();
  3823 + tcg_gen_helper_0_0(helper_fxors);
3824 3824 gen_op_store_FT0_fpr(rd);
3825 3825 break;
3826 3826 case 0x06e: /* VIS I fnand */
3827 3827 gen_op_load_fpr_DT0(DFPREG(rs1));
3828 3828 gen_op_load_fpr_DT1(DFPREG(rs2));
3829   - gen_op_fnand();
  3829 + tcg_gen_helper_0_0(helper_fnand);
3830 3830 gen_op_store_DT0_fpr(DFPREG(rd));
3831 3831 break;
3832 3832 case 0x06f: /* VIS I fnands */
3833 3833 gen_op_load_fpr_FT0(rs1);
3834 3834 gen_op_load_fpr_FT1(rs2);
3835   - gen_op_fnands();
  3835 + tcg_gen_helper_0_0(helper_fnands);
3836 3836 gen_op_store_FT0_fpr(rd);
3837 3837 break;
3838 3838 case 0x070: /* VIS I fand */
3839 3839 gen_op_load_fpr_DT0(DFPREG(rs1));
3840 3840 gen_op_load_fpr_DT1(DFPREG(rs2));
3841   - gen_op_fand();
  3841 + tcg_gen_helper_0_0(helper_fand);
3842 3842 gen_op_store_DT0_fpr(DFPREG(rd));
3843 3843 break;
3844 3844 case 0x071: /* VIS I fands */
3845 3845 gen_op_load_fpr_FT0(rs1);
3846 3846 gen_op_load_fpr_FT1(rs2);
3847   - gen_op_fands();
  3847 + tcg_gen_helper_0_0(helper_fands);
3848 3848 gen_op_store_FT0_fpr(rd);
3849 3849 break;
3850 3850 case 0x072: /* VIS I fxnor */
3851 3851 gen_op_load_fpr_DT0(DFPREG(rs1));
3852 3852 gen_op_load_fpr_DT1(DFPREG(rs2));
3853   - gen_op_fxnor();
  3853 + tcg_gen_helper_0_0(helper_fxnor);
3854 3854 gen_op_store_DT0_fpr(DFPREG(rd));
3855 3855 break;
3856 3856 case 0x073: /* VIS I fxnors */
3857 3857 gen_op_load_fpr_FT0(rs1);
3858 3858 gen_op_load_fpr_FT1(rs2);
3859   - gen_op_fxnors();
  3859 + tcg_gen_helper_0_0(helper_fxnors);
3860 3860 gen_op_store_FT0_fpr(rd);
3861 3861 break;
3862 3862 case 0x074: /* VIS I fsrc1 */
... ... @@ -3870,13 +3870,13 @@ static void disas_sparc_insn(DisasContext * dc)
3870 3870 case 0x076: /* VIS I fornot2 */
3871 3871 gen_op_load_fpr_DT1(DFPREG(rs1));
3872 3872 gen_op_load_fpr_DT0(DFPREG(rs2));
3873   - gen_op_fornot();
  3873 + tcg_gen_helper_0_0(helper_fornot);
3874 3874 gen_op_store_DT0_fpr(DFPREG(rd));
3875 3875 break;
3876 3876 case 0x077: /* VIS I fornot2s */
3877 3877 gen_op_load_fpr_FT1(rs1);
3878 3878 gen_op_load_fpr_FT0(rs2);
3879   - gen_op_fornots();
  3879 + tcg_gen_helper_0_0(helper_fornots);
3880 3880 gen_op_store_FT0_fpr(rd);
3881 3881 break;
3882 3882 case 0x078: /* VIS I fsrc2 */
... ... @@ -3890,33 +3890,33 @@ static void disas_sparc_insn(DisasContext * dc)
3890 3890 case 0x07a: /* VIS I fornot1 */
3891 3891 gen_op_load_fpr_DT0(DFPREG(rs1));
3892 3892 gen_op_load_fpr_DT1(DFPREG(rs2));
3893   - gen_op_fornot();
  3893 + tcg_gen_helper_0_0(helper_fornot);
3894 3894 gen_op_store_DT0_fpr(DFPREG(rd));
3895 3895 break;
3896 3896 case 0x07b: /* VIS I fornot1s */
3897 3897 gen_op_load_fpr_FT0(rs1);
3898 3898 gen_op_load_fpr_FT1(rs2);
3899   - gen_op_fornots();
  3899 + tcg_gen_helper_0_0(helper_fornots);
3900 3900 gen_op_store_FT0_fpr(rd);
3901 3901 break;
3902 3902 case 0x07c: /* VIS I for */
3903 3903 gen_op_load_fpr_DT0(DFPREG(rs1));
3904 3904 gen_op_load_fpr_DT1(DFPREG(rs2));
3905   - gen_op_for();
  3905 + tcg_gen_helper_0_0(helper_for);
3906 3906 gen_op_store_DT0_fpr(DFPREG(rd));
3907 3907 break;
3908 3908 case 0x07d: /* VIS I fors */
3909 3909 gen_op_load_fpr_FT0(rs1);
3910 3910 gen_op_load_fpr_FT1(rs2);
3911   - gen_op_fors();
  3911 + tcg_gen_helper_0_0(helper_fors);
3912 3912 gen_op_store_FT0_fpr(rd);
3913 3913 break;
3914 3914 case 0x07e: /* VIS I fone */
3915   - gen_op_movl_DT0_1();
  3915 + tcg_gen_helper_0_0(helper_movl_DT0_1);
3916 3916 gen_op_store_DT0_fpr(DFPREG(rd));
3917 3917 break;
3918 3918 case 0x07f: /* VIS I fones */
3919   - gen_op_movl_FT0_1();
  3919 + tcg_gen_helper_0_0(helper_movl_FT0_1);
3920 3920 gen_op_store_FT0_fpr(rd);
3921 3921 break;
3922 3922 case 0x080: /* VIS I shutdown */
... ...