gwj / at91sam9263 · Commits

Commit ff07ec8309a2e6d74b5f7585e51c5693cc9520f2

Authored by blueswir1
1 parent 75b680e5

Convert float move ops to TCG 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4090 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 74 additions and 325 deletions
target-sparc/fop_template.h deleted 100644 → 0
  View file @75b680e
1   -/*
2   - * SPARC micro operations (templates for various register related
3   - * operations)
4   - *
5   - * Copyright (c) 2003 Fabrice Bellard
6   - *
7   - * This library is free software; you can redistribute it and/or
8   - * modify it under the terms of the GNU Lesser General Public
9   - * License as published by the Free Software Foundation; either
10   - * version 2 of the License, or (at your option) any later version.
11   - *
12   - * This library is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15   - * Lesser General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU Lesser General Public
18   - * License along with this library; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20   - */
21   -
22   -/* floating point registers moves */
23   -void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void)
24   -{
25   - FT0 = REG;
26   -}
27   -
28   -void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void)
29   -{
30   - REG = FT0;
31   -}
32   -
33   -void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void)
34   -{
35   - FT1 = REG;
36   -}
37   -
38   -void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void)
39   -{
40   - REG = FT1;
41   -}
42   -
43   -/* double floating point registers moves */
44   -void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void)
45   -{
46   - CPU_DoubleU u;
47   - uint32_t *p = (uint32_t *)®
48   - u.l.lower = *(p +1);
49   - u.l.upper = *p;
50   - DT0 = u.d;
51   -}
52   -
53   -void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void)
54   -{
55   - CPU_DoubleU u;
56   - uint32_t *p = (uint32_t *)®
57   - u.d = DT0;
58   - *(p +1) = u.l.lower;
59   - *p = u.l.upper;
60   -}
61   -
62   -void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void)
63   -{
64   - CPU_DoubleU u;
65   - uint32_t *p = (uint32_t *)®
66   - u.l.lower = *(p +1);
67   - u.l.upper = *p;
68   - DT1 = u.d;
69   -}
70   -
71   -void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void)
72   -{
73   - CPU_DoubleU u;
74   - uint32_t *p = (uint32_t *)®
75   - u.d = DT1;
76   - *(p +1) = u.l.lower;
77   - *p = u.l.upper;
78   -}
79   -
80   -#if defined(CONFIG_USER_ONLY)
81   -/* quad floating point registers moves */
82   -void OPPROTO glue(op_load_fpr_QT0_fpr, REGNAME)(void)
83   -{
84   - CPU_QuadU u;
85   - uint32_t *p = (uint32_t *)®
86   - u.l.lowest = *(p + 3);
87   - u.l.lower = *(p + 2);
88   - u.l.upper = *(p + 1);
89   - u.l.upmost = *p;
90   - QT0 = u.q;
91   -}
92   -
93   -void OPPROTO glue(op_store_QT0_fpr_fpr, REGNAME)(void)
94   -{
95   - CPU_QuadU u;
96   - uint32_t *p = (uint32_t *)®
97   - u.q = QT0;
98   - *(p + 3) = u.l.lowest;
99   - *(p + 2) = u.l.lower;
100   - *(p + 1) = u.l.upper;
101   - *p = u.l.upmost;
102   -}
103   -
104   -void OPPROTO glue(op_load_fpr_QT1_fpr, REGNAME)(void)
105   -{
106   - CPU_QuadU u;
107   - uint32_t *p = (uint32_t *)®
108   - u.l.lowest = *(p + 3);
109   - u.l.lower = *(p + 2);
110   - u.l.upper = *(p + 1);
111   - u.l.upmost = *p;
112   - QT1 = u.q;
113   -}
114   -
115   -void OPPROTO glue(op_store_QT1_fpr_fpr, REGNAME)(void)
116   -{
117   - CPU_QuadU u;
118   - uint32_t *p = (uint32_t *)®
119   - u.q = QT1;
120   - *(p + 3) = u.l.lowest;
121   - *(p + 2) = u.l.lower;
122   - *(p + 1) = u.l.upper;
123   - *p = u.l.upmost;
124   -}
125   -#endif
126   -
127   -#undef REG
128   -#undef REGNAME
target-sparc/op.c
  View file @ff07ec8
... ... @@ -21,154 +21,6 @@
21 21 #include "exec.h"
22 22 #include "helper.h"
23 23  
24   -#define REGNAME f0
25   -#define REG (env->fpr[0])
26   -#include "fop_template.h"
27   -#define REGNAME f1
28   -#define REG (env->fpr[1])
29   -#include "fop_template.h"
30   -#define REGNAME f2
31   -#define REG (env->fpr[2])
32   -#include "fop_template.h"
33   -#define REGNAME f3
34   -#define REG (env->fpr[3])
35   -#include "fop_template.h"
36   -#define REGNAME f4
37   -#define REG (env->fpr[4])
38   -#include "fop_template.h"
39   -#define REGNAME f5
40   -#define REG (env->fpr[5])
41   -#include "fop_template.h"
42   -#define REGNAME f6
43   -#define REG (env->fpr[6])
44   -#include "fop_template.h"
45   -#define REGNAME f7
46   -#define REG (env->fpr[7])
47   -#include "fop_template.h"
48   -#define REGNAME f8
49   -#define REG (env->fpr[8])
50   -#include "fop_template.h"
51   -#define REGNAME f9
52   -#define REG (env->fpr[9])
53   -#include "fop_template.h"
54   -#define REGNAME f10
55   -#define REG (env->fpr[10])
56   -#include "fop_template.h"
57   -#define REGNAME f11
58   -#define REG (env->fpr[11])
59   -#include "fop_template.h"
60   -#define REGNAME f12
61   -#define REG (env->fpr[12])
62   -#include "fop_template.h"
63   -#define REGNAME f13
64   -#define REG (env->fpr[13])
65   -#include "fop_template.h"
66   -#define REGNAME f14
67   -#define REG (env->fpr[14])
68   -#include "fop_template.h"
69   -#define REGNAME f15
70   -#define REG (env->fpr[15])
71   -#include "fop_template.h"
72   -#define REGNAME f16
73   -#define REG (env->fpr[16])
74   -#include "fop_template.h"
75   -#define REGNAME f17
76   -#define REG (env->fpr[17])
77   -#include "fop_template.h"
78   -#define REGNAME f18
79   -#define REG (env->fpr[18])
80   -#include "fop_template.h"
81   -#define REGNAME f19
82   -#define REG (env->fpr[19])
83   -#include "fop_template.h"
84   -#define REGNAME f20
85   -#define REG (env->fpr[20])
86   -#include "fop_template.h"
87   -#define REGNAME f21
88   -#define REG (env->fpr[21])
89   -#include "fop_template.h"
90   -#define REGNAME f22
91   -#define REG (env->fpr[22])
92   -#include "fop_template.h"
93   -#define REGNAME f23
94   -#define REG (env->fpr[23])
95   -#include "fop_template.h"
96   -#define REGNAME f24
97   -#define REG (env->fpr[24])
98   -#include "fop_template.h"
99   -#define REGNAME f25
100   -#define REG (env->fpr[25])
101   -#include "fop_template.h"
102   -#define REGNAME f26
103   -#define REG (env->fpr[26])
104   -#include "fop_template.h"
105   -#define REGNAME f27
106   -#define REG (env->fpr[27])
107   -#include "fop_template.h"
108   -#define REGNAME f28
109   -#define REG (env->fpr[28])
110   -#include "fop_template.h"
111   -#define REGNAME f29
112   -#define REG (env->fpr[29])
113   -#include "fop_template.h"
114   -#define REGNAME f30
115   -#define REG (env->fpr[30])
116   -#include "fop_template.h"
117   -#define REGNAME f31
118   -#define REG (env->fpr[31])
119   -#include "fop_template.h"
120   -
121   -#ifdef TARGET_SPARC64
122   -#define REGNAME f32
123   -#define REG (env->fpr[32])
124   -#include "fop_template.h"
125   -#define REGNAME f34
126   -#define REG (env->fpr[34])
127   -#include "fop_template.h"
128   -#define REGNAME f36
129   -#define REG (env->fpr[36])
130   -#include "fop_template.h"
131   -#define REGNAME f38
132   -#define REG (env->fpr[38])
133   -#include "fop_template.h"
134   -#define REGNAME f40
135   -#define REG (env->fpr[40])
136   -#include "fop_template.h"
137   -#define REGNAME f42
138   -#define REG (env->fpr[42])
139   -#include "fop_template.h"
140   -#define REGNAME f44
141   -#define REG (env->fpr[44])
142   -#include "fop_template.h"
143   -#define REGNAME f46
144   -#define REG (env->fpr[46])
145   -#include "fop_template.h"
146   -#define REGNAME f48
147   -#define REG (env->fpr[47])
148   -#include "fop_template.h"
149   -#define REGNAME f50
150   -#define REG (env->fpr[50])
151   -#include "fop_template.h"
152   -#define REGNAME f52
153   -#define REG (env->fpr[52])
154   -#include "fop_template.h"
155   -#define REGNAME f54
156   -#define REG (env->fpr[54])
157   -#include "fop_template.h"
158   -#define REGNAME f56
159   -#define REG (env->fpr[56])
160   -#include "fop_template.h"
161   -#define REGNAME f58
162   -#define REG (env->fpr[58])
163   -#include "fop_template.h"
164   -#define REGNAME f60
165   -#define REG (env->fpr[60])
166   -#include "fop_template.h"
167   -#define REGNAME f62
168   -#define REG (env->fpr[62])
169   -#include "fop_template.h"
170   -#endif
171   -
172 24 /* Load and store */
173 25 #define MEMSUFFIX _raw
174 26 #include "op_mem.h"
... ...
target-sparc/translate.c
  View file @ff07ec8
... ... @@ -114,60 +114,85 @@ static int sign_extend(int x, int len)
114 114  
115 115 static void disas_sparc_insn(DisasContext * dc);
116 116  
117   -#ifdef TARGET_SPARC64
118   -#define GEN32(func, NAME) \
119   -static GenOpFunc * const NAME ## _table [64] = { \
120   -NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
121   -NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
122   -NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
123   -NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
124   -NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
125   -NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
126   -NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
127   -NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
128   -NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
129   -NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
130   -NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
131   -NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
132   -}; \
133   -static inline void func(int n) \
134   -{ \
135   - NAME ## _table[n](); \
  117 +/* floating point registers moves */
  118 +static void gen_op_load_fpr_FT0(unsigned int src)
  119 +{
  120 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  121 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
136 122 }
137   -#else
138   -#define GEN32(func, NAME) \
139   -static GenOpFunc *const NAME ## _table [32] = { \
140   -NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
141   -NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
142   -NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
143   -NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
144   -NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
145   -NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
146   -NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
147   -NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
148   -}; \
149   -static inline void func(int n) \
150   -{ \
151   - NAME ## _table[n](); \
  123 +
  124 +static void gen_op_load_fpr_FT1(unsigned int src)
  125 +{
  126 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  127 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1));
152 128 }
153   -#endif
154 129  
155   -/* floating point registers moves */
156   -GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
157   -GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
158   -GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
159   -GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
  130 +static void gen_op_store_FT0_fpr(unsigned int dst)
  131 +{
  132 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
  133 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
  134 +}
160 135  
161   -GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
162   -GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
163   -GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
164   -GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
  136 +static void gen_op_load_fpr_DT0(unsigned int src)
  137 +{
  138 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  139 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
  140 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  141 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
  142 +}
165 143  
166   -#if defined(CONFIG_USER_ONLY)
167   -GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
168   -GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
169   -GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
170   -GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
  144 +static void gen_op_load_fpr_DT1(unsigned int src)
  145 +{
  146 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  147 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
  148 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  149 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
  150 +}
  151 +
  152 +static void gen_op_store_DT0_fpr(unsigned int dst)
  153 +{
  154 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
  155 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
  156 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
  157 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
  158 +}
  159 +
  160 +#ifdef CONFIG_USER_ONLY
  161 +static void gen_op_load_fpr_QT0(unsigned int src)
  162 +{
  163 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  164 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
  165 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  166 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
  167 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
  168 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
  169 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
  170 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
  171 +}
  172 +
  173 +static void gen_op_load_fpr_QT1(unsigned int src)
  174 +{
  175 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  176 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
  177 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
  178 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
  179 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
  180 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
  181 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
  182 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
  183 +}
  184 +
  185 +static void gen_op_store_QT0_fpr(unsigned int dst)
  186 +{
  187 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
  188 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
  189 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
  190 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
  191 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
  192 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
  193 + tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
  194 + tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
  195 +}
171 196 #endif
172 197  
173 198 /* moves */
... ...