gwj / at91sam9263 · Commits

Commit 3bf73a4980be9578a7430f38c868a0e80b0d3d67

Authored by aurel32
1 parent 8f99cc6c

SH4: use uint32_t/i32 based types/ops 

Use uint32_t/i32 based types/ops to stay consistent with previous dyngen
code. Thanks to Paul Brook for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 30 additions and 30 deletions
target-sh4/translate.c
  View file @3bf73a4
@@ -79,21 +79,21 @@ static void sh4_translate_init(void) @@ -79,21 +79,21 @@ static void sh4_translate_init(void)
79 } 79 }
80 80
81 /* General purpose registers moves. */ 81 /* General purpose registers moves. */
82 -static inline void gen_movl_imm_rN(target_ulong arg, int reg) 82 +static inline void gen_movl_imm_rN(uint32_t arg, int reg)
83 { 83 {
84 - TCGv tmp = tcg_const_tl(arg);  
85 - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, gregs[reg])); 84 + TCGv tmp = tcg_const_i32(arg);
  85 + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
86 tcg_temp_free(tmp); 86 tcg_temp_free(tmp);
87 } 87 }
88 88
89 static always_inline void gen_movl_T_rN (TCGv t, int reg) 89 static always_inline void gen_movl_T_rN (TCGv t, int reg)
90 { 90 {
91 - tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, gregs[reg])); 91 + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
92 } 92 }
93 93
94 static always_inline void gen_movl_rN_T (TCGv t, int reg) 94 static always_inline void gen_movl_rN_T (TCGv t, int reg)
95 { 95 {
96 - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, gregs[reg])); 96 + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
97 } 97 }
98 98
99 #ifdef CONFIG_USER_ONLY 99 #ifdef CONFIG_USER_ONLY
@@ -355,12 +355,12 @@ void _decode_opc(DisasContext * ctx) @@ -355,12 +355,12 @@ void _decode_opc(DisasContext * ctx)
355 gen_movl_imm_rN(B7_0s, REG(B11_8)); 355 gen_movl_imm_rN(B7_0s, REG(B11_8));
356 return; 356 return;
357 case 0x9000: /* mov.w @(disp,PC),Rn */ 357 case 0x9000: /* mov.w @(disp,PC),Rn */
358 - tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2); 358 + tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
359 gen_op_ldw_T0_T0(ctx); 359 gen_op_ldw_T0_T0(ctx);
360 gen_movl_T_rN(cpu_T[0], REG(B11_8)); 360 gen_movl_T_rN(cpu_T[0], REG(B11_8));
361 return; 361 return;
362 case 0xd000: /* mov.l @(disp,PC),Rn */ 362 case 0xd000: /* mov.l @(disp,PC),Rn */
363 - tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3); 363 + tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
364 gen_op_ldl_T0_T0(ctx); 364 gen_op_ldl_T0_T0(ctx);
365 gen_movl_T_rN(cpu_T[0], REG(B11_8)); 365 gen_movl_T_rN(cpu_T[0], REG(B11_8));
366 return; 366 return;
@@ -585,30 +585,30 @@ void _decode_opc(DisasContext * ctx) @@ -585,30 +585,30 @@ void _decode_opc(DisasContext * ctx)
585 return; 585 return;
586 case 0x600e: /* exts.b Rm,Rn */ 586 case 0x600e: /* exts.b Rm,Rn */
587 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 587 gen_movl_rN_T(cpu_T[0], REG(B7_4));
588 - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);  
589 - tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); 588 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
  589 + tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
590 gen_movl_T_rN(cpu_T[0], REG(B11_8)); 590 gen_movl_T_rN(cpu_T[0], REG(B11_8));
591 return; 591 return;
592 case 0x600f: /* exts.w Rm,Rn */ 592 case 0x600f: /* exts.w Rm,Rn */
593 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 593 gen_movl_rN_T(cpu_T[0], REG(B7_4));
594 - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);  
595 - tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); 594 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
  595 + tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
596 gen_movl_T_rN(cpu_T[0], REG(B11_8)); 596 gen_movl_T_rN(cpu_T[0], REG(B11_8));
597 return; 597 return;
598 case 0x600c: /* extu.b Rm,Rn */ 598 case 0x600c: /* extu.b Rm,Rn */
599 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 599 gen_movl_rN_T(cpu_T[0], REG(B7_4));
600 - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); 600 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
601 gen_movl_T_rN(cpu_T[0], REG(B11_8)); 601 gen_movl_T_rN(cpu_T[0], REG(B11_8));
602 return; 602 return;
603 case 0x600d: /* extu.w Rm,Rn */ 603 case 0x600d: /* extu.w Rm,Rn */
604 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 604 gen_movl_rN_T(cpu_T[0], REG(B7_4));
605 - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); 605 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
606 gen_movl_T_rN(cpu_T[0], REG(B11_8)); 606 gen_movl_T_rN(cpu_T[0], REG(B11_8));
607 return; 607 return;
608 case 0x000f: /* mac.l @Rm+,@Rn+ */ 608 case 0x000f: /* mac.l @Rm+,@Rn+ */
609 gen_movl_rN_T(cpu_T[0], REG(B11_8)); 609 gen_movl_rN_T(cpu_T[0], REG(B11_8));
610 gen_op_ldl_T0_T0(ctx); 610 gen_op_ldl_T0_T0(ctx);
611 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 611 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
612 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 612 gen_movl_rN_T(cpu_T[0], REG(B7_4));
613 gen_op_ldl_T0_T0(ctx); 613 gen_op_ldl_T0_T0(ctx);
614 gen_op_macl_T0_T1(); 614 gen_op_macl_T0_T1();
@@ -618,7 +618,7 @@ void _decode_opc(DisasContext * ctx) @@ -618,7 +618,7 @@ void _decode_opc(DisasContext * ctx)
618 case 0x400f: /* mac.w @Rm+,@Rn+ */ 618 case 0x400f: /* mac.w @Rm+,@Rn+ */
619 gen_movl_rN_T(cpu_T[0], REG(B11_8)); 619 gen_movl_rN_T(cpu_T[0], REG(B11_8));
620 gen_op_ldl_T0_T0(ctx); 620 gen_op_ldl_T0_T0(ctx);
621 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 621 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
622 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 622 gen_movl_rN_T(cpu_T[0], REG(B7_4));
623 gen_op_ldl_T0_T0(ctx); 623 gen_op_ldl_T0_T0(ctx);
624 gen_op_macw_T0_T1(); 624 gen_op_macw_T0_T1();
@@ -632,18 +632,18 @@ void _decode_opc(DisasContext * ctx) @@ -632,18 +632,18 @@ void _decode_opc(DisasContext * ctx)
632 return; 632 return;
633 case 0x200f: /* muls.w Rm,Rn */ 633 case 0x200f: /* muls.w Rm,Rn */
634 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 634 gen_movl_rN_T(cpu_T[0], REG(B7_4));
635 - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);  
636 - tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); 635 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
  636 + tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
637 gen_movl_rN_T(cpu_T[1], REG(B11_8)); 637 gen_movl_rN_T(cpu_T[1], REG(B11_8));
638 - tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);  
639 - tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); 638 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
  639 + tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
640 gen_op_mulsw_T0_T1(); 640 gen_op_mulsw_T0_T1();
641 return; 641 return;
642 case 0x200e: /* mulu.w Rm,Rn */ 642 case 0x200e: /* mulu.w Rm,Rn */
643 gen_movl_rN_T(cpu_T[0], REG(B7_4)); 643 gen_movl_rN_T(cpu_T[0], REG(B7_4));
644 - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); 644 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
645 gen_movl_rN_T(cpu_T[1], REG(B11_8)); 645 gen_movl_rN_T(cpu_T[1], REG(B11_8));
646 - tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff); 646 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
647 gen_op_muluw_T0_T1(); 647 gen_op_muluw_T0_T1();
648 return; 648 return;
649 case 0x600b: /* neg Rm,Rn */ 649 case 0x600b: /* neg Rm,Rn */
@@ -843,7 +843,7 @@ void _decode_opc(DisasContext * ctx) @@ -843,7 +843,7 @@ void _decode_opc(DisasContext * ctx)
843 case 0xcd00: /* and.b #imm,@(R0,GBR) */ 843 case 0xcd00: /* and.b #imm,@(R0,GBR) */
844 gen_movl_rN_T(cpu_T[0], REG(0)); 844 gen_movl_rN_T(cpu_T[0], REG(0));
845 gen_op_addl_GBR_T0(); 845 gen_op_addl_GBR_T0();
846 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 846 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
847 gen_op_ldub_T0_T0(ctx); 847 gen_op_ldub_T0_T0(ctx);
848 gen_op_and_imm_T0(B7_0); 848 gen_op_and_imm_T0(B7_0);
849 gen_op_stb_T0_T1(ctx); 849 gen_op_stb_T0_T1(ctx);
@@ -895,21 +895,21 @@ void _decode_opc(DisasContext * ctx) @@ -895,21 +895,21 @@ void _decode_opc(DisasContext * ctx)
895 case 0xc000: /* mov.b R0,@(disp,GBR) */ 895 case 0xc000: /* mov.b R0,@(disp,GBR) */
896 gen_op_stc_gbr_T0(); 896 gen_op_stc_gbr_T0();
897 gen_op_addl_imm_T0(B7_0); 897 gen_op_addl_imm_T0(B7_0);
898 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 898 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
899 gen_movl_rN_T(cpu_T[0], REG(0)); 899 gen_movl_rN_T(cpu_T[0], REG(0));
900 gen_op_stb_T0_T1(ctx); 900 gen_op_stb_T0_T1(ctx);
901 return; 901 return;
902 case 0xc100: /* mov.w R0,@(disp,GBR) */ 902 case 0xc100: /* mov.w R0,@(disp,GBR) */
903 gen_op_stc_gbr_T0(); 903 gen_op_stc_gbr_T0();
904 gen_op_addl_imm_T0(B7_0 * 2); 904 gen_op_addl_imm_T0(B7_0 * 2);
905 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 905 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
906 gen_movl_rN_T(cpu_T[0], REG(0)); 906 gen_movl_rN_T(cpu_T[0], REG(0));
907 gen_op_stw_T0_T1(ctx); 907 gen_op_stw_T0_T1(ctx);
908 return; 908 return;
909 case 0xc200: /* mov.l R0,@(disp,GBR) */ 909 case 0xc200: /* mov.l R0,@(disp,GBR) */
910 gen_op_stc_gbr_T0(); 910 gen_op_stc_gbr_T0();
911 gen_op_addl_imm_T0(B7_0 * 4); 911 gen_op_addl_imm_T0(B7_0 * 4);
912 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 912 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
913 gen_movl_rN_T(cpu_T[0], REG(0)); 913 gen_movl_rN_T(cpu_T[0], REG(0));
914 gen_op_stl_T0_T1(ctx); 914 gen_op_stl_T0_T1(ctx);
915 return; 915 return;
@@ -947,7 +947,7 @@ void _decode_opc(DisasContext * ctx) @@ -947,7 +947,7 @@ void _decode_opc(DisasContext * ctx)
947 case 0xcf00: /* or.b #imm,@(R0,GBR) */ 947 case 0xcf00: /* or.b #imm,@(R0,GBR) */
948 gen_movl_rN_T(cpu_T[0], REG(0)); 948 gen_movl_rN_T(cpu_T[0], REG(0));
949 gen_op_addl_GBR_T0(); 949 gen_op_addl_GBR_T0();
950 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 950 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
951 gen_op_ldub_T0_T0(ctx); 951 gen_op_ldub_T0_T0(ctx);
952 gen_op_or_imm_T0(B7_0); 952 gen_op_or_imm_T0(B7_0);
953 gen_op_stb_T0_T1(ctx); 953 gen_op_stb_T0_T1(ctx);
@@ -972,7 +972,7 @@ void _decode_opc(DisasContext * ctx) @@ -972,7 +972,7 @@ void _decode_opc(DisasContext * ctx)
972 case 0xce00: /* xor.b #imm,@(R0,GBR) */ 972 case 0xce00: /* xor.b #imm,@(R0,GBR) */
973 gen_movl_rN_T(cpu_T[0], REG(0)); 973 gen_movl_rN_T(cpu_T[0], REG(0));
974 gen_op_addl_GBR_T0(); 974 gen_op_addl_GBR_T0();
975 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 975 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
976 gen_op_ldub_T0_T0(ctx); 976 gen_op_ldub_T0_T0(ctx);
977 gen_op_xor_imm_T0(B7_0); 977 gen_op_xor_imm_T0(B7_0);
978 gen_op_stb_T0_T1(ctx); 978 gen_op_stb_T0_T1(ctx);
@@ -1142,7 +1142,7 @@ void _decode_opc(DisasContext * ctx) @@ -1142,7 +1142,7 @@ void _decode_opc(DisasContext * ctx)
1142 return; 1142 return;
1143 case 0x401b: /* tas.b @Rn */ 1143 case 0x401b: /* tas.b @Rn */
1144 gen_movl_rN_T(cpu_T[0], REG(B11_8)); 1144 gen_movl_rN_T(cpu_T[0], REG(B11_8));
1145 - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); 1145 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
1146 gen_op_ldub_T0_T0(ctx); 1146 gen_op_ldub_T0_T0(ctx);
1147 gen_op_cmp_eq_imm_T0(0); 1147 gen_op_cmp_eq_imm_T0(0);
1148 gen_op_or_imm_T0(0x80); 1148 gen_op_or_imm_T0(0x80);
@@ -1213,14 +1213,14 @@ void _decode_opc(DisasContext * ctx) @@ -1213,14 +1213,14 @@ void _decode_opc(DisasContext * ctx)
1213 break; 1213 break;
1214 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ 1214 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1215 if (!(ctx->fpscr & FPSCR_PR)) { 1215 if (!(ctx->fpscr & FPSCR_PR)) {
1216 - tcg_gen_movi_tl(cpu_T[0], 0); 1216 + tcg_gen_movi_i32(cpu_T[0], 0);
1217 gen_op_fmov_T0_frN(FREG(B11_8)); 1217 gen_op_fmov_T0_frN(FREG(B11_8));
1218 return; 1218 return;
1219 } 1219 }
1220 break; 1220 break;
1221 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ 1221 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1222 if (!(ctx->fpscr & FPSCR_PR)) { 1222 if (!(ctx->fpscr & FPSCR_PR)) {
1223 - tcg_gen_movi_tl(cpu_T[0], 0x3f800000); 1223 + tcg_gen_movi_i32(cpu_T[0], 0x3f800000);
1224 gen_op_fmov_T0_frN(FREG(B11_8)); 1224 gen_op_fmov_T0_frN(FREG(B11_8));
1225 return; 1225 return;
1226 } 1226 }