gwj / at91sam9263 · Commits

Commit 3bf73a4980be9578a7430f38c868a0e80b0d3d67

Authored by aurel32
1 parent 8f99cc6c

SH4: use uint32_t/i32 based types/ops 

Use uint32_t/i32 based types/ops to stay consistent with previous dyngen
code. Thanks to Paul Brook for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 30 additions and 30 deletions
target-sh4/translate.c
  View file @3bf73a4
... ... @@ -79,21 +79,21 @@ static void sh4_translate_init(void)
79 79 }
80 80  
81 81 /* General purpose registers moves. */
82   -static inline void gen_movl_imm_rN(target_ulong arg, int reg)
  82 +static inline void gen_movl_imm_rN(uint32_t arg, int reg)
83 83 {
84   - TCGv tmp = tcg_const_tl(arg);
85   - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
  84 + TCGv tmp = tcg_const_i32(arg);
  85 + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
86 86 tcg_temp_free(tmp);
87 87 }
88 88  
89 89 static always_inline void gen_movl_T_rN (TCGv t, int reg)
90 90 {
91   - tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
  91 + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
92 92 }
93 93  
94 94 static always_inline void gen_movl_rN_T (TCGv t, int reg)
95 95 {
96   - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
  96 + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
97 97 }
98 98  
99 99 #ifdef CONFIG_USER_ONLY
... ... @@ -355,12 +355,12 @@ void _decode_opc(DisasContext * ctx)
355 355 gen_movl_imm_rN(B7_0s, REG(B11_8));
356 356 return;
357 357 case 0x9000: /* mov.w @(disp,PC),Rn */
358   - tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
  358 + tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
359 359 gen_op_ldw_T0_T0(ctx);
360 360 gen_movl_T_rN(cpu_T[0], REG(B11_8));
361 361 return;
362 362 case 0xd000: /* mov.l @(disp,PC),Rn */
363   - tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
  363 + tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
364 364 gen_op_ldl_T0_T0(ctx);
365 365 gen_movl_T_rN(cpu_T[0], REG(B11_8));
366 366 return;
... ... @@ -585,30 +585,30 @@ void _decode_opc(DisasContext * ctx)
585 585 return;
586 586 case 0x600e: /* exts.b Rm,Rn */
587 587 gen_movl_rN_T(cpu_T[0], REG(B7_4));
588   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
589   - tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
  588 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
  589 + tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
590 590 gen_movl_T_rN(cpu_T[0], REG(B11_8));
591 591 return;
592 592 case 0x600f: /* exts.w Rm,Rn */
593 593 gen_movl_rN_T(cpu_T[0], REG(B7_4));
594   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
595   - tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
  594 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
  595 + tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
596 596 gen_movl_T_rN(cpu_T[0], REG(B11_8));
597 597 return;
598 598 case 0x600c: /* extu.b Rm,Rn */
599 599 gen_movl_rN_T(cpu_T[0], REG(B7_4));
600   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
  600 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
601 601 gen_movl_T_rN(cpu_T[0], REG(B11_8));
602 602 return;
603 603 case 0x600d: /* extu.w Rm,Rn */
604 604 gen_movl_rN_T(cpu_T[0], REG(B7_4));
605   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  605 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
606 606 gen_movl_T_rN(cpu_T[0], REG(B11_8));
607 607 return;
608 608 case 0x000f: /* mac.l @Rm+,@Rn+ */
609 609 gen_movl_rN_T(cpu_T[0], REG(B11_8));
610 610 gen_op_ldl_T0_T0(ctx);
611   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  611 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
612 612 gen_movl_rN_T(cpu_T[0], REG(B7_4));
613 613 gen_op_ldl_T0_T0(ctx);
614 614 gen_op_macl_T0_T1();
... ... @@ -618,7 +618,7 @@ void _decode_opc(DisasContext * ctx)
618 618 case 0x400f: /* mac.w @Rm+,@Rn+ */
619 619 gen_movl_rN_T(cpu_T[0], REG(B11_8));
620 620 gen_op_ldl_T0_T0(ctx);
621   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  621 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
622 622 gen_movl_rN_T(cpu_T[0], REG(B7_4));
623 623 gen_op_ldl_T0_T0(ctx);
624 624 gen_op_macw_T0_T1();
... ... @@ -632,18 +632,18 @@ void _decode_opc(DisasContext * ctx)
632 632 return;
633 633 case 0x200f: /* muls.w Rm,Rn */
634 634 gen_movl_rN_T(cpu_T[0], REG(B7_4));
635   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
636   - tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
  635 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
  636 + tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
637 637 gen_movl_rN_T(cpu_T[1], REG(B11_8));
638   - tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
639   - tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
  638 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
  639 + tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
640 640 gen_op_mulsw_T0_T1();
641 641 return;
642 642 case 0x200e: /* mulu.w Rm,Rn */
643 643 gen_movl_rN_T(cpu_T[0], REG(B7_4));
644   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  644 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
645 645 gen_movl_rN_T(cpu_T[1], REG(B11_8));
646   - tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
  646 + tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
647 647 gen_op_muluw_T0_T1();
648 648 return;
649 649 case 0x600b: /* neg Rm,Rn */
... ... @@ -843,7 +843,7 @@ void _decode_opc(DisasContext * ctx)
843 843 case 0xcd00: /* and.b #imm,@(R0,GBR) */
844 844 gen_movl_rN_T(cpu_T[0], REG(0));
845 845 gen_op_addl_GBR_T0();
846   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  846 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
847 847 gen_op_ldub_T0_T0(ctx);
848 848 gen_op_and_imm_T0(B7_0);
849 849 gen_op_stb_T0_T1(ctx);
... ... @@ -895,21 +895,21 @@ void _decode_opc(DisasContext * ctx)
895 895 case 0xc000: /* mov.b R0,@(disp,GBR) */
896 896 gen_op_stc_gbr_T0();
897 897 gen_op_addl_imm_T0(B7_0);
898   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  898 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
899 899 gen_movl_rN_T(cpu_T[0], REG(0));
900 900 gen_op_stb_T0_T1(ctx);
901 901 return;
902 902 case 0xc100: /* mov.w R0,@(disp,GBR) */
903 903 gen_op_stc_gbr_T0();
904 904 gen_op_addl_imm_T0(B7_0 * 2);
905   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  905 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
906 906 gen_movl_rN_T(cpu_T[0], REG(0));
907 907 gen_op_stw_T0_T1(ctx);
908 908 return;
909 909 case 0xc200: /* mov.l R0,@(disp,GBR) */
910 910 gen_op_stc_gbr_T0();
911 911 gen_op_addl_imm_T0(B7_0 * 4);
912   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  912 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
913 913 gen_movl_rN_T(cpu_T[0], REG(0));
914 914 gen_op_stl_T0_T1(ctx);
915 915 return;
... ... @@ -947,7 +947,7 @@ void _decode_opc(DisasContext * ctx)
947 947 case 0xcf00: /* or.b #imm,@(R0,GBR) */
948 948 gen_movl_rN_T(cpu_T[0], REG(0));
949 949 gen_op_addl_GBR_T0();
950   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  950 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
951 951 gen_op_ldub_T0_T0(ctx);
952 952 gen_op_or_imm_T0(B7_0);
953 953 gen_op_stb_T0_T1(ctx);
... ... @@ -972,7 +972,7 @@ void _decode_opc(DisasContext * ctx)
972 972 case 0xce00: /* xor.b #imm,@(R0,GBR) */
973 973 gen_movl_rN_T(cpu_T[0], REG(0));
974 974 gen_op_addl_GBR_T0();
975   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  975 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
976 976 gen_op_ldub_T0_T0(ctx);
977 977 gen_op_xor_imm_T0(B7_0);
978 978 gen_op_stb_T0_T1(ctx);
... ... @@ -1142,7 +1142,7 @@ void _decode_opc(DisasContext * ctx)
1142 1142 return;
1143 1143 case 0x401b: /* tas.b @Rn */
1144 1144 gen_movl_rN_T(cpu_T[0], REG(B11_8));
1145   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  1145 + tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
1146 1146 gen_op_ldub_T0_T0(ctx);
1147 1147 gen_op_cmp_eq_imm_T0(0);
1148 1148 gen_op_or_imm_T0(0x80);
... ... @@ -1213,14 +1213,14 @@ void _decode_opc(DisasContext * ctx)
1213 1213 break;
1214 1214 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1215 1215 if (!(ctx->fpscr & FPSCR_PR)) {
1216   - tcg_gen_movi_tl(cpu_T[0], 0);
  1216 + tcg_gen_movi_i32(cpu_T[0], 0);
1217 1217 gen_op_fmov_T0_frN(FREG(B11_8));
1218 1218 return;
1219 1219 }
1220 1220 break;
1221 1221 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1222 1222 if (!(ctx->fpscr & FPSCR_PR)) {
1223   - tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
  1223 + tcg_gen_movi_i32(cpu_T[0], 0x3f800000);
1224 1224 gen_op_fmov_T0_frN(FREG(B11_8));
1225 1225 return;
1226 1226 }
... ...