gwj / at91sam9263 · Commits

Commit 3bdd58a4dfaf284868e7b34f29ae74c60ad23ac9

Authored by balrog
1 parent 9617efe8

Correct the number of PXA255 GPIO lines. Reuse the PXA timers struct for PXA27x additional timers. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2789 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 17 additions and 22 deletions
hw/pxa2xx.c
  View file @3bdd58a
@@ -1645,7 +1645,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, @@ -1645,7 +1645,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
1645 1645
1646 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env); 1646 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
1647 1647
1648 - s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); 1648 + s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
1649 1649
1650 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma); 1650 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1651 1651
hw/pxa2xx_timer.c
  View file @3bdd58a
@@ -66,12 +66,7 @@ struct pxa2xx_timer0_s { @@ -66,12 +66,7 @@ struct pxa2xx_timer0_s {
66 }; 66 };
67 67
68 struct pxa2xx_timer4_s { 68 struct pxa2xx_timer4_s {
69 - uint32_t value;  
70 - int level;  
71 - qemu_irq irq;  
72 - QEMUTimer *qtimer;  
73 - int num;  
74 - void *info; 69 + struct pxa2xx_timer0_s tm;
75 int32_t oldclock; 70 int32_t oldclock;
76 int32_t clock; 71 int32_t clock;
77 uint64_t lastload; 72 uint64_t lastload;
@@ -134,7 +129,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) @@ -134,7 +129,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
134 s->tm4[counter].lastload, 129 s->tm4[counter].lastload,
135 s->tm4[counter].freq, ticks_per_sec); 130 s->tm4[counter].freq, ticks_per_sec);
136 131
137 - new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].value - now_vm), 132 + new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
138 ticks_per_sec, s->tm4[counter].freq); 133 ticks_per_sec, s->tm4[counter].freq);
139 qemu_mod_timer(s->timer[n].qtimer, new_qemu); 134 qemu_mod_timer(s->timer[n].qtimer, new_qemu);
140 } 135 }
@@ -162,7 +157,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) @@ -162,7 +157,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
162 case OSMR4: 157 case OSMR4:
163 if (!s->tm4) 158 if (!s->tm4)
164 goto badreg; 159 goto badreg;
165 - return s->tm4[tm].value; 160 + return s->tm4[tm].tm.value;
166 case OSCR: 161 case OSCR:
167 return s->clock + muldiv64(qemu_get_clock(vm_clock) - 162 return s->clock + muldiv64(qemu_get_clock(vm_clock) -
168 s->lastload, s->freq, ticks_per_sec); 163 s->lastload, s->freq, ticks_per_sec);
@@ -245,7 +240,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, @@ -245,7 +240,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
245 case OSMR4: 240 case OSMR4:
246 if (!s->tm4) 241 if (!s->tm4)
247 goto badreg; 242 goto badreg;
248 - s->tm4[tm].value = value; 243 + s->tm4[tm].tm.value = value;
249 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); 244 pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
250 break; 245 break;
251 case OSCR: 246 case OSCR:
@@ -282,10 +277,10 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, @@ -282,10 +277,10 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
282 } 277 }
283 if (s->tm4) { 278 if (s->tm4) {
284 for (i = 0; i < 8; i ++, value >>= 1) 279 for (i = 0; i < 8; i ++, value >>= 1)
285 - if (s->tm4[i].level && (value & 1))  
286 - s->tm4[i].level = 0; 280 + if (s->tm4[i].tm.level && (value & 1))
  281 + s->tm4[i].tm.level = 0;
287 if (!(s->events & 0xff0)) 282 if (!(s->events & 0xff0))
288 - qemu_irq_lower(s->tm4->irq); 283 + qemu_irq_lower(s->tm4->tm.irq);
289 } 284 }
290 break; 285 break;
291 case OWER: /* XXX: Reset on OSMR3 match? */ 286 case OWER: /* XXX: Reset on OSMR3 match? */
@@ -362,13 +357,13 @@ static void pxa2xx_timer_tick(void *opaque) @@ -362,13 +357,13 @@ static void pxa2xx_timer_tick(void *opaque)
362 static void pxa2xx_timer_tick4(void *opaque) 357 static void pxa2xx_timer_tick4(void *opaque)
363 { 358 {
364 struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque; 359 struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
365 - pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info; 360 + pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
366 361
367 - pxa2xx_timer_tick(opaque); 362 + pxa2xx_timer_tick(&t->tm);
368 if (t->control & (1 << 3)) 363 if (t->control & (1 << 3))
369 t->clock = 0; 364 t->clock = 0;
370 if (t->control & (1 << 6)) 365 if (t->control & (1 << 6))
371 - pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->num - 4); 366 + pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
372 } 367 }
373 368
374 static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, 369 static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
@@ -420,14 +415,14 @@ void pxa27x_timer_init(target_phys_addr_t base, @@ -420,14 +415,14 @@ void pxa27x_timer_init(target_phys_addr_t base,
420 s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 * 415 s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
421 sizeof(struct pxa2xx_timer4_s)); 416 sizeof(struct pxa2xx_timer4_s));
422 for (i = 0; i < 8; i ++) { 417 for (i = 0; i < 8; i ++) {
423 - s->tm4[i].value = 0;  
424 - s->tm4[i].irq = irq4;  
425 - s->tm4[i].info = s;  
426 - s->tm4[i].num = i + 4;  
427 - s->tm4[i].level = 0; 418 + s->tm4[i].tm.value = 0;
  419 + s->tm4[i].tm.irq = irq4;
  420 + s->tm4[i].tm.info = s;
  421 + s->tm4[i].tm.num = i + 4;
  422 + s->tm4[i].tm.level = 0;
428 s->tm4[i].freq = 0; 423 s->tm4[i].freq = 0;
429 s->tm4[i].control = 0x0; 424 s->tm4[i].control = 0x0;
430 - s->tm4[i].qtimer = qemu_new_timer(vm_clock, 425 + s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
431 pxa2xx_timer_tick4, &s->tm4[i]); 426 pxa2xx_timer_tick4, &s->tm4[i]);
432 } 427 }
433 } 428 }