Commit 37d269dfc6ccbfc3871d458c426e089e0c4403b6

Authored by aurel32
1 parent 799a8c8d

target-ppc: convert icbi instruction to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc/helper.h
@@ -11,6 +11,7 @@ DEF_HELPER_2(lmw, void, tl, i32) @@ -11,6 +11,7 @@ DEF_HELPER_2(lmw, void, tl, i32)
11 DEF_HELPER_2(stmw, void, tl, i32) 11 DEF_HELPER_2(stmw, void, tl, i32)
12 DEF_HELPER_1(dcbz, void, tl) 12 DEF_HELPER_1(dcbz, void, tl)
13 DEF_HELPER_1(dcbz_970, void, tl) 13 DEF_HELPER_1(dcbz_970, void, tl)
  14 +DEF_HELPER_1(icbi, void, tl)
14 15
15 DEF_HELPER_2(fcmpo, i32, i64, i64) 16 DEF_HELPER_2(fcmpo, i32, i64, i64)
16 DEF_HELPER_2(fcmpu, i32, i64, i64) 17 DEF_HELPER_2(fcmpu, i32, i64, i64)
target-ppc/op_helper.c
@@ -210,6 +210,32 @@ void helper_dcbz_970(target_ulong addr) @@ -210,6 +210,32 @@ void helper_dcbz_970(target_ulong addr)
210 do_dcbz(addr, env->dcache_line_size); 210 do_dcbz(addr, env->dcache_line_size);
211 } 211 }
212 212
  213 +void helper_icbi(target_ulong addr)
  214 +{
  215 + uint32_t tmp;
  216 +
  217 + addr = get_addr(addr & ~(env->dcache_line_size - 1));
  218 + /* Invalidate one cache line :
  219 + * PowerPC specification says this is to be treated like a load
  220 + * (not a fetch) by the MMU. To be sure it will be so,
  221 + * do the load "by hand".
  222 + */
  223 +#ifdef CONFIG_USER_ONLY
  224 + tmp = ldl_raw(addr);
  225 +#else
  226 + switch (env->mmu_idx) {
  227 + default:
  228 + case 0: tmp = ldl_user(addr);
  229 + break;
  230 + case 1: tmp = ldl_kernel(addr);
  231 + break;
  232 + case 2: tmp = ldl_hypv(addr);
  233 + break;
  234 + }
  235 +#endif
  236 + tb_invalidate_page_range(addr, addr + env->icache_line_size);
  237 +}
  238 +
213 /*****************************************************************************/ 239 /*****************************************************************************/
214 /* Fixed point operations helpers */ 240 /* Fixed point operations helpers */
215 #if defined(TARGET_PPC64) 241 #if defined(TARGET_PPC64)
target-ppc/op_helper.h
@@ -23,7 +23,6 @@ @@ -23,7 +23,6 @@
23 /* Memory load/store helpers */ 23 /* Memory load/store helpers */
24 void glue(do_lsw, MEMSUFFIX) (int dst); 24 void glue(do_lsw, MEMSUFFIX) (int dst);
25 void glue(do_stsw, MEMSUFFIX) (int src); 25 void glue(do_stsw, MEMSUFFIX) (int src);
26 -void glue(do_icbi, MEMSUFFIX) (void);  
27 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb); 26 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb);
28 void glue(do_POWER2_lfq, MEMSUFFIX) (void); 27 void glue(do_POWER2_lfq, MEMSUFFIX) (void);
29 void glue(do_POWER2_lfq_le, MEMSUFFIX) (void); 28 void glue(do_POWER2_lfq_le, MEMSUFFIX) (void);
@@ -33,7 +32,6 @@ void glue(do_POWER2_stfq_le, MEMSUFFIX) (void); @@ -33,7 +32,6 @@ void glue(do_POWER2_stfq_le, MEMSUFFIX) (void);
33 #if defined(TARGET_PPC64) 32 #if defined(TARGET_PPC64)
34 void glue(do_lsw_64, MEMSUFFIX) (int dst); 33 void glue(do_lsw_64, MEMSUFFIX) (int dst);
35 void glue(do_stsw_64, MEMSUFFIX) (int src); 34 void glue(do_stsw_64, MEMSUFFIX) (int src);
36 -void glue(do_icbi_64, MEMSUFFIX) (void);  
37 #endif 35 #endif
38 36
39 #else 37 #else
target-ppc/op_helper_mem.h
@@ -92,37 +92,6 @@ void glue(do_stsw_64, MEMSUFFIX) (int src) @@ -92,37 +92,6 @@ void glue(do_stsw_64, MEMSUFFIX) (int src)
92 } 92 }
93 #endif 93 #endif
94 94
95 -/* Instruction cache invalidation helper */  
96 -void glue(do_icbi, MEMSUFFIX) (void)  
97 -{  
98 - uint32_t tmp;  
99 - /* Invalidate one cache line :  
100 - * PowerPC specification says this is to be treated like a load  
101 - * (not a fetch) by the MMU. To be sure it will be so,  
102 - * do the load "by hand".  
103 - */  
104 - T0 &= ~(env->icache_line_size - 1);  
105 - tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);  
106 - tb_invalidate_page_range((uint32_t)T0,  
107 - (uint32_t)(T0 + env->icache_line_size));  
108 -}  
109 -  
110 -#if defined(TARGET_PPC64)  
111 -void glue(do_icbi_64, MEMSUFFIX) (void)  
112 -{  
113 - uint64_t tmp;  
114 - /* Invalidate one cache line :  
115 - * PowerPC specification says this is to be treated like a load  
116 - * (not a fetch) by the MMU. To be sure it will be so,  
117 - * do the load "by hand".  
118 - */  
119 - T0 &= ~(env->icache_line_size - 1);  
120 - tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);  
121 - tb_invalidate_page_range((uint64_t)T0,  
122 - (uint64_t)(T0 + env->icache_line_size));  
123 -}  
124 -#endif  
125 -  
126 /* PowerPC 601 specific instructions (POWER bridge) */ 95 /* PowerPC 601 specific instructions (POWER bridge) */
127 // XXX: to be tested 96 // XXX: to be tested
128 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb) 97 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
target-ppc/op_mem.h
@@ -314,21 +314,6 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void) @@ -314,21 +314,6 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
314 } 314 }
315 #endif 315 #endif
316 316
317 -/* Instruction cache block invalidate */  
318 -void OPPROTO glue(op_icbi, MEMSUFFIX) (void)  
319 -{  
320 - glue(do_icbi, MEMSUFFIX)();  
321 - RETURN();  
322 -}  
323 -  
324 -#if defined(TARGET_PPC64)  
325 -void OPPROTO glue(op_icbi_64, MEMSUFFIX) (void)  
326 -{  
327 - glue(do_icbi_64, MEMSUFFIX)();  
328 - RETURN();  
329 -}  
330 -#endif  
331 -  
332 /* External access */ 317 /* External access */
333 void OPPROTO glue(op_eciwx, MEMSUFFIX) (void) 318 void OPPROTO glue(op_eciwx, MEMSUFFIX) (void)
334 { 319 {
target-ppc/translate.c
@@ -4165,25 +4165,14 @@ GEN_HANDLER2(dcbz_970, &quot;dcbz&quot;, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) @@ -4165,25 +4165,14 @@ GEN_HANDLER2(dcbz_970, &quot;dcbz&quot;, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4165 } 4165 }
4166 4166
4167 /* icbi */ 4167 /* icbi */
4168 -#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()  
4169 -#define gen_op_icbi_le_raw gen_op_icbi_raw  
4170 -#define gen_op_icbi_le_user gen_op_icbi_user  
4171 -#define gen_op_icbi_le_kernel gen_op_icbi_kernel  
4172 -#define gen_op_icbi_le_hypv gen_op_icbi_hypv  
4173 -#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw  
4174 -#define gen_op_icbi_le_64_user gen_op_icbi_64_user  
4175 -#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel  
4176 -#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv  
4177 -static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {  
4178 - GEN_MEM_FUNCS(icbi),  
4179 -};  
4180 -  
4181 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI) 4168 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4182 { 4169 {
  4170 + TCGv t0 = tcg_temp_new();
4183 /* NIP cannot be restored if the memory exception comes from an helper */ 4171 /* NIP cannot be restored if the memory exception comes from an helper */
4184 gen_update_nip(ctx, ctx->nip - 4); 4172 gen_update_nip(ctx, ctx->nip - 4);
4185 - gen_addr_reg_index(cpu_T[0], ctx);  
4186 - op_icbi(); 4173 + gen_addr_reg_index(t0, ctx);
  4174 + gen_helper_icbi(t0);
  4175 + tcg_temp_free(t0);
4187 } 4176 }
4188 4177
4189 /* Optional: */ 4178 /* Optional: */