gwj / at91sam9263 · Commits

Commit 33c263df7f87ca0cd170a6017a668205488ab010

Authored by bellard
1 parent 4f57689a

SVM: added tsc_offset 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4668 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 8 additions and 4 deletions
target-i386/cpu.h
  View file @33c263d
@@ -119,9 +119,9 @@ @@ -119,9 +119,9 @@
119 #define ID_MASK 0x00200000 119 #define ID_MASK 0x00200000
120 120
121 /* hidden flags - used internally by qemu to represent additional cpu 121 /* hidden flags - used internally by qemu to represent additional cpu
122 - states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid  
123 - using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring  
124 - with eflags. */ 122 + states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
  123 + redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
  124 + position to ease oring with eflags. */
125 /* current cpl */ 125 /* current cpl */
126 #define HF_CPL_SHIFT 0 126 #define HF_CPL_SHIFT 0
127 /* true if soft mmu is being used */ 127 /* true if soft mmu is being used */
@@ -543,6 +543,7 @@ typedef struct CPUX86State { @@ -543,6 +543,7 @@ typedef struct CPUX86State {
543 543
544 target_phys_addr_t vm_hsave; 544 target_phys_addr_t vm_hsave;
545 target_phys_addr_t vm_vmcb; 545 target_phys_addr_t vm_vmcb;
  546 + uint64_t tsc_offset;
546 uint64_t intercept; 547 uint64_t intercept;
547 uint16_t intercept_cr_read; 548 uint16_t intercept_cr_read;
548 uint16_t intercept_cr_write; 549 uint16_t intercept_cr_write;
target-i386/op_helper.c
  View file @33c263d
@@ -3005,7 +3005,7 @@ void helper_rdtsc(void) @@ -3005,7 +3005,7 @@ void helper_rdtsc(void)
3005 } 3005 }
3006 helper_svm_check_intercept_param(SVM_EXIT_RDTSC, 0); 3006 helper_svm_check_intercept_param(SVM_EXIT_RDTSC, 0);
3007 3007
3008 - val = cpu_get_tsc(env); 3008 + val = cpu_get_tsc(env) + env->tsc_offset;
3009 EAX = (uint32_t)(val); 3009 EAX = (uint32_t)(val);
3010 EDX = (uint32_t)(val >> 32); 3010 EDX = (uint32_t)(val >> 32);
3011 } 3011 }
@@ -4851,6 +4851,8 @@ void helper_vmrun(int aflag, int next_eip_addend) @@ -4851,6 +4851,8 @@ void helper_vmrun(int aflag, int next_eip_addend)
4851 /* enable intercepts */ 4851 /* enable intercepts */
4852 env->hflags |= HF_SVMI_MASK; 4852 env->hflags |= HF_SVMI_MASK;
4853 4853
  4854 + env->tsc_offset = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.tsc_offset));
  4855 +
4854 env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base)); 4856 env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base));
4855 env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit)); 4857 env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit));
4856 4858
@@ -5226,6 +5228,7 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1) @@ -5226,6 +5228,7 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
5226 env->intercept = 0; 5228 env->intercept = 0;
5227 env->intercept_exceptions = 0; 5229 env->intercept_exceptions = 0;
5228 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; 5230 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
  5231 + env->tsc_offset = 0;
5229 5232
5230 env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base)); 5233 env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base));
5231 env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit)); 5234 env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit));