gwj / at91sam9263 · Commits

Commit 4f57689a8d5db61fb42434ed70142b2b0751da68

Authored by ths
1 parent 29cf4b75

Explicitly free temporaries. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4667 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 130 additions and 160 deletions
target-mips/translate.c
  View file @4f57689
... ... @@ -710,7 +710,7 @@ static inline void gen_save_pc(target_ulong pc)
710 710 tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
711 711 tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
712 712 tcg_temp_free(r_tc_off);
713   - tcg_temp_free(r_tc_off_tl);
  713 + tcg_temp_free(r_tc_off_ptr);
714 714 tcg_temp_free(r_ptr);
715 715 tcg_temp_free(r_tmp);
716 716 }
... ... @@ -729,7 +729,7 @@ static inline void gen_breg_pc(void)
729 729 tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
730 730 tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
731 731 tcg_temp_free(r_tc_off);
732   - tcg_temp_free(r_tc_off_tl);
  732 + tcg_temp_free(r_tc_off_ptr);
733 733 tcg_temp_free(r_ptr);
734 734 tcg_temp_free(r_tmp);
735 735 }
... ... @@ -740,6 +740,7 @@ static inline void gen_save_btarget(target_ulong btarget)
740 740  
741 741 tcg_gen_movi_tl(r_tmp, btarget);
742 742 tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
  743 + tcg_temp_free(r_tmp);
743 744 }
744 745  
745 746 static always_inline void gen_save_breg_target(int reg)
... ... @@ -748,6 +749,7 @@ static always_inline void gen_save_breg_target(int reg)
748 749  
749 750 gen_load_gpr(r_tmp, reg);
750 751 tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
  752 + tcg_temp_free(r_tmp);
751 753 }
752 754  
753 755 static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
... ... @@ -988,7 +990,7 @@ OP_LD_ATOMIC(lld,ld64);
988 990 #define OP_ST_ATOMIC(insn,fname,almask) \
989 991 void inline op_ldst_##insn(DisasContext *ctx) \
990 992 { \
991   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL); \
  993 + TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
992 994 int l1 = gen_new_label(); \
993 995 int l2 = gen_new_label(); \
994 996 int l3 = gen_new_label(); \
... ... @@ -1000,6 +1002,7 @@ void inline op_ldst_##insn(DisasContext *ctx) \
1000 1002 gen_set_label(l1); \
1001 1003 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1002 1004 tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \
  1005 + tcg_temp_free(r_tmp); \
1003 1006 tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \
1004 1007 tcg_gen_movi_tl(cpu_T[0], 1); \
1005 1008 tcg_gen_br(l3); \
... ... @@ -1282,7 +1285,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1282 1285 switch (opc) {
1283 1286 case OPC_ADDI:
1284 1287 {
1285   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  1288 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1286 1289 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1287 1290 int l1 = gen_new_label();
1288 1291  
... ... @@ -1294,8 +1297,10 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1294 1297 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1295 1298 tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
1296 1299 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
  1300 + tcg_temp_free(r_tmp2);
1297 1301 tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
1298 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
  1303 + tcg_temp_free(r_tmp1);
1299 1304 /* operands of same sign, result different sign */
1300 1305 generate_exception(ctx, EXCP_OVERFLOW);
1301 1306 gen_set_label(l1);
... ... @@ -1313,7 +1318,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1313 1318 #if defined(TARGET_MIPS64)
1314 1319 case OPC_DADDI:
1315 1320 {
1316   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  1321 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1317 1322 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1318 1323 int l1 = gen_new_label();
1319 1324  
... ... @@ -1325,8 +1330,10 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1325 1330 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1326 1331 tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
1327 1332 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
  1333 + tcg_temp_free(r_tmp2);
1328 1334 tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
1329 1335 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
  1336 + tcg_temp_free(r_tmp1);
1330 1337 /* operands of same sign, result different sign */
1331 1338 generate_exception(ctx, EXCP_OVERFLOW);
1332 1339 gen_set_label(l1);
... ... @@ -1438,6 +1445,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1438 1445 tcg_gen_shl_tl(r_tmp1, cpu_T[0], r_tmp1);
1439 1446 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
1440 1447 tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
  1448 + tcg_temp_free(r_tmp1);
1441 1449 }
1442 1450 opn = "drotr";
1443 1451 } else {
... ... @@ -1478,6 +1486,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1478 1486 tcg_gen_shl_tl(r_tmp1, cpu_T[0], r_tmp1);
1479 1487 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], r_tmp2);
1480 1488 tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
  1489 + tcg_temp_free(r_tmp1);
  1490 + tcg_temp_free(r_tmp2);
1481 1491 opn = "drotr32";
1482 1492 } else {
1483 1493 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm + 32);
... ... @@ -1524,7 +1534,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1524 1534 switch (opc) {
1525 1535 case OPC_ADD:
1526 1536 {
1527   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  1537 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1528 1538 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1529 1539 int l1 = gen_new_label();
1530 1540  
... ... @@ -1537,8 +1547,10 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1537 1547 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1538 1548 tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
1539 1549 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
  1550 + tcg_temp_free(r_tmp2);
1540 1551 tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
1541 1552 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
  1553 + tcg_temp_free(r_tmp1);
1542 1554 /* operands of same sign, result different sign */
1543 1555 generate_exception(ctx, EXCP_OVERFLOW);
1544 1556 gen_set_label(l1);
... ... @@ -1556,7 +1568,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1556 1568 break;
1557 1569 case OPC_SUB:
1558 1570 {
1559   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  1571 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1560 1572 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1561 1573 int l1 = gen_new_label();
1562 1574  
... ... @@ -1568,8 +1580,10 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1568 1580 tcg_gen_xor_tl(r_tmp2, r_tmp1, cpu_T[1]);
1569 1581 tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
1570 1582 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
  1583 + tcg_temp_free(r_tmp2);
1571 1584 tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
1572 1585 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
  1586 + tcg_temp_free(r_tmp1);
1573 1587 /* operands of different sign, first operand and result different sign */
1574 1588 generate_exception(ctx, EXCP_OVERFLOW);
1575 1589 gen_set_label(l1);
... ... @@ -1588,7 +1602,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1588 1602 #if defined(TARGET_MIPS64)
1589 1603 case OPC_DADD:
1590 1604 {
1591   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  1605 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1592 1606 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1593 1607 int l1 = gen_new_label();
1594 1608  
... ... @@ -1600,8 +1614,10 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1600 1614 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1601 1615 tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
1602 1616 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
  1617 + tcg_temp_free(r_tmp2);
1603 1618 tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
1604 1619 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
  1620 + tcg_temp_free(r_tmp1);
1605 1621 /* operands of same sign, result different sign */
1606 1622 generate_exception(ctx, EXCP_OVERFLOW);
1607 1623 gen_set_label(l1);
... ... @@ -1614,7 +1630,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1614 1630 break;
1615 1631 case OPC_DSUB:
1616 1632 {
1617   - TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
  1633 + TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1618 1634 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1619 1635 int l1 = gen_new_label();
1620 1636  
... ... @@ -1625,8 +1641,10 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1625 1641 tcg_gen_xor_tl(r_tmp2, r_tmp1, cpu_T[1]);
1626 1642 tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
1627 1643 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
  1644 + tcg_temp_free(r_tmp2);
1628 1645 tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
1629 1646 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
  1647 + tcg_temp_free(r_tmp1);
1630 1648 /* operands of different sign, first operand and result different sign */
1631 1649 generate_exception(ctx, EXCP_OVERFLOW);
1632 1650 gen_set_label(l1);
... ... @@ -1792,6 +1810,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1792 1810 tcg_gen_shl_tl(r_tmp1, cpu_T[1], r_tmp1);
1793 1811 tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1794 1812 tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
  1813 + tcg_temp_free(r_tmp1);
1795 1814 tcg_gen_br(l2);
1796 1815 }
1797 1816 gen_set_label(l1);
... ... @@ -1886,6 +1905,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1886 1905 tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
1887 1906 tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
1888 1907 tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
  1908 + tcg_temp_free(r_tmp1);
  1909 + tcg_temp_free(r_tmp2);
  1910 + tcg_temp_free(r_tmp3);
1889 1911 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
1890 1912 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
1891 1913 gen_store_LO(cpu_T[0], 0);
... ... @@ -1956,6 +1978,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1956 1978 tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
1957 1979 gen_store_LO(r_tmp1, 0);
1958 1980 gen_store_HI(r_tmp2, 0);
  1981 + tcg_temp_free(r_tmp1);
  1982 + tcg_temp_free(r_tmp2);
1959 1983 }
1960 1984 }
1961 1985 gen_set_label(l1);
... ... @@ -1973,6 +1997,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1973 1997  
1974 1998 tcg_gen_divu_i64(r_tmp1, cpu_T[0], cpu_T[1]);
1975 1999 tcg_gen_remu_i64(r_tmp2, cpu_T[0], cpu_T[1]);
  2000 + tcg_temp_free(r_tmp1);
  2001 + tcg_temp_free(r_tmp2);
1976 2002 gen_store_LO(r_tmp1, 0);
1977 2003 gen_store_HI(r_tmp2, 0);
1978 2004 }
... ... @@ -2539,11 +2565,27 @@ fail:
2539 2565 }
2540 2566  
2541 2567 /* CP0 (MMU and control) */
  2568 +static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
  2569 +{
  2570 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
  2571 +
  2572 + tcg_gen_ld_i32(r_tmp, cpu_env, off);
  2573 + tcg_gen_ext_i32_tl(t, r_tmp);
  2574 + tcg_temp_free(r_tmp);
  2575 +}
  2576 +
  2577 +static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
  2578 +{
  2579 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I64);
  2580 +
  2581 + tcg_gen_ld_i64(r_tmp, cpu_env, off);
  2582 + tcg_gen_trunc_i64_tl(t, r_tmp);
  2583 + tcg_temp_free(r_tmp);
  2584 +}
  2585 +
2542 2586 static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2543 2587 {
2544 2588 const char *rn = "invalid";
2545   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
2546   - TCGv r_tmp64 = tcg_temp_new(TCG_TYPE_I64);
2547 2589  
2548 2590 if (sel != 0)
2549 2591 check_insn(env, ctx, ISA_MIPS32);
... ... @@ -2552,8 +2594,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2552 2594 case 0:
2553 2595 switch (sel) {
2554 2596 case 0:
2555   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
2556   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2597 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Index));
2557 2598 rn = "Index";
2558 2599 break;
2559 2600 case 1:
... ... @@ -2583,44 +2624,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2583 2624 break;
2584 2625 case 1:
2585 2626 check_insn(env, ctx, ASE_MT);
2586   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
2587   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2627 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEControl));
2588 2628 rn = "VPEControl";
2589 2629 break;
2590 2630 case 2:
2591 2631 check_insn(env, ctx, ASE_MT);
2592   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
2593   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2632 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf0));
2594 2633 rn = "VPEConf0";
2595 2634 break;
2596 2635 case 3:
2597 2636 check_insn(env, ctx, ASE_MT);
2598   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
2599   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2637 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf1));
2600 2638 rn = "VPEConf1";
2601 2639 break;
2602 2640 case 4:
2603 2641 check_insn(env, ctx, ASE_MT);
2604   - tcg_gen_ld_i64(r_tmp64, cpu_env, offsetof(CPUState, CP0_YQMask));
2605   - tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
  2642 + gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_YQMask));
2606 2643 rn = "YQMask";
2607 2644 break;
2608 2645 case 5:
2609 2646 check_insn(env, ctx, ASE_MT);
2610   - tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPESchedule));
2611   - tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
  2647 + gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule));
2612 2648 rn = "VPESchedule";
2613 2649 break;
2614 2650 case 6:
2615 2651 check_insn(env, ctx, ASE_MT);
2616   - tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
2617   - tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
  2652 + gen_mfc0_load64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack));
2618 2653 rn = "VPEScheFBack";
2619 2654 break;
2620 2655 case 7:
2621 2656 check_insn(env, ctx, ASE_MT);
2622   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
2623   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2657 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEOpt));
2624 2658 rn = "VPEOpt";
2625 2659 break;
2626 2660 default:
... ... @@ -2702,14 +2736,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2702 2736 case 5:
2703 2737 switch (sel) {
2704 2738 case 0:
2705   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
2706   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2739 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageMask));
2707 2740 rn = "PageMask";
2708 2741 break;
2709 2742 case 1:
2710 2743 check_insn(env, ctx, ISA_MIPS32R2);
2711   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
2712   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2744 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageGrain));
2713 2745 rn = "PageGrain";
2714 2746 break;
2715 2747 default:
... ... @@ -2719,38 +2751,32 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2719 2751 case 6:
2720 2752 switch (sel) {
2721 2753 case 0:
2722   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
2723   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2754 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Wired));
2724 2755 rn = "Wired";
2725 2756 break;
2726 2757 case 1:
2727 2758 check_insn(env, ctx, ISA_MIPS32R2);
2728   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
2729   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2759 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf0));
2730 2760 rn = "SRSConf0";
2731 2761 break;
2732 2762 case 2:
2733 2763 check_insn(env, ctx, ISA_MIPS32R2);
2734   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
2735   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2764 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf1));
2736 2765 rn = "SRSConf1";
2737 2766 break;
2738 2767 case 3:
2739 2768 check_insn(env, ctx, ISA_MIPS32R2);
2740   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
2741   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2769 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf2));
2742 2770 rn = "SRSConf2";
2743 2771 break;
2744 2772 case 4:
2745 2773 check_insn(env, ctx, ISA_MIPS32R2);
2746   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
2747   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2774 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf3));
2748 2775 rn = "SRSConf3";
2749 2776 break;
2750 2777 case 5:
2751 2778 check_insn(env, ctx, ISA_MIPS32R2);
2752   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
2753   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2779 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf4));
2754 2780 rn = "SRSConf4";
2755 2781 break;
2756 2782 default:
... ... @@ -2761,8 +2787,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2761 2787 switch (sel) {
2762 2788 case 0:
2763 2789 check_insn(env, ctx, ISA_MIPS32R2);
2764   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
2765   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2790 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_HWREna));
2766 2791 rn = "HWREna";
2767 2792 break;
2768 2793 default:
... ... @@ -2805,8 +2830,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2805 2830 case 11:
2806 2831 switch (sel) {
2807 2832 case 0:
2808   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
2809   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2833 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Compare));
2810 2834 rn = "Compare";
2811 2835 break;
2812 2836 /* 6,7 are implementation dependent */
... ... @@ -2817,26 +2841,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2817 2841 case 12:
2818 2842 switch (sel) {
2819 2843 case 0:
2820   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
2821   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2844 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Status));
2822 2845 rn = "Status";
2823 2846 break;
2824 2847 case 1:
2825 2848 check_insn(env, ctx, ISA_MIPS32R2);
2826   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
2827   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2849 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_IntCtl));
2828 2850 rn = "IntCtl";
2829 2851 break;
2830 2852 case 2:
2831 2853 check_insn(env, ctx, ISA_MIPS32R2);
2832   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
2833   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2854 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSCtl));
2834 2855 rn = "SRSCtl";
2835 2856 break;
2836 2857 case 3:
2837 2858 check_insn(env, ctx, ISA_MIPS32R2);
2838   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
2839   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2859 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
2840 2860 rn = "SRSMap";
2841 2861 break;
2842 2862 default:
... ... @@ -2846,8 +2866,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2846 2866 case 13:
2847 2867 switch (sel) {
2848 2868 case 0:
2849   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
2850   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2869 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Cause));
2851 2870 rn = "Cause";
2852 2871 break;
2853 2872 default:
... ... @@ -2868,14 +2887,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2868 2887 case 15:
2869 2888 switch (sel) {
2870 2889 case 0:
2871   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
2872   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2890 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PRid));
2873 2891 rn = "PRid";
2874 2892 break;
2875 2893 case 1:
2876 2894 check_insn(env, ctx, ISA_MIPS32R2);
2877   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
2878   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2895 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_EBase));
2879 2896 rn = "EBase";
2880 2897 break;
2881 2898 default:
... ... @@ -2885,35 +2902,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2885 2902 case 16:
2886 2903 switch (sel) {
2887 2904 case 0:
2888   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
2889   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2905 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config0));
2890 2906 rn = "Config";
2891 2907 break;
2892 2908 case 1:
2893   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
2894   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2909 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config1));
2895 2910 rn = "Config1";
2896 2911 break;
2897 2912 case 2:
2898   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
2899   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2913 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config2));
2900 2914 rn = "Config2";
2901 2915 break;
2902 2916 case 3:
2903   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
2904   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2917 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config3));
2905 2918 rn = "Config3";
2906 2919 break;
2907 2920 /* 4,5 are reserved */
2908 2921 /* 6,7 are implementation dependent */
2909 2922 case 6:
2910   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
2911   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2923 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config6));
2912 2924 rn = "Config6";
2913 2925 break;
2914 2926 case 7:
2915   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
2916   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2927 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config7));
2917 2928 rn = "Config7";
2918 2929 break;
2919 2930 default:
... ... @@ -2968,8 +2979,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2968 2979 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2969 2980 switch (sel) {
2970 2981 case 0:
2971   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
2972   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  2982 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Framemask));
2973 2983 rn = "Framemask";
2974 2984 break;
2975 2985 default:
... ... @@ -3021,8 +3031,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3021 3031 case 25:
3022 3032 switch (sel) {
3023 3033 case 0:
3024   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
3025   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3034 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Performance0));
3026 3035 rn = "Performance0";
3027 3036 break;
3028 3037 case 1:
... ... @@ -3076,16 +3085,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3076 3085 case 2:
3077 3086 case 4:
3078 3087 case 6:
3079   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
3080   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3088 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagLo));
3081 3089 rn = "TagLo";
3082 3090 break;
3083 3091 case 1:
3084 3092 case 3:
3085 3093 case 5:
3086 3094 case 7:
3087   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
3088   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3095 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataLo));
3089 3096 rn = "DataLo";
3090 3097 break;
3091 3098 default:
... ... @@ -3098,16 +3105,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3098 3105 case 2:
3099 3106 case 4:
3100 3107 case 6:
3101   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
3102   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3108 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagHi));
3103 3109 rn = "TagHi";
3104 3110 break;
3105 3111 case 1:
3106 3112 case 3:
3107 3113 case 5:
3108 3114 case 7:
3109   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
3110   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3115 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataHi));
3111 3116 rn = "DataHi";
3112 3117 break;
3113 3118 default:
... ... @@ -3129,8 +3134,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3129 3134 switch (sel) {
3130 3135 case 0:
3131 3136 /* EJTAG support */
3132   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
3133   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3137 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
3134 3138 rn = "DESAVE";
3135 3139 break;
3136 3140 default:
... ... @@ -3761,7 +3765,6 @@ die:
3761 3765 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3762 3766 {
3763 3767 const char *rn = "invalid";
3764   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
3765 3768  
3766 3769 if (sel != 0)
3767 3770 check_insn(env, ctx, ISA_MIPS64);
... ... @@ -3770,8 +3773,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3770 3773 case 0:
3771 3774 switch (sel) {
3772 3775 case 0:
3773   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
3774   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3776 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Index));
3775 3777 rn = "Index";
3776 3778 break;
3777 3779 case 1:
... ... @@ -3801,20 +3803,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3801 3803 break;
3802 3804 case 1:
3803 3805 check_insn(env, ctx, ASE_MT);
3804   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
3805   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3806 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEControl));
3806 3807 rn = "VPEControl";
3807 3808 break;
3808 3809 case 2:
3809 3810 check_insn(env, ctx, ASE_MT);
3810   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
3811   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3811 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf0));
3812 3812 rn = "VPEConf0";
3813 3813 break;
3814 3814 case 3:
3815 3815 check_insn(env, ctx, ASE_MT);
3816   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
3817   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3816 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEConf1));
3818 3817 rn = "VPEConf1";
3819 3818 break;
3820 3819 case 4:
... ... @@ -3834,8 +3833,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3834 3833 break;
3835 3834 case 7:
3836 3835 check_insn(env, ctx, ASE_MT);
3837   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
3838   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3836 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_VPEOpt));
3839 3837 rn = "VPEOpt";
3840 3838 break;
3841 3839 default:
... ... @@ -3914,14 +3912,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3914 3912 case 5:
3915 3913 switch (sel) {
3916 3914 case 0:
3917   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
3918   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3915 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageMask));
3919 3916 rn = "PageMask";
3920 3917 break;
3921 3918 case 1:
3922 3919 check_insn(env, ctx, ISA_MIPS32R2);
3923   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
3924   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3920 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PageGrain));
3925 3921 rn = "PageGrain";
3926 3922 break;
3927 3923 default:
... ... @@ -3931,38 +3927,32 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3931 3927 case 6:
3932 3928 switch (sel) {
3933 3929 case 0:
3934   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
3935   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3930 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Wired));
3936 3931 rn = "Wired";
3937 3932 break;
3938 3933 case 1:
3939 3934 check_insn(env, ctx, ISA_MIPS32R2);
3940   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
3941   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3935 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf0));
3942 3936 rn = "SRSConf0";
3943 3937 break;
3944 3938 case 2:
3945 3939 check_insn(env, ctx, ISA_MIPS32R2);
3946   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
3947   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3940 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf1));
3948 3941 rn = "SRSConf1";
3949 3942 break;
3950 3943 case 3:
3951 3944 check_insn(env, ctx, ISA_MIPS32R2);
3952   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
3953   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3945 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf2));
3954 3946 rn = "SRSConf2";
3955 3947 break;
3956 3948 case 4:
3957 3949 check_insn(env, ctx, ISA_MIPS32R2);
3958   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
3959   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3950 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf3));
3960 3951 rn = "SRSConf3";
3961 3952 break;
3962 3953 case 5:
3963 3954 check_insn(env, ctx, ISA_MIPS32R2);
3964   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
3965   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3955 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSConf4));
3966 3956 rn = "SRSConf4";
3967 3957 break;
3968 3958 default:
... ... @@ -3973,8 +3963,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3973 3963 switch (sel) {
3974 3964 case 0:
3975 3965 check_insn(env, ctx, ISA_MIPS32R2);
3976   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
3977   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  3966 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_HWREna));
3978 3967 rn = "HWREna";
3979 3968 break;
3980 3969 default:
... ... @@ -4015,8 +4004,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4015 4004 case 11:
4016 4005 switch (sel) {
4017 4006 case 0:
4018   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
4019   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4007 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Compare));
4020 4008 rn = "Compare";
4021 4009 break;
4022 4010 /* 6,7 are implementation dependent */
... ... @@ -4027,26 +4015,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4027 4015 case 12:
4028 4016 switch (sel) {
4029 4017 case 0:
4030   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
4031   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4018 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Status));
4032 4019 rn = "Status";
4033 4020 break;
4034 4021 case 1:
4035 4022 check_insn(env, ctx, ISA_MIPS32R2);
4036   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
4037   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4023 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_IntCtl));
4038 4024 rn = "IntCtl";
4039 4025 break;
4040 4026 case 2:
4041 4027 check_insn(env, ctx, ISA_MIPS32R2);
4042   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
4043   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4028 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSCtl));
4044 4029 rn = "SRSCtl";
4045 4030 break;
4046 4031 case 3:
4047 4032 check_insn(env, ctx, ISA_MIPS32R2);
4048   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
4049   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4033 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
4050 4034 rn = "SRSMap";
4051 4035 break;
4052 4036 default:
... ... @@ -4056,8 +4040,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4056 4040 case 13:
4057 4041 switch (sel) {
4058 4042 case 0:
4059   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
4060   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4043 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Cause));
4061 4044 rn = "Cause";
4062 4045 break;
4063 4046 default:
... ... @@ -4077,14 +4060,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4077 4060 case 15:
4078 4061 switch (sel) {
4079 4062 case 0:
4080   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
4081   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4063 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_PRid));
4082 4064 rn = "PRid";
4083 4065 break;
4084 4066 case 1:
4085 4067 check_insn(env, ctx, ISA_MIPS32R2);
4086   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
4087   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4068 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_EBase));
4088 4069 rn = "EBase";
4089 4070 break;
4090 4071 default:
... ... @@ -4094,34 +4075,28 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4094 4075 case 16:
4095 4076 switch (sel) {
4096 4077 case 0:
4097   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
4098   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4078 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config0));
4099 4079 rn = "Config";
4100 4080 break;
4101 4081 case 1:
4102   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
4103   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4082 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config1));
4104 4083 rn = "Config1";
4105 4084 break;
4106 4085 case 2:
4107   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
4108   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4086 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config2));
4109 4087 rn = "Config2";
4110 4088 break;
4111 4089 case 3:
4112   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
4113   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4090 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config3));
4114 4091 rn = "Config3";
4115 4092 break;
4116 4093 /* 6,7 are implementation dependent */
4117 4094 case 6:
4118   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
4119   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4095 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config6));
4120 4096 rn = "Config6";
4121 4097 break;
4122 4098 case 7:
4123   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
4124   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4099 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Config7));
4125 4100 rn = "Config7";
4126 4101 break;
4127 4102 default:
... ... @@ -4173,8 +4148,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4173 4148 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4174 4149 switch (sel) {
4175 4150 case 0:
4176   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
4177   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4151 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Framemask));
4178 4152 rn = "Framemask";
4179 4153 break;
4180 4154 default:
... ... @@ -4225,8 +4199,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4225 4199 case 25:
4226 4200 switch (sel) {
4227 4201 case 0:
4228   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
4229   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4202 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_Performance0));
4230 4203 rn = "Performance0";
4231 4204 break;
4232 4205 case 1:
... ... @@ -4280,16 +4253,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4280 4253 case 2:
4281 4254 case 4:
4282 4255 case 6:
4283   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
4284   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4256 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagLo));
4285 4257 rn = "TagLo";
4286 4258 break;
4287 4259 case 1:
4288 4260 case 3:
4289 4261 case 5:
4290 4262 case 7:
4291   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
4292   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4263 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataLo));
4293 4264 rn = "DataLo";
4294 4265 break;
4295 4266 default:
... ... @@ -4302,16 +4273,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4302 4273 case 2:
4303 4274 case 4:
4304 4275 case 6:
4305   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
4306   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4276 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_TagHi));
4307 4277 rn = "TagHi";
4308 4278 break;
4309 4279 case 1:
4310 4280 case 3:
4311 4281 case 5:
4312 4282 case 7:
4313   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
4314   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4283 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DataHi));
4315 4284 rn = "DataHi";
4316 4285 break;
4317 4286 default:
... ... @@ -4332,8 +4301,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4332 4301 switch (sel) {
4333 4302 case 0:
4334 4303 /* EJTAG support */
4335   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
4336   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
  4304 + gen_mfc0_load32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
4337 4305 rn = "DESAVE";
4338 4306 break;
4339 4307 default:
... ... @@ -6629,12 +6597,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6629 6597  
6630 6598 /* Handle blikely not taken case */
6631 6599 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
6632   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  6600 + TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL);
6633 6601 int l1 = gen_new_label();
6634 6602  
6635 6603 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
6636 6604 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
6637 6605 tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
  6606 + tcg_temp_free(r_tmp);
6638 6607 gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
6639 6608 gen_goto_tb(ctx, 1, ctx->pc + 4);
6640 6609 gen_set_label(l1);
... ... @@ -7188,11 +7157,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7188 7157 /* Conditional branch */
7189 7158 MIPS_DEBUG("conditional branch");
7190 7159 {
7191   - TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
  7160 + TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL);
7192 7161 int l1 = gen_new_label();
7193 7162  
7194 7163 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
7195 7164 tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
  7165 + tcg_temp_free(r_tmp);
7196 7166 gen_goto_tb(ctx, 1, ctx->pc + 4);
7197 7167 gen_set_label(l1);
7198 7168 gen_goto_tb(ctx, 0, ctx->btarget);
... ...