gwj / at91sam9263 · Commits

Commit 2e29bd04786003561303dcad940b38afe790fb9b

Authored by Blue Swirl
1 parent 426f17bb

PPC: convert Uni-north to qdev: also fixes Mac99 machine crash 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 1 changed file with 166 additions and 55 deletions
hw/unin_pci.c
  View file @2e29bd0
... ... @@ -38,7 +38,10 @@
38 38 typedef target_phys_addr_t pci_addr_t;
39 39 #include "pci_host.h"
40 40  
41   -typedef PCIHostState UNINState;
  41 +typedef struct UNINState {
  42 + SysBusDevice busdev;
  43 + PCIHostState host_state;
  44 +} UNINState;
42 45  
43 46 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
44 47 uint32_t val)
... ... @@ -50,7 +53,7 @@ static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
50 53 val = bswap32(val);
51 54 #endif
52 55  
53   - s->config_reg = val;
  56 + s->host_state.config_reg = val;
54 57 }
55 58  
56 59 static uint32_t pci_unin_main_config_readl (void *opaque,
... ... @@ -59,7 +62,7 @@ static uint32_t pci_unin_main_config_readl (void *opaque,
59 62 UNINState *s = opaque;
60 63 uint32_t val;
61 64  
62   - val = s->config_reg;
  65 + val = s->host_state.config_reg;
63 66 #ifdef TARGET_WORDS_BIGENDIAN
64 67 val = bswap32(val);
65 68 #endif
... ... @@ -97,7 +100,7 @@ static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
97 100 {
98 101 UNINState *s = opaque;
99 102  
100   - s->config_reg = val;
  103 + s->host_state.config_reg = val;
101 104 }
102 105  
103 106 static uint32_t pci_unin_config_readl (void *opaque,
... ... @@ -105,7 +108,7 @@ static uint32_t pci_unin_config_readl (void *opaque,
105 108 {
106 109 UNINState *s = opaque;
107 110  
108   - return s->config_reg;
  111 + return s->host_state.config_reg;
109 112 }
110 113  
111 114 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
... ... @@ -120,19 +123,17 @@ static CPUReadMemoryFunc *pci_unin_config_read[] = {
120 123 &pci_unin_config_readl,
121 124 };
122 125  
123   -#if 0
124 126 static CPUWriteMemoryFunc *pci_unin_write[] = {
125   - &pci_host_pci_writeb,
126   - &pci_host_pci_writew,
127   - &pci_host_pci_writel,
  127 + &pci_host_data_writeb,
  128 + &pci_host_data_writew,
  129 + &pci_host_data_writel,
128 130 };
129 131  
130 132 static CPUReadMemoryFunc *pci_unin_read[] = {
131   - &pci_host_pci_readb,
132   - &pci_host_pci_readw,
133   - &pci_host_pci_readl,
  133 + &pci_host_data_readb,
  134 + &pci_host_data_readw,
  135 + &pci_host_data_readl,
134 136 };
135   -#endif
136 137  
137 138 /* Don't know if this matches real hardware, but it agrees with OHW. */
138 139 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
... ... @@ -166,27 +167,118 @@ static void pci_unin_reset(void *opaque)
166 167 {
167 168 }
168 169  
169   -PCIBus *pci_pmac_init(qemu_irq *pic)
  170 +static void pci_unin_main_init_device(SysBusDevice *dev)
170 171 {
171 172 UNINState *s;
172   - PCIDevice *d;
173 173 int pci_mem_config, pci_mem_data;
174 174  
175 175 /* Use values found on a real PowerMac */
176 176 /* Uninorth main bus */
177   - s = qemu_mallocz(sizeof(UNINState));
178   - s->bus = pci_register_bus(NULL, "pci",
179   - pci_unin_set_irq, pci_unin_map_irq,
180   - pic, 11 << 3, 4);
  177 + s = FROM_SYSBUS(UNINState, dev);
181 178  
182 179 pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read,
183 180 pci_unin_main_config_write, s);
184 181 pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
185   - pci_unin_main_write, s);
186   - cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
187   - cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
188   - d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
189   - 11 << 3, NULL, NULL);
  182 + pci_unin_main_write, &s->host_state);
  183 +
  184 + sysbus_init_mmio(dev, 0x1000, pci_mem_config);
  185 + sysbus_init_mmio(dev, 0x1000, pci_mem_data);
  186 +
  187 + register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
  188 + qemu_register_reset(pci_unin_reset, &s->host_state);
  189 + pci_unin_reset(&s->host_state);
  190 +}
  191 +
  192 +static void pci_dec_21154_init_device(SysBusDevice *dev)
  193 +{
  194 + UNINState *s;
  195 + int pci_mem_config, pci_mem_data;
  196 +
  197 + /* Uninorth bridge */
  198 + s = FROM_SYSBUS(UNINState, dev);
  199 +
  200 + // XXX: s = &pci_bridge[2];
  201 + pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
  202 + pci_unin_config_write, s);
  203 + pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
  204 + pci_unin_main_write, &s->host_state);
  205 + sysbus_init_mmio(dev, 0x1000, pci_mem_config);
  206 + sysbus_init_mmio(dev, 0x1000, pci_mem_data);
  207 +}
  208 +
  209 +static void pci_unin_agp_init_device(SysBusDevice *dev)
  210 +{
  211 + UNINState *s;
  212 + int pci_mem_config, pci_mem_data;
  213 +
  214 + /* Uninorth AGP bus */
  215 + s = FROM_SYSBUS(UNINState, dev);
  216 +
  217 + pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
  218 + pci_unin_config_write, s);
  219 + pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
  220 + pci_unin_main_write, &s->host_state);
  221 + sysbus_init_mmio(dev, 0x1000, pci_mem_config);
  222 + sysbus_init_mmio(dev, 0x1000, pci_mem_data);
  223 +}
  224 +
  225 +static void pci_unin_internal_init_device(SysBusDevice *dev)
  226 +{
  227 + UNINState *s;
  228 + int pci_mem_config, pci_mem_data;
  229 +
  230 + /* Uninorth internal bus */
  231 + s = FROM_SYSBUS(UNINState, dev);
  232 +
  233 + pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
  234 + pci_unin_config_write, s);
  235 + pci_mem_data = cpu_register_io_memory(pci_unin_read,
  236 + pci_unin_write, s);
  237 + sysbus_init_mmio(dev, 0x1000, pci_mem_config);
  238 + sysbus_init_mmio(dev, 0x1000, pci_mem_data);
  239 +}
  240 +
  241 +PCIBus *pci_pmac_init(qemu_irq *pic)
  242 +{
  243 + DeviceState *dev;
  244 + SysBusDevice *s;
  245 + UNINState *d;
  246 +
  247 + /* Use values found on a real PowerMac */
  248 + /* Uninorth main bus */
  249 + dev = qdev_create(NULL, "Uni-north main");
  250 + qdev_init(dev);
  251 + s = sysbus_from_qdev(dev);
  252 + d = FROM_SYSBUS(UNINState, s);
  253 + d->host_state.bus = pci_register_bus(NULL, "pci",
  254 + pci_unin_set_irq, pci_unin_map_irq,
  255 + pic, 11 << 3, 4);
  256 +
  257 + pci_create_simple(d->host_state.bus, 11 << 3, "Uni-north main");
  258 +
  259 + sysbus_mmio_map(s, 0, 0xf2800000);
  260 + sysbus_mmio_map(s, 1, 0xf2c00000);
  261 +
  262 + /* DEC 21154 bridge */
  263 +#if 0
  264 + /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
  265 + pci_create_simple(d->host_state.bus, 12 << 3, "DEC 21154");
  266 +#endif
  267 +
  268 + /* Uninorth AGP bus */
  269 + pci_create_simple(d->host_state.bus, 13 << 3, "Uni-north AGP");
  270 +
  271 + /* Uninorth internal bus */
  272 +#if 0
  273 + /* XXX: not needed for now */
  274 + pci_create_simple(d->host_state.bus, 14 << 3, "Uni-north internal");
  275 +#endif
  276 +
  277 + return d->host_state.bus;
  278 +}
  279 +
  280 +static void unin_main_pci_host_init(PCIDevice *d)
  281 +{
190 282 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
191 283 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
192 284 d->config[0x08] = 0x00; // revision
... ... @@ -195,11 +287,11 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
195 287 d->config[0x0D] = 0x10; // latency_timer
196 288 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
197 289 d->config[0x34] = 0x00; // capabilities_pointer
  290 +}
198 291  
199   -#if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
  292 +static void dec_21154_pci_host_init(PCIDevice *d)
  293 +{
200 294 /* pci-to-pci bridge */
201   - d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
202   - NULL, NULL);
203 295 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
204 296 pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
205 297 d->config[0x08] = 0x05; // revision
... ... @@ -223,18 +315,10 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
223 315 d->config[0x26] = 0xF1; // prefectchable_memory_limit
224 316 d->config[0x27] = 0x7F;
225 317 // d->config[0x34] = 0xdc // capabilities_pointer
226   -#endif
227   -
228   - /* Uninorth AGP bus */
229   - pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
230   - pci_unin_config_write, s);
231   - pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
232   - pci_unin_main_write, s);
233   - cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
234   - cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
  318 +}
235 319  
236   - d = pci_register_device(s->bus, "Uni-north AGP", sizeof(PCIDevice),
237   - 11 << 3, NULL, NULL);
  320 +static void unin_agp_pci_host_init(PCIDevice *d)
  321 +{
238 322 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
239 323 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
240 324 d->config[0x08] = 0x00; // revision
... ... @@ -243,19 +327,10 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
243 327 d->config[0x0D] = 0x10; // latency_timer
244 328 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
245 329 // d->config[0x34] = 0x80; // capabilities_pointer
  330 +}
246 331  
247   -#if 0 // XXX: not needed for now
248   - /* Uninorth internal bus */
249   - s = &pci_bridge[2];
250   - pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
251   - pci_unin_config_write, s);
252   - pci_mem_data = cpu_register_io_memory(pci_unin_read,
253   - pci_unin_write, s);
254   - cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
255   - cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
256   -
257   - d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
258   - 3, 11 << 3, NULL, NULL);
  332 +static void unin_internal_pci_host_init(PCIDevice *d)
  333 +{
259 334 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
260 335 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
261 336 d->config[0x08] = 0x00; // revision
... ... @@ -264,10 +339,46 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
264 339 d->config[0x0D] = 0x10; // latency_timer
265 340 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
266 341 d->config[0x34] = 0x00; // capabilities_pointer
267   -#endif
268   - register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
269   - qemu_register_reset(pci_unin_reset, d);
270   - pci_unin_reset(d);
  342 +}
  343 +
  344 +static PCIDeviceInfo unin_main_pci_host_info = {
  345 + .qdev.name = "Uni-north main",
  346 + .qdev.size = sizeof(PCIDevice),
  347 + .init = unin_main_pci_host_init,
  348 +};
  349 +
  350 +static PCIDeviceInfo dec_21154_pci_host_info = {
  351 + .qdev.name = "DEC 21154",
  352 + .qdev.size = sizeof(PCIDevice),
  353 + .init = dec_21154_pci_host_init,
  354 +};
271 355  
272   - return s->bus;
  356 +static PCIDeviceInfo unin_agp_pci_host_info = {
  357 + .qdev.name = "Uni-north AGP",
  358 + .qdev.size = sizeof(PCIDevice),
  359 + .init = unin_agp_pci_host_init,
  360 +};
  361 +
  362 +static PCIDeviceInfo unin_internal_pci_host_info = {
  363 + .qdev.name = "Uni-north internal",
  364 + .qdev.size = sizeof(PCIDevice),
  365 + .init = unin_internal_pci_host_init,
  366 +};
  367 +
  368 +static void unin_register_devices(void)
  369 +{
  370 + sysbus_register_dev("Uni-north main", sizeof(UNINState),
  371 + pci_unin_main_init_device);
  372 + pci_qdev_register(&unin_main_pci_host_info);
  373 + sysbus_register_dev("DEC 21154", sizeof(UNINState),
  374 + pci_dec_21154_init_device);
  375 + pci_qdev_register(&dec_21154_pci_host_info);
  376 + sysbus_register_dev("Uni-north AGP", sizeof(UNINState),
  377 + pci_unin_agp_init_device);
  378 + pci_qdev_register(&unin_agp_pci_host_info);
  379 + sysbus_register_dev("Uni-north internal", sizeof(UNINState),
  380 + pci_unin_internal_init_device);
  381 + pci_qdev_register(&unin_internal_pci_host_info);
273 382 }
  383 +
  384 +device_init(unin_register_devices)
... ...