gwj / at91sam9263 · Commits

Commit 426f17bb0b8dc30d29c27eed0a01cb2c113e9066

Authored by Blue Swirl
1 parent c05ac895

PPC: convert Grackle to qdev 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 1 changed file with 86 additions and 20 deletions
hw/grackle_pci.c
  View file @426f17b
... ... @@ -23,7 +23,7 @@
23 23 * THE SOFTWARE.
24 24 */
25 25  
26   -#include "hw.h"
  26 +#include "sysbus.h"
27 27 #include "ppc_mac.h"
28 28 #include "pci.h"
29 29  
... ... @@ -40,7 +40,10 @@
40 40 typedef target_phys_addr_t pci_addr_t;
41 41 #include "pci_host.h"
42 42  
43   -typedef PCIHostState GrackleState;
  43 +typedef struct GrackleState {
  44 + SysBusDevice busdev;
  45 + PCIHostState host_state;
  46 +} GrackleState;
44 47  
45 48 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
46 49 uint32_t val)
... ... @@ -52,7 +55,7 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
52 55 #ifdef TARGET_WORDS_BIGENDIAN
53 56 val = bswap32(val);
54 57 #endif
55   - s->config_reg = val;
  58 + s->host_state.config_reg = val;
56 59 }
57 60  
58 61 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
... ... @@ -60,7 +63,7 @@ static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
60 63 GrackleState *s = opaque;
61 64 uint32_t val;
62 65  
63   - val = s->config_reg;
  66 + val = s->host_state.config_reg;
64 67 #ifdef TARGET_WORDS_BIGENDIAN
65 68 val = bswap32(val);
66 69 #endif
... ... @@ -128,31 +131,76 @@ static void pci_grackle_reset(void *opaque)
128 131  
129 132 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
130 133 {
  134 + DeviceState *dev;
  135 + SysBusDevice *s;
  136 + GrackleState *d;
  137 +
  138 + dev = qdev_create(NULL, "grackle");
  139 + qdev_init(dev);
  140 + s = sysbus_from_qdev(dev);
  141 + d = FROM_SYSBUS(GrackleState, s);
  142 + d->host_state.bus = pci_register_bus(NULL, "pci",
  143 + pci_grackle_set_irq,
  144 + pci_grackle_map_irq,
  145 + pic, 0, 4);
  146 +
  147 + pci_create_simple(d->host_state.bus, 0, "grackle");
  148 +
  149 + sysbus_mmio_map(s, 0, base);
  150 + sysbus_mmio_map(s, 1, base + 0x00200000);
  151 +
  152 + return d->host_state.bus;
  153 +}
  154 +
  155 +static void pci_grackle_init_device(SysBusDevice *dev)
  156 +{
  157 + GrackleState *s;
  158 + int pci_mem_config, pci_mem_data;
  159 +
  160 + s = FROM_SYSBUS(GrackleState, dev);
  161 +
  162 + pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
  163 + pci_grackle_config_write, s);
  164 + pci_mem_data = cpu_register_io_memory(pci_grackle_read,
  165 + pci_grackle_write,
  166 + &s->host_state);
  167 + sysbus_init_mmio(dev, 0x1000, pci_mem_config);
  168 + sysbus_init_mmio(dev, 0x1000, pci_mem_data);
  169 +
  170 + register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,
  171 + &s->host_state);
  172 + qemu_register_reset(pci_grackle_reset, &s->host_state);
  173 + pci_grackle_reset(&s->host_state);
  174 +}
  175 +
  176 +static void pci_dec_21154_init_device(SysBusDevice *dev)
  177 +{
131 178 GrackleState *s;
132   - PCIDevice *d;
133 179 int pci_mem_config, pci_mem_data;
134 180  
135   - s = qemu_mallocz(sizeof(GrackleState));
136   - s->bus = pci_register_bus(NULL, "pci",
137   - pci_grackle_set_irq, pci_grackle_map_irq,
138   - pic, 0, 4);
  181 + s = FROM_SYSBUS(GrackleState, dev);
139 182  
140 183 pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
141 184 pci_grackle_config_write, s);
142 185 pci_mem_data = cpu_register_io_memory(pci_grackle_read,
143   - pci_grackle_write, s);
144   - cpu_register_physical_memory(base, 0x1000, pci_mem_config);
145   - cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
146   - d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
147   - 0, NULL, NULL);
  186 + pci_grackle_write,
  187 + &s->host_state);
  188 + sysbus_init_mmio(dev, 0x1000, pci_mem_config);
  189 + sysbus_init_mmio(dev, 0x1000, pci_mem_data);
  190 +}
  191 +
  192 +static void grackle_pci_host_init(PCIDevice *d)
  193 +{
148 194 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
149 195 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
150 196 d->config[0x08] = 0x00; // revision
151 197 d->config[0x09] = 0x01;
152 198 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
153 199 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
  200 +}
154 201  
155   -#if 0
  202 +static void dec_21154_pci_host_init(PCIDevice *d)
  203 +{
156 204 /* PCI2PCI bridge same values as PearPC - check this */
157 205 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
158 206 pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
... ... @@ -175,10 +223,28 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
175 223 d->config[0x25] = 0x84;
176 224 d->config[0x26] = 0x00; // prefetchable_memory_limit
177 225 d->config[0x27] = 0x85;
178   -#endif
179   - register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
180   - qemu_register_reset(pci_grackle_reset, d);
181   - pci_grackle_reset(d);
  226 +}
  227 +
  228 +static PCIDeviceInfo grackle_pci_host_info = {
  229 + .qdev.name = "grackle",
  230 + .qdev.size = sizeof(PCIDevice),
  231 + .init = grackle_pci_host_init,
  232 +};
182 233  
183   - return s->bus;
  234 +static PCIDeviceInfo dec_21154_pci_host_info = {
  235 + .qdev.name = "DEC 21154",
  236 + .qdev.size = sizeof(PCIDevice),
  237 + .init = dec_21154_pci_host_init,
  238 +};
  239 +
  240 +static void grackle_register_devices(void)
  241 +{
  242 + sysbus_register_dev("grackle", sizeof(GrackleState),
  243 + pci_grackle_init_device);
  244 + pci_qdev_register(&grackle_pci_host_info);
  245 + sysbus_register_dev("DEC 21154", sizeof(GrackleState),
  246 + pci_dec_21154_init_device);
  247 + pci_qdev_register(&dec_21154_pci_host_info);
184 248 }
  249 +
  250 +device_init(grackle_register_devices)
... ...