gwj / at91sam9263 · Commits

Commit 2ca1d92b0785b65c48b415ee9074f3674432edde

Authored by Blue Swirl
1 parent d4b0d468

Convert subx 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 2 changed files with 50 additions and 31 deletions
target-sparc/op_helper.c
  View file @2ca1d92
@@ -972,6 +972,48 @@ static uint32_t compute_C_sub_xcc(void) @@ -972,6 +972,48 @@ static uint32_t compute_C_sub_xcc(void)
972 } 972 }
973 #endif 973 #endif
974 974
  975 +static uint32_t compute_all_subx(void)
  976 +{
  977 + uint32_t ret;
  978 +
  979 + ret = get_NZ_icc(CC_DST);
  980 + ret |= get_C_sub_icc(CC_DST - CC_SRC2, CC_SRC);
  981 + ret |= get_C_sub_icc(CC_DST, CC_SRC2);
  982 + ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
  983 + return ret;
  984 +}
  985 +
  986 +static uint32_t compute_C_subx(void)
  987 +{
  988 + uint32_t ret;
  989 +
  990 + ret = get_C_sub_icc(CC_DST - CC_SRC2, CC_SRC);
  991 + ret |= get_C_sub_icc(CC_DST, CC_SRC2);
  992 + return ret;
  993 +}
  994 +
  995 +#ifdef TARGET_SPARC64
  996 +static uint32_t compute_all_subx_xcc(void)
  997 +{
  998 + uint32_t ret;
  999 +
  1000 + ret = get_NZ_xcc(CC_DST);
  1001 + ret |= get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC);
  1002 + ret |= get_C_sub_xcc(CC_DST, CC_SRC2);
  1003 + ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
  1004 + return ret;
  1005 +}
  1006 +
  1007 +static uint32_t compute_C_subx_xcc(void)
  1008 +{
  1009 + uint32_t ret;
  1010 +
  1011 + ret = get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC);
  1012 + ret |= get_C_sub_xcc(CC_DST, CC_SRC2);
  1013 + return ret;
  1014 +}
  1015 +#endif
  1016 +
975 static uint32_t compute_all_logic(void) 1017 static uint32_t compute_all_logic(void)
976 { 1018 {
977 return get_NZ_icc(CC_DST); 1019 return get_NZ_icc(CC_DST);
@@ -1000,6 +1042,7 @@ static const CCTable icc_table[CC_OP_NB] = { @@ -1000,6 +1042,7 @@ static const CCTable icc_table[CC_OP_NB] = {
1000 [CC_OP_ADD] = { compute_all_add, compute_C_add }, 1042 [CC_OP_ADD] = { compute_all_add, compute_C_add },
1001 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, 1043 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
1002 [CC_OP_SUB] = { compute_all_sub, compute_C_sub }, 1044 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
  1045 + [CC_OP_SUBX] = { compute_all_subx, compute_C_subx },
1003 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, 1046 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
1004 }; 1047 };
1005 1048
@@ -1010,6 +1053,7 @@ static const CCTable xcc_table[CC_OP_NB] = { @@ -1010,6 +1053,7 @@ static const CCTable xcc_table[CC_OP_NB] = {
1010 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, 1053 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
1011 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, 1054 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
1012 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, 1055 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
  1056 + [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
1013 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, 1057 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
1014 }; 1058 };
1015 #endif 1059 #endif
target-sparc/translate.c
  View file @2ca1d92
@@ -635,33 +635,14 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) @@ -635,33 +635,14 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
635 tcg_gen_mov_tl(dst, cpu_cc_dst); 635 tcg_gen_mov_tl(dst, cpu_cc_dst);
636 } 636 }
637 637
638 -static inline void gen_op_subx_cc2(TCGv dst)  
639 -{  
640 - gen_cc_NZ_icc(cpu_cc_dst);  
641 - gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);  
642 - gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);  
643 -#ifdef TARGET_SPARC64  
644 - gen_cc_NZ_xcc(cpu_cc_dst);  
645 - gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);  
646 - gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);  
647 -#endif  
648 - tcg_gen_mov_tl(dst, cpu_cc_dst);  
649 -}  
650 -  
651 static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) 638 static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2)
652 { 639 {
653 tcg_gen_mov_tl(cpu_cc_src, src1); 640 tcg_gen_mov_tl(cpu_cc_src, src1);
654 tcg_gen_movi_tl(cpu_cc_src2, src2); 641 tcg_gen_movi_tl(cpu_cc_src2, src2);
655 gen_mov_reg_C(cpu_tmp0, cpu_psr); 642 gen_mov_reg_C(cpu_tmp0, cpu_psr);
656 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); 643 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
657 - gen_cc_clear_icc();  
658 - gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);  
659 -#ifdef TARGET_SPARC64  
660 - gen_cc_clear_xcc();  
661 - gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);  
662 -#endif  
663 tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); 644 tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2);
664 - gen_op_subx_cc2(dst); 645 + tcg_gen_mov_tl(dst, cpu_cc_dst);
665 } 646 }
666 647
667 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) 648 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -670,14 +651,8 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) @@ -670,14 +651,8 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
670 tcg_gen_mov_tl(cpu_cc_src2, src2); 651 tcg_gen_mov_tl(cpu_cc_src2, src2);
671 gen_mov_reg_C(cpu_tmp0, cpu_psr); 652 gen_mov_reg_C(cpu_tmp0, cpu_psr);
672 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); 653 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
673 - gen_cc_clear_icc();  
674 - gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);  
675 -#ifdef TARGET_SPARC64  
676 - gen_cc_clear_xcc();  
677 - gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);  
678 -#endif  
679 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); 654 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
680 - gen_op_subx_cc2(dst); 655 + tcg_gen_mov_tl(dst, cpu_cc_dst);
681 } 656 }
682 657
683 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) 658 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -3263,8 +3238,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3263,8 +3238,8 @@ static void disas_sparc_insn(DisasContext * dc)
3263 if (xop & 0x10) { 3238 if (xop & 0x10) {
3264 gen_helper_compute_psr(); 3239 gen_helper_compute_psr();
3265 gen_op_subxi_cc(cpu_dst, cpu_src1, simm); 3240 gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
3266 - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);  
3267 - dc->cc_op = CC_OP_FLAGS; 3241 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
  3242 + dc->cc_op = CC_OP_SUBX;
3268 } else { 3243 } else {
3269 gen_helper_compute_psr(); 3244 gen_helper_compute_psr();
3270 gen_mov_reg_C(cpu_tmp0, cpu_psr); 3245 gen_mov_reg_C(cpu_tmp0, cpu_psr);
@@ -3275,8 +3250,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3275,8 +3250,8 @@ static void disas_sparc_insn(DisasContext * dc)
3275 if (xop & 0x10) { 3250 if (xop & 0x10) {
3276 gen_helper_compute_psr(); 3251 gen_helper_compute_psr();
3277 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); 3252 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3278 - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);  
3279 - dc->cc_op = CC_OP_FLAGS; 3253 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
  3254 + dc->cc_op = CC_OP_SUBX;
3280 } else { 3255 } else {
3281 gen_helper_compute_psr(); 3256 gen_helper_compute_psr();
3282 gen_mov_reg_C(cpu_tmp0, cpu_psr); 3257 gen_mov_reg_C(cpu_tmp0, cpu_psr);